diff options
Diffstat (limited to 'gm_platform/fw/adc.c')
| -rw-r--r-- | gm_platform/fw/adc.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/gm_platform/fw/adc.c b/gm_platform/fw/adc.c index ab9d6b5..7e1b8cc 100644 --- a/gm_platform/fw/adc.c +++ b/gm_platform/fw/adc.c @@ -32,12 +32,11 @@ static uint16_t current_seq = 0; static int current_buf = 0; static void adc_dma_init(void); -static void adc_timer_init(int psc, int ivl); static void adc_dma_launch(void); /* Mode that can be used for debugging */ -void adc_configure_scope_mode(int sampling_interval_ns) { +void adc_init() { adc_dma_init(); /* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */ @@ -56,14 +55,6 @@ void adc_configure_scope_mode(int sampling_interval_ns) { /* Enable conversion */ ADC1->CR |= ADC_CR_ADEN; ADC1->CR |= ADC_CR_ADSTART; - - /* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us. - Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this - would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */ - int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6; - if (cycles > 0xffff) - cycles = 0xffff; - adc_timer_init(12/*250ns/tick*/, cycles); } static void adc_dma_init() { @@ -91,8 +82,8 @@ void adc_dma_launch() { DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */ } -static void adc_timer_init(int psc, int ivl) { - TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */ +void adc_timer_init(int psc, int ivl) { + TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal */ TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */ TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */ TIM1->CCR4 = 1; /* Trigger at start of timer cycle */ |