diff options
| -rw-r--r-- | controller/fw/Makefile | 2 | ||||
| -rw-r--r-- | controller/fw/src/adc.c | 19 | ||||
| -rw-r--r-- | controller/fw/src/main.c | 9 |
3 files changed, 20 insertions, 10 deletions
diff --git a/controller/fw/Makefile b/controller/fw/Makefile index 58acf4c..89960d2 100644 --- a/controller/fw/Makefile +++ b/controller/fw/Makefile @@ -121,7 +121,7 @@ CFLAGS += -I$(abspath musl_include_shims) COMMON_CFLAGS += -I$(BUILDDIR) -Isrc -Itinyaes CFLAGS += -I$(CUBE_DIR)/Drivers/CMSIS/Device/ST/STM32F4xx/Include -COMMON_CFLAGS += -Os -std=gnu11 -g -DSTM32F407xx -DSTM32F4 +COMMON_CFLAGS += -O0 -std=gnu11 -g -DSTM32F407xx -DSTM32F4 CFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS) #SIM_CFLAGS += -mthumb -mcpu=cortex-m4 -mfloat-abi=soft CFLAGS += -fno-common -ffunction-sections -fdata-sections diff --git a/controller/fw/src/adc.c b/controller/fw/src/adc.c index 4801525..fba2420 100644 --- a/controller/fw/src/adc.c +++ b/controller/fw/src/adc.c @@ -37,29 +37,30 @@ void adc_init() { while (adc_stream->CR & DMA_SxCR_EN) ; /* wait for stream to become available */ adc_stream->NDTR = FMEAS_FFT_LEN/2; - adc_stream->PAR = ADC1->DR; + adc_stream->PAR = &(ADC1->DR); adc_stream->M0AR = (uint32_t) (adc_fft_buf[0] + FMEAS_FFT_LEN/2); adc_stream->M1AR = (uint32_t) (adc_fft_buf[1] + FMEAS_FFT_LEN/2); adc_stream->CR = (dma_adc_channel<<DMA_SxCR_CHSEL_Pos) | DMA_SxCR_DBM | (1<<DMA_SxCR_MSIZE_Pos) - | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_PFCTRL - | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE | DMA_SxCR_EN; + | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | (2<<DMA_SxCR_PL_Pos) + | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE; adc_stream->CR |= DMA_SxCR_EN; NVIC_EnableIRQ(DMA2_Stream0_IRQn); NVIC_SetPriority(DMA2_Stream0_IRQn, 128); ADC1->CR1 = (0<<ADC_CR1_RES_Pos) | (0<<ADC_CR1_DISCNUM_Pos) | ADC_CR1_DISCEN | (0<<ADC_CR1_AWDCH_Pos); - ADC1->CR2 = ADC_CR2_EXTEN | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS; + ADC1->CR2 = (1<<ADC_CR2_EXTEN_Pos) | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS; ADC1->SQR3 = (adc_channel<<ADC_SQR3_SQ3_Pos); ADC1->SQR1 = (0<<ADC_SQR1_L_Pos); TIM1->CR2 = (2<<TIM_CR2_MMS_Pos); /* Enable update event on TRGO to provide a 1ms reference to rest of system */ - TIM1->CR1 = TIM_CR1_CEN; TIM1->CCMR1 = (6<<TIM_CCMR1_OC1M_Pos) | (0<<TIM_CCMR1_CC1S_Pos); TIM1->CCER = TIM_CCER_CC1E; TIM1->PSC = 84-1; /* 1us ticks @ f_APB2=84MHz */ TIM1->ARR = 1000-1; /* 1ms period */ - TIM1->CCR1 = 1; + TIM1->CCR1 = 500-1; + TIM1->BDTR = TIM_BDTR_MOE; + TIM1->CR1 = TIM_CR1_CEN; TIM1->EGR = TIM_EGR_UG; } @@ -75,14 +76,16 @@ void DMA2_Stream0_IRQHandler(void) { if (mem_stream->CR & DMA_SxCR_EN) panic(); /* We should be long done by now. */ + adc_dma->LIFCR = 0x3d<<DMA_LISR_FEIF1_Pos; mem_stream->NDTR = FMEAS_FFT_LEN/2; int ct = !!(adc_stream->CR & DMA_SxCR_CT); /* back half of old buffer (that was just written) */ - mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct]); + mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct] + FMEAS_FFT_LEN/2); /* front half of current buffer (whose back half is being written now) */ mem_stream->M0AR = (uint32_t) (adc_fft_buf[ct] + 0); + mem_stream->CR = (1<<DMA_SxCR_MSIZE_Pos) | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_PINC - | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE; + | (0<<DMA_SxCR_PL_Pos) | (2<<DMA_SxCR_DIR_Pos); mem_stream->CR |= DMA_SxCR_EN; /* Kickoff FFT */ diff --git a/controller/fw/src/main.c b/controller/fw/src/main.c index 58977f7..4f2d67b 100644 --- a/controller/fw/src/main.c +++ b/controller/fw/src/main.c @@ -96,6 +96,8 @@ static void spi_flash_if_set_cs(bool val) { static void spi_flash_setup(void) { + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; + GPIOB->MODER &= ~GPIO_MODER_MODER3_Msk & ~GPIO_MODER_MODER4_Msk & ~GPIO_MODER_MODER5_Msk & ~GPIO_MODER_MODER0_Msk; GPIOB->MODER |= (2<<GPIO_MODER_MODER3_Pos) /* SCK */ | (2<<GPIO_MODER_MODER4_Pos) /* MISO */ @@ -114,7 +116,7 @@ static void spi_flash_setup(void) RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST; - RCC->APB2RSTR &= RCC_APB2RSTR_SPI1RST; + RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST; spif_init(&spif, 256, SPI1, &spi_flash_if_set_cs); } @@ -142,6 +144,7 @@ void spi_flash_test(void) { static unsigned int measurement_errors = 0; static struct dsss_demod_state demod_state; static uint32_t freq_sample_ts = 0; +static uint32_t debug_last_freq = 0; int main(void) { @@ -152,14 +155,18 @@ int main(void) while (23) { if (adc_fft_buf_ready_idx != -1) { + /* float out; if (adc_buf_measure_freq(adc_fft_buf[adc_fft_buf_ready_idx], &out)) { measurement_errors++; continue; } + debug_last_freq = out; + dsss_demod_init(&demod_state); dsss_demod_step(&demod_state, out, freq_sample_ts); + */ freq_sample_ts++; /* TODO: also increase in case of freq measurement error? */ adc_fft_buf_ready_idx = -1; |