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-rw-r--r--gm_platform/fw/adc.c47
-rw-r--r--gm_platform/fw/crctest.py79
-rwxr-xr-xgm_platform/fw/main.binbin6736 -> 7416 bytes
-rw-r--r--gm_platform/fw/main.c4
-rwxr-xr-xgm_platform/fw/main.elfbin181756 -> 184004 bytes
-rw-r--r--gm_platform/fw/main.hex727
-rw-r--r--gm_platform/fw/main.lst5803
-rw-r--r--gm_platform/fw/main.map464
-rw-r--r--gm_platform/fw/serial.c181
-rw-r--r--gm_platform/fw/serial.h41
10 files changed, 4005 insertions, 3341 deletions
diff --git a/gm_platform/fw/adc.c b/gm_platform/fw/adc.c
index 2a33171..e3aba5b 100644
--- a/gm_platform/fw/adc.c
+++ b/gm_platform/fw/adc.c
@@ -22,16 +22,22 @@
#include <stdlib.h>
#include <assert.h>
-volatile uint16_t adc_buf[100]; /* 100ms worth of data */
-uint32_t usart_overruns = 0;
-
-static void adc_dma_init(int burstlen);
+static struct __attribute__((__packed__)) hl_adc_pkt {
+ struct ll_pkt ll;
+ uint16_t seq;
+ volatile uint16_t data[32];
+} adc_pkt[2];
+static uint16_t current_seq = 0;
+static int current_buf = 0;
+
+static void adc_dma_init(void);
static void adc_timer_init(int psc, int ivl);
+static void adc_dma_launch(void);
/* Mode that can be used for debugging */
void adc_configure_scope_mode(int sampling_interval_ns) {
- adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]));
+ adc_dma_init();
/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
@@ -59,24 +65,28 @@ void adc_configure_scope_mode(int sampling_interval_ns) {
adc_timer_init(12/*250ns/tick*/, cycles);
}
-static void adc_dma_init(int burstlen) {
+static void adc_dma_init() {
/* Configure DMA 1 Channel 1 to get rid of all the data */
DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
- DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
- DMA1_Channel1->CNDTR = burstlen;
DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
DMA1_Channel1->CCR |=
- DMA_CCR_CIRC /* circular mode so we can leave it running indefinitely */
- | (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
+ (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
| DMA_CCR_MINC
- | DMA_CCR_HTIE /* Enable half-transfer interrupt. */
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5);
+ NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
+
+ adc_dma_launch();
+}
+void adc_dma_launch() {
+ DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Disable channel */
+ current_buf = !current_buf;
+ DMA1_Channel1->CMAR = (unsigned int)&(adc_pkt[current_buf].data);
+ DMA1_Channel1->CNDTR = ARRAY_LEN(adc_pkt[current_buf].data);
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
}
@@ -103,18 +113,13 @@ void DMA1_Channel1_IRQHandler(void) {
uint32_t isr = DMA1->ISR;
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
+ adc_dma_launch();
gdb_dump();
- static_assert(ARRAY_LEN(adc_buf) % 2 == 0, "ADC_BUFSIZE must be even for half-transfer uart tx logic to work");
-
- int rc;
- if (isr & DMA_ISR_HTIF2) /* half-transfer */
- rc = usart_send_packet_nonblocking((uint8_t *)adc_buf, sizeof(adc_buf)/2);
- else /* end of transfer */
- rc = usart_send_packet_nonblocking((uint8_t *)adc_buf + ARRAY_LEN(adc_buf)/2, sizeof(adc_buf)/2);
- if (rc)
- usart_overruns++;
+ adc_pkt[!current_buf].seq = current_seq++;
+ /* Ignore return value since we can't do anything here. Overruns are logged in serial.c. */
+ usart_send_packet_nonblocking(&adc_pkt[!current_buf].ll, sizeof(adc_pkt[!current_buf]));
/*
static int debug_buf_pos = 0;
diff --git a/gm_platform/fw/crctest.py b/gm_platform/fw/crctest.py
new file mode 100644
index 0000000..5c97be9
--- /dev/null
+++ b/gm_platform/fw/crctest.py
@@ -0,0 +1,79 @@
+custom_crc_table = {}
+
+def generate_crc32_table(_poly):
+
+ global custom_crc_table
+
+ for i in range(256):
+ c = i << 24
+
+ for j in range(8):
+ c = (c << 1) ^ _poly if (c & 0x80000000) else c << 1
+
+ custom_crc_table[i] = c & 0xffffffff
+
+
+def crc32_stm(bytes_arr):
+
+ length = len(bytes_arr)
+ crc = 0xffffffff
+
+ k = 0
+ while length >= 4:
+
+ v = ((bytes_arr[k] << 24) & 0xFF000000) | ((bytes_arr[k+1] << 16) & 0xFF0000) | \
+ ((bytes_arr[k+2] << 8) & 0xFF00) | (bytes_arr[k+3] & 0xFF)
+
+ crc = ((crc << 8) & 0xffffffff) ^ custom_crc_table[0xFF & ((crc >> 24) ^ v)]
+ crc = ((crc << 8) & 0xffffffff) ^ custom_crc_table[0xFF & ((crc >> 24) ^ (v >> 8))]
+ crc = ((crc << 8) & 0xffffffff) ^ custom_crc_table[0xFF & ((crc >> 24) ^ (v >> 16))]
+ crc = ((crc << 8) & 0xffffffff) ^ custom_crc_table[0xFF & ((crc >> 24) ^ (v >> 24))]
+
+ k += 4
+ length -= 4
+
+ if length > 0:
+ v = 0
+
+ for i in range(length):
+ v |= (bytes_arr[k+i] << 24-i*8)
+
+ if length == 1:
+ v &= 0xFF000000
+
+ elif length == 2:
+ v &= 0xFFFF0000
+
+ elif length == 3:
+ v &= 0xFFFFFF00
+
+ crc = (( crc << 8 ) & 0xffffffff) ^ custom_crc_table[0xFF & ( (crc >> 24) ^ (v ) )];
+ crc = (( crc << 8 ) & 0xffffffff) ^ custom_crc_table[0xFF & ( (crc >> 24) ^ (v >> 8) )];
+ crc = (( crc << 8 ) & 0xffffffff) ^ custom_crc_table[0xFF & ( (crc >> 24) ^ (v >> 16) )];
+ crc = (( crc << 8 ) & 0xffffffff) ^ custom_crc_table[0xFF & ( (crc >> 24) ^ (v >> 24) )];
+
+ return crc
+
+poly = 0x04C11DB7
+buf = bytes(reversed([1, 2, 3, 4]))
+
+generate_crc32_table(poly)
+print(hex(crc32_stm(bytearray(buf))))
+
+from crccheck import crc
+import struct
+
+def rev_bits_in_word(w):
+ return sum( ((w>>i)&1) << (31-i) for i in range(32) )
+
+import zlib
+def crc32stm(inbytes):
+ crc32 = crc.Crc32.calc(inbytes)^0xffffffff
+ #crc32 = zlib.crc32(inbytes)^0xffffffff
+ crc32 = rev_bits_in_word(crc32)
+ return crc32
+
+#data = [0x80,0x40,0xc0,0x20]
+data = [0x00, 0, 0, 0x80, 0, 0, 0, 0x80]
+print(hex(crc32stm(bytes(data))))
+print(hex(zlib.crc32(bytes([0, 0, 0, 1]))^0xffffffff))
diff --git a/gm_platform/fw/main.bin b/gm_platform/fw/main.bin
index 8eea2b7..828a8bd 100755
--- a/gm_platform/fw/main.bin
+++ b/gm_platform/fw/main.bin
Binary files differ
diff --git a/gm_platform/fw/main.c b/gm_platform/fw/main.c
index 3020a42..5741d7c 100644
--- a/gm_platform/fw/main.c
+++ b/gm_platform/fw/main.c
@@ -30,7 +30,7 @@ volatile union {
struct {
unsigned int usb, ocxo, error, _nc1, _nc2, _nc3, pps, sd_card;
};
- unsigned int arr[0];
+ unsigned int arr[8];
} leds;
int main(void) {
@@ -47,7 +47,7 @@ int main(void) {
NVIC_SetPriority(SysTick_IRQn, 3<<5);
/* Turn on lots of neat things */
- RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
+ RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN | RCC_AHBENR_CRCEN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_DBGMCUEN |\
RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
diff --git a/gm_platform/fw/main.elf b/gm_platform/fw/main.elf
index 5b20d44..b7b6067 100755
--- a/gm_platform/fw/main.elf
+++ b/gm_platform/fw/main.elf
Binary files differ
diff --git a/gm_platform/fw/main.hex b/gm_platform/fw/main.hex
index 39c6bb0..d69bcb8 100644
--- a/gm_platform/fw/main.hex
+++ b/gm_platform/fw/main.hex
@@ -1,15 +1,15 @@
:020000040800F2
-:10000000001000205519000885040008910400081C
+:1000000000100020FD1B0008850400089104000872
:1000100000000000000000000000000000000000E0
:10002000000000000000000000000000950400082F
:100030000000000000000000A1040008AD0400085A
-:10004000A119000800000000A1190008A11900086A
-:10005000A1190008A1190008A1190008A119000898
-:100060000000000063070008A90A0008A1190008A1
-:10007000A1190008A1190008A1190008000000003A
-:10008000A11900080000000000000000A1190008EC
-:1000900000000000C9030008A1190008A119000808
-:1000A000000000009D03000800000000A1190008E6
+:10004000491C000800000000491C0008491C000869
+:10005000491C0008491C0008491C0008491C0008EC
+:10006000000000009B070008D10C0008491C000894
+:10007000491C0008491C0008491C00080000000039
+:10008000491C00080000000000000000491C000896
+:1000900000000000C9030008491C0008491C0008B2
+:1000A000000000009D03000800000000290A00086D
:1000B0000000000000000000000000000000000040
:1000C00080B582B000AF0200FB1D1A70FB1D1B78CB
:1000D0001A001F231A40044B012191400A001A60A4
@@ -38,8 +38,8 @@
:100240004B490A405A60494B5A68484B8821490338
:100250000A435A60454B1A68444B802149040A43BB
:100260001A60C046414B1A6880239B041340F9D0A2
-:100270003E4B5A683D4B02210A435A6000F072FE21
-:100280003C4B1B680A21180001F0EEF9030018002E
+:100270003E4B5A683D4B02210A435A6000F0C6FFCC
+:100280003C4B1B680A21180001F042FB03001800D8
:10029000FFF79AFF01235B421800FFF711FF0123CC
:1002A0005B4260211800FFF721FF304B5A692F4B4A
:1002B00031490A435A612D4B9A692C4B2F490A4305
@@ -53,8 +53,8 @@
:10033000DDFE174B00225A60154B0122DA60144B88
:100340002F229A62124B134ADA62114B01221A6071
:100350001520FFF7B5FE40211520FFF7C7FE0E4B15
-:10036000180000F045F900F0CDFAFEE70010024059
-:100370000CF8C3FF0000002011000600015A4200E3
+:10036000180000F045F900F0F5FAFEE70010024031
+:100370000CF8C3FF0000002051000600015A4200A3
:1003800070A92800808A080000040048003001405D
:1003900000440140E703000040420F0080B500AF79
:1003A000084B9B680222134009D09023DB050822EA
@@ -70,14 +70,14 @@
:1004400011600A2B10D10C4B00221A600B4AFB1DC5
:100450001B7813700A4B5A68094B80210A435A6073
:100460009023DB0508229A62C046BD4602B080BDDB
-:1004700000440140B0000020980000200C300140F2
+:100470000044014078010020980000200C30014029
:100480000030014080B500AF00BEC046BD4680BD13
:1004900000BEC04680B500AF00BEC046BD4680BDB0
:1004A00080B500AF00BEC046BD4680BD80B500AF80
:1004B0000A4B1B68591C094A11600A2B0AD1074BC9
:1004C00000221A60064B1B685A1C054B1A60054B2C
:1004D00064229A61C046BD4680BDC0469C00002093
-:1004E00094000020B000002080B582B000AF020070
+:1004E000940000207801002080B582B000AF0200A7
:1004F000FB1D1A70FB1D1B781A001F231A40044BAA
:10050000012191400A001A60C046BD4602B080BD7C
:1005100000E100E090B583B000AF02003960FB1D40
@@ -94,332 +94,375 @@
:1005C000FB1D1B78180003230340DB009A400748FB
:1005D000FB1D1B785BB29B080A43C0339B001A507B
:1005E000C046BD4603B090BD00ED00E000E100E074
-:1005F00080B584B000AF7860202000F04BF8214B2C
-:10060000802212061A611F4B07225A611D4B1E4A97
-:10061000DA601C4B04229A621A4B9A68194B8021AB
-:1006200009060A439A60C046164B9B68002BFBDB09
-:10063000144B9A68134B01210A439A60114B9A6834
-:10064000104B04210A439A607B68104A934206DDEE
-:100650007B68FA21180001F091F8030000E00623FE
-:10066000FB60FA6880235B029A4201DB084BFB6067
-:10067000FB6819000C2000F03DF8C046BD4604B0F0
-:1006800080BDC0460024014043080000DC05000096
-:10069000FFFF000080B582B000AF7860114B124AB6
-:1006A0009A60104B114ADA600E4B7A685A600D4B13
-:1006B00000221A600B4B1A680A4B0D490A431A6054
-:1006C0000920FFF711FF60210920FFF723FF054BE9
-:1006D0001A68044B01210A431A60C046BD4602B0A5
-:1006E00080BDC0460800024040240140D0000020E8
-:1006F000A605000080B582B000AF78603960154B68
-:10070000802212025A64134BC022D201DA61114BCB
-:10071000802252011A620F4B01221A647B685A1E12
-:100720000C4B9A623B685A1E0A4BDA62094B5A69B3
-:10073000084B01210A435A61064B80221A60054B7F
-:100740001A68044B01210A431A60C046BD4602B034
-:1007500080BDC046002C014080B500AFC046BD46FC
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diff --git a/gm_platform/fw/main.lst b/gm_platform/fw/main.lst
index caf6805..1958b70 100644
--- a/gm_platform/fw/main.lst
+++ b/gm_platform/fw/main.lst
@@ -15,178 +15,185 @@ SYMBOL TABLE:
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_ranges 00000000 .debug_ranges
-00000000 l df *ABS* 00000000 /tmp/ccr2qryM.o
-08001964 l .text 00000000 LoopCopyDataInit
-0800195c l .text 00000000 CopyDataInit
-08001978 l .text 00000000 LoopFillZerobss
-08001972 l .text 00000000 FillZerobss
-08001986 l .text 00000000 LoopForever
-080019a0 l .text 00000000 Infinite_Loop
+00000000 l df *ABS* 00000000 /tmp/ccjaIjJQ.o
+08001c0c l .text 00000000 LoopCopyDataInit
+08001c04 l .text 00000000 CopyDataInit
+08001c20 l .text 00000000 LoopFillZerobss
+08001c1a l .text 00000000 FillZerobss
+08001c2e l .text 00000000 LoopForever
+08001c48 l .text 00000000 Infinite_Loop
00000000 l df *ABS* 00000000 main.c
080000c0 l F .text 0000002c NVIC_EnableIRQ
080000ec l F .text 000000dc NVIC_SetPriority
080001c8 l F .text 00000048 SysTick_Config
-20000098 l .bss 00000004 leds_update_counter.5780
-2000009c l .bss 00000004 n.5803
+20000098 l .bss 00000004 leds_update_counter.5792
+2000009c l .bss 00000004 n.5815
00000000 l df *ABS* 00000000 adc.c
080004e8 l F .text 0000002c NVIC_EnableIRQ
08000514 l F .text 000000dc NVIC_SetPriority
-08000694 l F .text 00000060 adc_dma_init
-080006f4 l F .text 00000064 adc_timer_init
-08000758 l F .text 0000000a gdb_dump
+200000a0 l .bss 00000090 adc_pkt
+20000130 l .bss 00000002 current_seq
+20000134 l .bss 00000004 current_buf
+08000690 l F .text 00000040 adc_dma_init
+0800072c l F .text 00000064 adc_timer_init
+080006d0 l F .text 0000005c adc_dma_launch
+08000790 l F .text 0000000a gdb_dump
00000000 l df *ABS* 00000000 serial.c
-080007cc l F .text 0000002c NVIC_EnableIRQ
-080007f8 l F .text 00000030 NVIC_DisableIRQ
-08000828 l F .text 000000dc NVIC_SetPriority
-08000984 l F .text 00000074 usart_schedule_dma
-200000a4 l .bss 00000001 x.6221
+0800081c l F .text 0000002c NVIC_EnableIRQ
+08000848 l F .text 00000030 NVIC_DisableIRQ
+08000878 l F .text 000000dc NVIC_SetPriority
+20000138 l .bss 00000004 tx_overruns
+2000013c l .bss 00000004 rx_overruns
+20000140 l .bss 00000004 rx_framing_errors
+20000144 l .bss 00000004 rx_protocol_errors
+20000148 l .bss 00000008 cobs_state
+20000150 l .bss 00000020 rx_buf
+08000d10 l F .text 000000ac usart_retransmit_packet
+08000b50 l F .text 00000074 usart_schedule_dma
+08000ca8 l F .text 00000028 usart_putc_nonblocking
00000000 l df *ABS* 00000000 cobs.c
00000000 l df *ABS* 00000000 system_stm32f0xx.c
00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c
-08001050 l F .text 0000001c LL_RCC_HSE_EnableBypass
-0800106c l F .text 00000020 LL_RCC_HSE_DisableBypass
-0800108c l F .text 0000001c LL_RCC_HSE_Enable
-080010a8 l F .text 00000028 LL_RCC_HSE_IsReady
-080010d0 l F .text 0000001c LL_RCC_HSI_Enable
-080010ec l F .text 00000020 LL_RCC_HSI_IsReady
-0800110c l F .text 00000028 LL_RCC_SetSysClkSource
-08001134 l F .text 00000018 LL_RCC_GetSysClkSource
-0800114c l F .text 00000028 LL_RCC_SetAHBPrescaler
-08001174 l F .text 0000002c LL_RCC_SetAPB1Prescaler
-080011a0 l F .text 0000001c LL_RCC_PLL_Enable
-080011bc l F .text 00000028 LL_RCC_PLL_IsReady
-080011e4 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
-08001230 l F .text 00000034 LL_InitTick
-08001264 l F .text 00000028 LL_FLASH_SetLatency
-0800128c l F .text 00000018 LL_FLASH_GetLatency
-080014e6 l F .text 00000026 UTILS_PLL_IsBusy
-080014ac l F .text 0000003a UTILS_GetPLLOutputFrequency
-0800150c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
-08001450 l F .text 0000005c UTILS_SetFlashLatency
+080012f8 l F .text 0000001c LL_RCC_HSE_EnableBypass
+08001314 l F .text 00000020 LL_RCC_HSE_DisableBypass
+08001334 l F .text 0000001c LL_RCC_HSE_Enable
+08001350 l F .text 00000028 LL_RCC_HSE_IsReady
+08001378 l F .text 0000001c LL_RCC_HSI_Enable
+08001394 l F .text 00000020 LL_RCC_HSI_IsReady
+080013b4 l F .text 00000028 LL_RCC_SetSysClkSource
+080013dc l F .text 00000018 LL_RCC_GetSysClkSource
+080013f4 l F .text 00000028 LL_RCC_SetAHBPrescaler
+0800141c l F .text 0000002c LL_RCC_SetAPB1Prescaler
+08001448 l F .text 0000001c LL_RCC_PLL_Enable
+08001464 l F .text 00000028 LL_RCC_PLL_IsReady
+0800148c l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
+080014d8 l F .text 00000034 LL_InitTick
+0800150c l F .text 00000028 LL_FLASH_SetLatency
+08001534 l F .text 00000018 LL_FLASH_GetLatency
+0800178e l F .text 00000026 UTILS_PLL_IsBusy
+08001754 l F .text 0000003a UTILS_GetPLLOutputFrequency
+080017b4 l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
+080016f8 l F .text 0000005c UTILS_SetFlashLatency
00000000 l df *ABS* 00000000 base.c
00000000 l df *ABS* 00000000 cmsis_exports.c
00000000 l df *ABS* 00000000 _udivsi3.o
-08001668 l .text 00000000 .udivsi3_skip_div0_test
+08001910 l .text 00000000 .udivsi3_skip_div0_test
00000000 l df *ABS* 00000000 _divsi3.o
-0800177c l .text 00000000 .divsi3_skip_div0_test
+08001a24 l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
-080019b4 g O .text 00000008 APBPrescTable
+08001c5c g O .text 00000008 APBPrescTable
20000044 g O .data 00000004 tim17
2000007c g O .data 00000004 gpioc
20000088 g O .data 00000004 scb
-080012c2 g F .text 00000046 LL_mDelay
-08000ae8 g F .text 00000034 usart_send_packet
-080019a0 w F .text 00000002 TIM1_CC_IRQHandler
-080015e4 g F .text 0000000a __sinit
+0800156a g F .text 00000046 LL_mDelay
+08001c48 w F .text 00000002 TIM1_CC_IRQHandler
+0800188c g F .text 0000000a __sinit
08000490 g F .text 00000004 HardFault_Handler
2000006c g O .data 00000004 rcc
-200000a0 g O .bss 00000004 usart_overruns
080004ac g F .text 0000003c SysTick_Handler
-080019bc g .text 00000000 _sidata
+08001c64 g .text 00000000 _sidata
080004a0 g F .text 0000000c PendSV_Handler
20000020 g O .data 00000004 syscfg
08000484 g F .text 0000000c NMI_Handler
-2000051c g .bss 00000000 __exidx_end
-08001324 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
-080019a0 w F .text 00000002 I2C1_IRQHandler
-08001308 g F .text 0000001c LL_SetSystemCoreClock
-200000a8 g O .bss 00000004 __errno
+200003b8 g .bss 00000000 __exidx_end
+080015cc g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
+08001c48 w F .text 00000002 I2C1_IRQHandler
+080015b0 g F .text 0000001c LL_SetSystemCoreClock
+20000170 g O .bss 00000004 __errno
20000008 g O .data 00000004 tim14
20000048 g O .data 00000004 dbgmcu
2000003c g O .data 00000004 usart1
-080019bc g .text 00000000 _etext
+08001c64 g .text 00000000 _etext
20000094 g .bss 00000000 _sbss
-08000cf4 g F .text 000000d6 cobs_decode
-20000110 g O .bss 0000040c usart_tx_buf
+08000f9a g F .text 000000d6 cobs_decode
+20000198 g O .bss 00000220 usart_tx_buf
20000094 g O .bss 00000004 sys_time_seconds
20000000 g O .data 00000004 SystemCoreClock
2000001c g O .data 00000004 pwr
-08001668 g F .text 0000010a .hidden __udivsi3
-08001652 g F .text 00000014 __assert_func
+08001910 g F .text 0000010a .hidden __udivsi3
+080018fa g F .text 00000014 __assert_func
20000000 g .data 00000000 _sdata
0800039c g F .text 0000002c SPI1_IRQHandler
20000060 g O .data 00000004 dma1_channel5
20000058 g O .data 00000004 dma1_channel3
-2000051c g .bss 00000000 __exidx_start
-080012a4 g F .text 0000001e LL_Init1msTick
+200003b8 g .bss 00000000 __exidx_start
+0800154c g F .text 0000001e LL_Init1msTick
20000054 g O .data 00000004 dma1_channel2
-080019a0 w F .text 00000002 EXTI2_3_IRQHandler
-080019a0 w F .text 00000002 ADC1_IRQHandler
-08000de6 g F .text 000000e2 cobs_decode_incremental
+08001c48 w F .text 00000002 EXTI2_3_IRQHandler
+08001c48 w F .text 00000002 ADC1_IRQHandler
+0800108c g F .text 000000e2 cobs_decode_incremental
2000004c g O .data 00000004 dma1
-080019a0 w F .text 00000002 TIM17_IRQHandler
-080019a0 w F .text 00000002 RTC_IRQHandler
-2000051c g .bss 00000000 _ebss
+08001c48 w F .text 00000002 TIM17_IRQHandler
+08001c48 w F .text 00000002 RTC_IRQHandler
+200003b8 g .bss 00000000 _ebss
2000002c g O .data 00000004 adc1_common
-08001954 w F .text 00000034 Reset_Handler
+08001bfc w F .text 00000034 Reset_Handler
20000070 g O .data 00000004 crc
20000024 g O .data 00000004 exti
08000210 g F .text 0000000a update_leds
20000028 g O .data 00000004 adc1
-0800177c g F .text 00000000 .hidden __aeabi_idiv
-08000b70 g F .text 000000c6 cobs_encode
-200000b0 g O .bss 00000020 leds
+08001a24 g F .text 00000000 .hidden __aeabi_idiv
+20000178 g O .bss 00000020 leds
20000074 g O .data 00000004 gpioa
080003c8 g F .text 000000bc TIM16_IRQHandler
-080019a0 w F .text 00000002 TIM3_IRQHandler
-080019a0 w F .text 00000002 EXTI4_15_IRQHandler
-080019a0 w F .text 00000002 RCC_IRQHandler
-08000b1c g F .text 00000054 usart_send_packet_nonblocking
+08001c48 w F .text 00000002 TIM3_IRQHandler
+08001c48 w F .text 00000002 EXTI4_15_IRQHandler
+08001c48 w F .text 00000002 RCC_IRQHandler
+08000dbc g F .text 00000120 usart_send_packet_nonblocking
20000094 g .bss 00000000 _bss
-08000762 g F .text 0000006a DMA1_Channel1_IRQHandler
-080019a0 g .text 00000002 Default_Handler
-080019a4 g O .text 00000010 AHBPrescTable
-08000c36 g F .text 000000be cobs_encode_usart
+0800079a g F .text 00000082 DMA1_Channel1_IRQHandler
+08001c48 g .text 00000002 Default_Handler
+08001c4c g O .text 00000010 AHBPrescTable
+08000edc g F .text 000000be cobs_encode_usart
20000010 g O .data 00000004 wwdg
-080019a0 w F .text 00000002 TIM14_IRQHandler
-080019a0 w F .text 00000002 DMA1_Channel4_5_IRQHandler
+08001c48 w F .text 00000002 TIM14_IRQHandler
+08001c48 w F .text 00000002 DMA1_Channel4_5_IRQHandler
20000030 g O .data 00000004 adc
-08000a50 g F .text 00000030 usart_putc
-080019a0 w F .text 00000002 EXTI0_1_IRQHandler
-08001950 w F .text 00000002 .hidden __aeabi_ldiv0
+08000c78 g F .text 00000030 usart_putc
+08001c48 w F .text 00000002 EXTI0_1_IRQHandler
+08001bf8 w F .text 00000002 .hidden __aeabi_ldiv0
20000004 g O .data 00000004 tim3
2000000c g O .data 00000004 rtc
-08000904 g F .text 00000080 usart_dma_init
-080015ee g F .text 0000003a memset
+08000954 g F .text 000000d4 usart_dma_init
+08001896 g F .text 0000003a memset
+08000bc4 g F .text 0000003c usart_ack_packet
0800021a g F .text 00000182 main
20000064 g O .data 00000004 flash
-08001668 g F .text 00000000 .hidden __aeabi_uidiv
+08001910 g F .text 00000000 .hidden __aeabi_uidiv
08000494 g F .text 0000000c SVC_Handler
20000018 g O .data 00000004 i2c1
20000050 g O .data 00000004 dma1_channel1
-0800177c g F .text 000001cc .hidden __divsi3
+08001a24 g F .text 000001cc .hidden __divsi3
20000090 g O .data 00000004 nvic
-08000edc g F .text 00000088 SystemInit
-08000a80 g F .text 00000028 usart_putc_nonblocking
-200000ac g O .bss 00000004 _impure_ptr
-080019a0 w F .text 00000002 WWDG_IRQHandler
+08001184 g F .text 00000088 SystemInit
+20000174 g O .bss 00000004 _impure_ptr
+08001c48 w F .text 00000002 WWDG_IRQHandler
20000000 g .data 00000000 _data
20000084 g O .data 00000004 gpiof
-08000aa8 g F .text 00000040 DMA1_Channel2_3_IRQHandler
-200000d0 g O .bss 00000040 adc_buf
+08000cd0 g F .text 00000040 DMA1_Channel2_3_IRQHandler
20000080 g O .data 00000004 gpiod
20001000 g *ABS* 00000000 _estack
-08001774 g F .text 00000008 .hidden __aeabi_uidivmod
+08001a1c g F .text 00000008 .hidden __aeabi_uidivmod
20000068 g O .data 00000004 ob
20000094 g .data 00000000 _edata
20000038 g O .data 00000004 spi1
-080009f8 g F .text 00000058 usart_dma_fifo_push
+08000c00 g F .text 00000078 usart_dma_fifo_push
2000005c g O .data 00000004 dma1_channel4
08000000 g O .isr_vector 00000000 g_pfnVectors
-08000f64 g F .text 000000ec SystemCoreClockUpdate
-080013b0 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
-08001950 w F .text 00000002 .hidden __aeabi_idiv0
+0800120c g F .text 000000ec SystemCoreClockUpdate
+08001658 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
+08001bf8 w F .text 00000002 .hidden __aeabi_idiv0
20000014 g O .data 00000004 iwdg
-080019a0 w F .text 00000002 FLASH_IRQHandler
-08000dca g F .text 0000001c cobs_decode_incremental_initialize
-080019a0 w F .text 00000002 USART1_IRQHandler
-080005f0 g F .text 000000a4 adc_configure_scope_mode
-08001628 g F .text 0000002a strlen
-080019a0 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
+08001c48 w F .text 00000002 FLASH_IRQHandler
+08001070 g F .text 0000001c cobs_decode_incremental_initialize
+08000a28 g F .text 00000128 USART1_IRQHandler
+080005f0 g F .text 000000a0 adc_configure_scope_mode
+080018d0 g F .text 0000002a strlen
+08001c48 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
20000078 g O .data 00000004 gpiob
20000034 g O .data 00000004 tim1
2000008c g O .data 00000004 systick
-08001948 g F .text 00000008 .hidden __aeabi_idivmod
+08001bf0 g F .text 00000008 .hidden __aeabi_idivmod
20000040 g O .data 00000004 tim16
@@ -428,7 +435,7 @@ void update_leds() {
0800021a <main>:
unsigned int usb, ocxo, error, _nc1, _nc2, _nc3, pps, sd_card;
};
- unsigned int arr[0];
+ unsigned int arr[8];
} leds;
int main(void) {
@@ -489,13 +496,13 @@ int main(void) {
8000278: 430a orrs r2, r1
800027a: 605a str r2, [r3, #4]
SystemCoreClockUpdate();
- 800027c: f000 fe72 bl 8000f64 <SystemCoreClockUpdate>
+ 800027c: f000 ffc6 bl 800120c <SystemCoreClockUpdate>
SysTick_Config(SystemCoreClock/10); /* 100ms interval */
8000280: 4b3c ldr r3, [pc, #240] ; (8000374 <main+0x15a>)
8000282: 681b ldr r3, [r3, #0]
8000284: 210a movs r1, #10
8000286: 0018 movs r0, r3
- 8000288: f001 f9ee bl 8001668 <__udivsi3>
+ 8000288: f001 fb42 bl 8001910 <__udivsi3>
800028c: 0003 movs r3, r0
800028e: 0018 movs r0, r3
8000290: f7ff ff9a bl 80001c8 <SysTick_Config>
@@ -512,7 +519,7 @@ int main(void) {
80002a6: f7ff ff21 bl 80000ec <NVIC_SetPriority>
/* Turn on lots of neat things */
- RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
+ RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN | RCC_AHBENR_CRCEN;
80002aa: 4b30 ldr r3, [pc, #192] ; (800036c <main+0x152>)
80002ac: 695a ldr r2, [r3, #20]
80002ae: 4b2f ldr r3, [pc, #188] ; (800036c <main+0x152>)
@@ -647,14 +654,14 @@ int main(void) {
8000362: f000 f945 bl 80005f0 <adc_configure_scope_mode>
usart_dma_init();
- 8000366: f000 facd bl 8000904 <usart_dma_init>
+ 8000366: f000 faf5 bl 8000954 <usart_dma_init>
while (42) {
800036a: e7fe b.n 800036a <main+0x150>
800036c: 40021000 .word 0x40021000
8000370: ffc3f80c .word 0xffc3f80c
8000374: 20000000 .word 0x20000000
- 8000378: 00060011 .word 0x00060011
+ 8000378: 00060051 .word 0x00060051
800037c: 00425a01 .word 0x00425a01
8000380: 0028a970 .word 0x0028a970
8000384: 00088a80 .word 0x00088a80
@@ -813,7 +820,7 @@ void TIM16_IRQHandler(void) {
800046c: b002 add sp, #8
800046e: bd80 pop {r7, pc}
8000470: 40014400 .word 0x40014400
- 8000474: 200000b0 .word 0x200000b0
+ 8000474: 20000178 .word 0x20000178
8000478: 20000098 .word 0x20000098
800047c: 4001300c .word 0x4001300c
8000480: 40013000 .word 0x40013000
@@ -900,7 +907,7 @@ void SysTick_Handler(void) {
80004da: 46c0 nop ; (mov r8, r8)
80004dc: 2000009c .word 0x2000009c
80004e0: 20000094 .word 0x20000094
- 80004e4: 200000b0 .word 0x200000b0
+ 80004e4: 20000178 .word 0x20000178
080004e8 <NVIC_EnableIRQ>:
{
@@ -1049,8 +1056,8 @@ void SysTick_Handler(void) {
80005ec: e000e100 .word 0xe000e100
080005f0 <adc_configure_scope_mode>:
-static void adc_dma_init(int burstlen);
static void adc_timer_init(int psc, int ivl);
+static void adc_dma_launch(void);
/* Mode that can be used for debugging */
@@ -1059,3529 +1066,3915 @@ void adc_configure_scope_mode(int sampling_interval_ns) {
80005f2: b084 sub sp, #16
80005f4: af00 add r7, sp, #0
80005f6: 6078 str r0, [r7, #4]
- adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]));
- 80005f8: 2020 movs r0, #32
- 80005fa: f000 f84b bl 8000694 <adc_dma_init>
+ adc_dma_init();
+ 80005f8: f000 f84a bl 8000690 <adc_dma_init>
/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
- 80005fe: 4b21 ldr r3, [pc, #132] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000600: 2280 movs r2, #128 ; 0x80
- 8000602: 0612 lsls r2, r2, #24
- 8000604: 611a str r2, [r3, #16]
+ 80005fc: 4b20 ldr r3, [pc, #128] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 80005fe: 2280 movs r2, #128 ; 0x80
+ 8000600: 0612 lsls r2, r2, #24
+ 8000602: 611a str r2, [r3, #16]
/* Sampling time 239.5 ADC clock cycles -> total conversion time 38.5us*/
ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos);
- 8000606: 4b1f ldr r3, [pc, #124] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000608: 2207 movs r2, #7
- 800060a: 615a str r2, [r3, #20]
+ 8000604: 4b1e ldr r3, [pc, #120] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000606: 2207 movs r2, #7
+ 8000608: 615a str r2, [r3, #20]
/* Setup DMA and triggering */
/* Trigger from TIM1 TRGO */
ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
- 800060c: 4b1d ldr r3, [pc, #116] ; (8000684 <adc_configure_scope_mode+0x94>)
- 800060e: 4a1e ldr r2, [pc, #120] ; (8000688 <adc_configure_scope_mode+0x98>)
- 8000610: 60da str r2, [r3, #12]
+ 800060a: 4b1d ldr r3, [pc, #116] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 800060c: 4a1d ldr r2, [pc, #116] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800060e: 60da str r2, [r3, #12]
ADC1->CHSELR = ADC_CHSELR_CHSEL2;
- 8000612: 4b1c ldr r3, [pc, #112] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000614: 2204 movs r2, #4
- 8000616: 629a str r2, [r3, #40] ; 0x28
+ 8000610: 4b1b ldr r3, [pc, #108] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000612: 2204 movs r2, #4
+ 8000614: 629a str r2, [r3, #40] ; 0x28
/* Perform self-calibration */
ADC1->CR |= ADC_CR_ADCAL;
- 8000618: 4b1a ldr r3, [pc, #104] ; (8000684 <adc_configure_scope_mode+0x94>)
- 800061a: 689a ldr r2, [r3, #8]
- 800061c: 4b19 ldr r3, [pc, #100] ; (8000684 <adc_configure_scope_mode+0x94>)
- 800061e: 2180 movs r1, #128 ; 0x80
- 8000620: 0609 lsls r1, r1, #24
- 8000622: 430a orrs r2, r1
- 8000624: 609a str r2, [r3, #8]
+ 8000616: 4b1a ldr r3, [pc, #104] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000618: 689a ldr r2, [r3, #8]
+ 800061a: 4b19 ldr r3, [pc, #100] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 800061c: 2180 movs r1, #128 ; 0x80
+ 800061e: 0609 lsls r1, r1, #24
+ 8000620: 430a orrs r2, r1
+ 8000622: 609a str r2, [r3, #8]
while (ADC1->CR & ADC_CR_ADCAL)
- 8000626: 46c0 nop ; (mov r8, r8)
- 8000628: 4b16 ldr r3, [pc, #88] ; (8000684 <adc_configure_scope_mode+0x94>)
- 800062a: 689b ldr r3, [r3, #8]
- 800062c: 2b00 cmp r3, #0
- 800062e: dbfb blt.n 8000628 <adc_configure_scope_mode+0x38>
+ 8000624: 46c0 nop ; (mov r8, r8)
+ 8000626: 4b16 ldr r3, [pc, #88] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000628: 689b ldr r3, [r3, #8]
+ 800062a: 2b00 cmp r3, #0
+ 800062c: dbfb blt.n 8000626 <adc_configure_scope_mode+0x36>
;
/* Enable conversion */
ADC1->CR |= ADC_CR_ADEN;
- 8000630: 4b14 ldr r3, [pc, #80] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000632: 689a ldr r2, [r3, #8]
- 8000634: 4b13 ldr r3, [pc, #76] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000636: 2101 movs r1, #1
- 8000638: 430a orrs r2, r1
- 800063a: 609a str r2, [r3, #8]
+ 800062e: 4b14 ldr r3, [pc, #80] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000630: 689a ldr r2, [r3, #8]
+ 8000632: 4b13 ldr r3, [pc, #76] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000634: 2101 movs r1, #1
+ 8000636: 430a orrs r2, r1
+ 8000638: 609a str r2, [r3, #8]
ADC1->CR |= ADC_CR_ADSTART;
- 800063c: 4b11 ldr r3, [pc, #68] ; (8000684 <adc_configure_scope_mode+0x94>)
- 800063e: 689a ldr r2, [r3, #8]
- 8000640: 4b10 ldr r3, [pc, #64] ; (8000684 <adc_configure_scope_mode+0x94>)
- 8000642: 2104 movs r1, #4
- 8000644: 430a orrs r2, r1
- 8000646: 609a str r2, [r3, #8]
+ 800063a: 4b11 ldr r3, [pc, #68] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 800063c: 689a ldr r2, [r3, #8]
+ 800063e: 4b10 ldr r3, [pc, #64] ; (8000680 <adc_configure_scope_mode+0x90>)
+ 8000640: 2104 movs r1, #4
+ 8000642: 430a orrs r2, r1
+ 8000644: 609a str r2, [r3, #8]
/* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us.
Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this
would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */
int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6;
- 8000648: 687b ldr r3, [r7, #4]
- 800064a: 4a10 ldr r2, [pc, #64] ; (800068c <adc_configure_scope_mode+0x9c>)
- 800064c: 4293 cmp r3, r2
- 800064e: dd06 ble.n 800065e <adc_configure_scope_mode+0x6e>
- 8000650: 687b ldr r3, [r7, #4]
- 8000652: 21fa movs r1, #250 ; 0xfa
- 8000654: 0018 movs r0, r3
- 8000656: f001 f891 bl 800177c <__divsi3>
- 800065a: 0003 movs r3, r0
- 800065c: e000 b.n 8000660 <adc_configure_scope_mode+0x70>
- 800065e: 2306 movs r3, #6
- 8000660: 60fb str r3, [r7, #12]
+ 8000646: 687b ldr r3, [r7, #4]
+ 8000648: 4a0f ldr r2, [pc, #60] ; (8000688 <adc_configure_scope_mode+0x98>)
+ 800064a: 4293 cmp r3, r2
+ 800064c: dd06 ble.n 800065c <adc_configure_scope_mode+0x6c>
+ 800064e: 687b ldr r3, [r7, #4]
+ 8000650: 21fa movs r1, #250 ; 0xfa
+ 8000652: 0018 movs r0, r3
+ 8000654: f001 f9e6 bl 8001a24 <__divsi3>
+ 8000658: 0003 movs r3, r0
+ 800065a: e000 b.n 800065e <adc_configure_scope_mode+0x6e>
+ 800065c: 2306 movs r3, #6
+ 800065e: 60fb str r3, [r7, #12]
if (cycles > 0xffff)
- 8000662: 68fa ldr r2, [r7, #12]
- 8000664: 2380 movs r3, #128 ; 0x80
- 8000666: 025b lsls r3, r3, #9
- 8000668: 429a cmp r2, r3
- 800066a: db01 blt.n 8000670 <adc_configure_scope_mode+0x80>
+ 8000660: 68fa ldr r2, [r7, #12]
+ 8000662: 2380 movs r3, #128 ; 0x80
+ 8000664: 025b lsls r3, r3, #9
+ 8000666: 429a cmp r2, r3
+ 8000668: db01 blt.n 800066e <adc_configure_scope_mode+0x7e>
cycles = 0xffff;
- 800066c: 4b08 ldr r3, [pc, #32] ; (8000690 <adc_configure_scope_mode+0xa0>)
- 800066e: 60fb str r3, [r7, #12]
+ 800066a: 4b08 ldr r3, [pc, #32] ; (800068c <adc_configure_scope_mode+0x9c>)
+ 800066c: 60fb str r3, [r7, #12]
adc_timer_init(12/*250ns/tick*/, cycles);
- 8000670: 68fb ldr r3, [r7, #12]
- 8000672: 0019 movs r1, r3
- 8000674: 200c movs r0, #12
- 8000676: f000 f83d bl 80006f4 <adc_timer_init>
+ 800066e: 68fb ldr r3, [r7, #12]
+ 8000670: 0019 movs r1, r3
+ 8000672: 200c movs r0, #12
+ 8000674: f000 f85a bl 800072c <adc_timer_init>
}
- 800067a: 46c0 nop ; (mov r8, r8)
- 800067c: 46bd mov sp, r7
- 800067e: b004 add sp, #16
- 8000680: bd80 pop {r7, pc}
- 8000682: 46c0 nop ; (mov r8, r8)
- 8000684: 40012400 .word 0x40012400
- 8000688: 00000843 .word 0x00000843
- 800068c: 000005dc .word 0x000005dc
- 8000690: 0000ffff .word 0x0000ffff
-
-08000694 <adc_dma_init>:
-
-static void adc_dma_init(int burstlen) {
- 8000694: b580 push {r7, lr}
- 8000696: b082 sub sp, #8
- 8000698: af00 add r7, sp, #0
- 800069a: 6078 str r0, [r7, #4]
+ 8000678: 46c0 nop ; (mov r8, r8)
+ 800067a: 46bd mov sp, r7
+ 800067c: b004 add sp, #16
+ 800067e: bd80 pop {r7, pc}
+ 8000680: 40012400 .word 0x40012400
+ 8000684: 00000843 .word 0x00000843
+ 8000688: 000005dc .word 0x000005dc
+ 800068c: 0000ffff .word 0x0000ffff
+
+08000690 <adc_dma_init>:
+
+static void adc_dma_init() {
+ 8000690: b580 push {r7, lr}
+ 8000692: af00 add r7, sp, #0
/* Configure DMA 1 Channel 1 to get rid of all the data */
DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
- 800069c: 4b11 ldr r3, [pc, #68] ; (80006e4 <adc_dma_init+0x50>)
- 800069e: 4a12 ldr r2, [pc, #72] ; (80006e8 <adc_dma_init+0x54>)
- 80006a0: 609a str r2, [r3, #8]
- DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
- 80006a2: 4b10 ldr r3, [pc, #64] ; (80006e4 <adc_dma_init+0x50>)
- 80006a4: 4a11 ldr r2, [pc, #68] ; (80006ec <adc_dma_init+0x58>)
- 80006a6: 60da str r2, [r3, #12]
- DMA1_Channel1->CNDTR = burstlen;
- 80006a8: 4b0e ldr r3, [pc, #56] ; (80006e4 <adc_dma_init+0x50>)
- 80006aa: 687a ldr r2, [r7, #4]
- 80006ac: 605a str r2, [r3, #4]
+ 8000694: 4b0b ldr r3, [pc, #44] ; (80006c4 <adc_dma_init+0x34>)
+ 8000696: 4a0c ldr r2, [pc, #48] ; (80006c8 <adc_dma_init+0x38>)
+ 8000698: 609a str r2, [r3, #8]
DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
- 80006ae: 4b0d ldr r3, [pc, #52] ; (80006e4 <adc_dma_init+0x50>)
- 80006b0: 2200 movs r2, #0
- 80006b2: 601a str r2, [r3, #0]
+ 800069a: 4b0a ldr r3, [pc, #40] ; (80006c4 <adc_dma_init+0x34>)
+ 800069c: 2200 movs r2, #0
+ 800069e: 601a str r2, [r3, #0]
DMA1_Channel1->CCR |=
- 80006b4: 4b0b ldr r3, [pc, #44] ; (80006e4 <adc_dma_init+0x50>)
- 80006b6: 681a ldr r2, [r3, #0]
- 80006b8: 4b0a ldr r3, [pc, #40] ; (80006e4 <adc_dma_init+0x50>)
- 80006ba: 490d ldr r1, [pc, #52] ; (80006f0 <adc_dma_init+0x5c>)
- 80006bc: 430a orrs r2, r1
- 80006be: 601a str r2, [r3, #0]
+ 80006a0: 4b08 ldr r3, [pc, #32] ; (80006c4 <adc_dma_init+0x34>)
+ 80006a2: 681a ldr r2, [r3, #0]
+ 80006a4: 4b07 ldr r3, [pc, #28] ; (80006c4 <adc_dma_init+0x34>)
+ 80006a6: 4909 ldr r1, [pc, #36] ; (80006cc <adc_dma_init+0x3c>)
+ 80006a8: 430a orrs r2, r1
+ 80006aa: 601a str r2, [r3, #0]
+ | (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
| DMA_CCR_MINC
- | DMA_CCR_HTIE /* Enable half-transfer interrupt. */
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- 80006c0: 2009 movs r0, #9
- 80006c2: f7ff ff11 bl 80004e8 <NVIC_EnableIRQ>
- NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5);
- 80006c6: 2160 movs r1, #96 ; 0x60
- 80006c8: 2009 movs r0, #9
- 80006ca: f7ff ff23 bl 8000514 <NVIC_SetPriority>
-
+ 80006ac: 2009 movs r0, #9
+ 80006ae: f7ff ff1b bl 80004e8 <NVIC_EnableIRQ>
+ NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
+ 80006b2: 2140 movs r1, #64 ; 0x40
+ 80006b4: 2009 movs r0, #9
+ 80006b6: f7ff ff2d bl 8000514 <NVIC_SetPriority>
+
+ adc_dma_launch();
+ 80006ba: f000 f809 bl 80006d0 <adc_dma_launch>
+}
+ 80006be: 46c0 nop ; (mov r8, r8)
+ 80006c0: 46bd mov sp, r7
+ 80006c2: bd80 pop {r7, pc}
+ 80006c4: 40020008 .word 0x40020008
+ 80006c8: 40012440 .word 0x40012440
+ 80006cc: 00000582 .word 0x00000582
+
+080006d0 <adc_dma_launch>:
+
+void adc_dma_launch() {
+ 80006d0: b580 push {r7, lr}
+ 80006d2: af00 add r7, sp, #0
+ DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Disable channel */
+ 80006d4: 4b12 ldr r3, [pc, #72] ; (8000720 <adc_dma_launch+0x50>)
+ 80006d6: 681a ldr r2, [r3, #0]
+ 80006d8: 4b11 ldr r3, [pc, #68] ; (8000720 <adc_dma_launch+0x50>)
+ 80006da: 2101 movs r1, #1
+ 80006dc: 438a bics r2, r1
+ 80006de: 601a str r2, [r3, #0]
+ current_buf = !current_buf;
+ 80006e0: 4b10 ldr r3, [pc, #64] ; (8000724 <adc_dma_launch+0x54>)
+ 80006e2: 681b ldr r3, [r3, #0]
+ 80006e4: 425a negs r2, r3
+ 80006e6: 4153 adcs r3, r2
+ 80006e8: b2db uxtb r3, r3
+ 80006ea: 001a movs r2, r3
+ 80006ec: 4b0d ldr r3, [pc, #52] ; (8000724 <adc_dma_launch+0x54>)
+ 80006ee: 601a str r2, [r3, #0]
+ DMA1_Channel1->CMAR = (unsigned int)&(adc_pkt[current_buf].data);
+ 80006f0: 4b0c ldr r3, [pc, #48] ; (8000724 <adc_dma_launch+0x54>)
+ 80006f2: 681a ldr r2, [r3, #0]
+ 80006f4: 0013 movs r3, r2
+ 80006f6: 00db lsls r3, r3, #3
+ 80006f8: 189b adds r3, r3, r2
+ 80006fa: 00db lsls r3, r3, #3
+ 80006fc: 3308 adds r3, #8
+ 80006fe: 001a movs r2, r3
+ 8000700: 4b09 ldr r3, [pc, #36] ; (8000728 <adc_dma_launch+0x58>)
+ 8000702: 18d2 adds r2, r2, r3
+ 8000704: 4b06 ldr r3, [pc, #24] ; (8000720 <adc_dma_launch+0x50>)
+ 8000706: 60da str r2, [r3, #12]
+ DMA1_Channel1->CNDTR = ARRAY_LEN(adc_pkt[current_buf].data);
+ 8000708: 4b05 ldr r3, [pc, #20] ; (8000720 <adc_dma_launch+0x50>)
+ 800070a: 2220 movs r2, #32
+ 800070c: 605a str r2, [r3, #4]
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
- 80006ce: 4b05 ldr r3, [pc, #20] ; (80006e4 <adc_dma_init+0x50>)
- 80006d0: 681a ldr r2, [r3, #0]
- 80006d2: 4b04 ldr r3, [pc, #16] ; (80006e4 <adc_dma_init+0x50>)
- 80006d4: 2101 movs r1, #1
- 80006d6: 430a orrs r2, r1
- 80006d8: 601a str r2, [r3, #0]
+ 800070e: 4b04 ldr r3, [pc, #16] ; (8000720 <adc_dma_launch+0x50>)
+ 8000710: 681a ldr r2, [r3, #0]
+ 8000712: 4b03 ldr r3, [pc, #12] ; (8000720 <adc_dma_launch+0x50>)
+ 8000714: 2101 movs r1, #1
+ 8000716: 430a orrs r2, r1
+ 8000718: 601a str r2, [r3, #0]
}
- 80006da: 46c0 nop ; (mov r8, r8)
- 80006dc: 46bd mov sp, r7
- 80006de: b002 add sp, #8
- 80006e0: bd80 pop {r7, pc}
- 80006e2: 46c0 nop ; (mov r8, r8)
- 80006e4: 40020008 .word 0x40020008
- 80006e8: 40012440 .word 0x40012440
- 80006ec: 200000d0 .word 0x200000d0
- 80006f0: 000005a6 .word 0x000005a6
-
-080006f4 <adc_timer_init>:
+ 800071a: 46c0 nop ; (mov r8, r8)
+ 800071c: 46bd mov sp, r7
+ 800071e: bd80 pop {r7, pc}
+ 8000720: 40020008 .word 0x40020008
+ 8000724: 20000134 .word 0x20000134
+ 8000728: 200000a0 .word 0x200000a0
+
+0800072c <adc_timer_init>:
static void adc_timer_init(int psc, int ivl) {
- 80006f4: b580 push {r7, lr}
- 80006f6: b082 sub sp, #8
- 80006f8: af00 add r7, sp, #0
- 80006fa: 6078 str r0, [r7, #4]
- 80006fc: 6039 str r1, [r7, #0]
+ 800072c: b580 push {r7, lr}
+ 800072e: b082 sub sp, #8
+ 8000730: af00 add r7, sp, #0
+ 8000732: 6078 str r0, [r7, #4]
+ 8000734: 6039 str r1, [r7, #0]
TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */
- 80006fe: 4b15 ldr r3, [pc, #84] ; (8000754 <adc_timer_init+0x60>)
- 8000700: 2280 movs r2, #128 ; 0x80
- 8000702: 0212 lsls r2, r2, #8
- 8000704: 645a str r2, [r3, #68] ; 0x44
+ 8000736: 4b15 ldr r3, [pc, #84] ; (800078c <adc_timer_init+0x60>)
+ 8000738: 2280 movs r2, #128 ; 0x80
+ 800073a: 0212 lsls r2, r2, #8
+ 800073c: 645a str r2, [r3, #68] ; 0x44
TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
- 8000706: 4b13 ldr r3, [pc, #76] ; (8000754 <adc_timer_init+0x60>)
- 8000708: 22c0 movs r2, #192 ; 0xc0
- 800070a: 01d2 lsls r2, r2, #7
- 800070c: 61da str r2, [r3, #28]
+ 800073e: 4b13 ldr r3, [pc, #76] ; (800078c <adc_timer_init+0x60>)
+ 8000740: 22c0 movs r2, #192 ; 0xc0
+ 8000742: 01d2 lsls r2, r2, #7
+ 8000744: 61da str r2, [r3, #28]
TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
- 800070e: 4b11 ldr r3, [pc, #68] ; (8000754 <adc_timer_init+0x60>)
- 8000710: 2280 movs r2, #128 ; 0x80
- 8000712: 0152 lsls r2, r2, #5
- 8000714: 621a str r2, [r3, #32]
+ 8000746: 4b11 ldr r3, [pc, #68] ; (800078c <adc_timer_init+0x60>)
+ 8000748: 2280 movs r2, #128 ; 0x80
+ 800074a: 0152 lsls r2, r2, #5
+ 800074c: 621a str r2, [r3, #32]
TIM1->CCR4 = 1; /* Trigger at start of timer cycle */
- 8000716: 4b0f ldr r3, [pc, #60] ; (8000754 <adc_timer_init+0x60>)
- 8000718: 2201 movs r2, #1
- 800071a: 641a str r2, [r3, #64] ; 0x40
+ 800074e: 4b0f ldr r3, [pc, #60] ; (800078c <adc_timer_init+0x60>)
+ 8000750: 2201 movs r2, #1
+ 8000752: 641a str r2, [r3, #64] ; 0x40
/* Set prescaler and interval */
TIM1->PSC = psc-1;
- 800071c: 687b ldr r3, [r7, #4]
- 800071e: 1e5a subs r2, r3, #1
- 8000720: 4b0c ldr r3, [pc, #48] ; (8000754 <adc_timer_init+0x60>)
- 8000722: 629a str r2, [r3, #40] ; 0x28
+ 8000754: 687b ldr r3, [r7, #4]
+ 8000756: 1e5a subs r2, r3, #1
+ 8000758: 4b0c ldr r3, [pc, #48] ; (800078c <adc_timer_init+0x60>)
+ 800075a: 629a str r2, [r3, #40] ; 0x28
TIM1->ARR = ivl-1;
- 8000724: 683b ldr r3, [r7, #0]
- 8000726: 1e5a subs r2, r3, #1
- 8000728: 4b0a ldr r3, [pc, #40] ; (8000754 <adc_timer_init+0x60>)
- 800072a: 62da str r2, [r3, #44] ; 0x2c
+ 800075c: 683b ldr r3, [r7, #0]
+ 800075e: 1e5a subs r2, r3, #1
+ 8000760: 4b0a ldr r3, [pc, #40] ; (800078c <adc_timer_init+0x60>)
+ 8000762: 62da str r2, [r3, #44] ; 0x2c
/* Preload all values */
TIM1->EGR |= TIM_EGR_UG;
- 800072c: 4b09 ldr r3, [pc, #36] ; (8000754 <adc_timer_init+0x60>)
- 800072e: 695a ldr r2, [r3, #20]
- 8000730: 4b08 ldr r3, [pc, #32] ; (8000754 <adc_timer_init+0x60>)
- 8000732: 2101 movs r1, #1
- 8000734: 430a orrs r2, r1
- 8000736: 615a str r2, [r3, #20]
+ 8000764: 4b09 ldr r3, [pc, #36] ; (800078c <adc_timer_init+0x60>)
+ 8000766: 695a ldr r2, [r3, #20]
+ 8000768: 4b08 ldr r3, [pc, #32] ; (800078c <adc_timer_init+0x60>)
+ 800076a: 2101 movs r1, #1
+ 800076c: 430a orrs r2, r1
+ 800076e: 615a str r2, [r3, #20]
TIM1->CR1 = TIM_CR1_ARPE;
- 8000738: 4b06 ldr r3, [pc, #24] ; (8000754 <adc_timer_init+0x60>)
- 800073a: 2280 movs r2, #128 ; 0x80
- 800073c: 601a str r2, [r3, #0]
+ 8000770: 4b06 ldr r3, [pc, #24] ; (800078c <adc_timer_init+0x60>)
+ 8000772: 2280 movs r2, #128 ; 0x80
+ 8000774: 601a str r2, [r3, #0]
/* And... go! */
TIM1->CR1 |= TIM_CR1_CEN;
- 800073e: 4b05 ldr r3, [pc, #20] ; (8000754 <adc_timer_init+0x60>)
- 8000740: 681a ldr r2, [r3, #0]
- 8000742: 4b04 ldr r3, [pc, #16] ; (8000754 <adc_timer_init+0x60>)
- 8000744: 2101 movs r1, #1
- 8000746: 430a orrs r2, r1
- 8000748: 601a str r2, [r3, #0]
+ 8000776: 4b05 ldr r3, [pc, #20] ; (800078c <adc_timer_init+0x60>)
+ 8000778: 681a ldr r2, [r3, #0]
+ 800077a: 4b04 ldr r3, [pc, #16] ; (800078c <adc_timer_init+0x60>)
+ 800077c: 2101 movs r1, #1
+ 800077e: 430a orrs r2, r1
+ 8000780: 601a str r2, [r3, #0]
}
- 800074a: 46c0 nop ; (mov r8, r8)
- 800074c: 46bd mov sp, r7
- 800074e: b002 add sp, #8
- 8000750: bd80 pop {r7, pc}
- 8000752: 46c0 nop ; (mov r8, r8)
- 8000754: 40012c00 .word 0x40012c00
+ 8000782: 46c0 nop ; (mov r8, r8)
+ 8000784: 46bd mov sp, r7
+ 8000786: b002 add sp, #8
+ 8000788: bd80 pop {r7, pc}
+ 800078a: 46c0 nop ; (mov r8, r8)
+ 800078c: 40012c00 .word 0x40012c00
-08000758 <gdb_dump>:
+08000790 <gdb_dump>:
/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */
static void gdb_dump(void) {
- 8000758: b580 push {r7, lr}
- 800075a: af00 add r7, sp, #0
+ 8000790: b580 push {r7, lr}
+ 8000792: af00 add r7, sp, #0
}
- 800075c: 46c0 nop ; (mov r8, r8)
- 800075e: 46bd mov sp, r7
- 8000760: bd80 pop {r7, pc}
+ 8000794: 46c0 nop ; (mov r8, r8)
+ 8000796: 46bd mov sp, r7
+ 8000798: bd80 pop {r7, pc}
-08000762 <DMA1_Channel1_IRQHandler>:
+0800079a <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void) {
- 8000762: b580 push {r7, lr}
- 8000764: b082 sub sp, #8
- 8000766: af00 add r7, sp, #0
+ 800079a: b580 push {r7, lr}
+ 800079c: b082 sub sp, #8
+ 800079e: af00 add r7, sp, #0
uint32_t isr = DMA1->ISR;
- 8000768: 4b14 ldr r3, [pc, #80] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
- 800076a: 681b ldr r3, [r3, #0]
- 800076c: 603b str r3, [r7, #0]
+ 80007a0: 4b1a ldr r3, [pc, #104] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
+ 80007a2: 681b ldr r3, [r3, #0]
+ 80007a4: 607b str r3, [r7, #4]
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
- 800076e: 4b13 ldr r3, [pc, #76] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
- 8000770: 685a ldr r2, [r3, #4]
- 8000772: 4b12 ldr r3, [pc, #72] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
- 8000774: 2101 movs r1, #1
- 8000776: 430a orrs r2, r1
- 8000778: 605a str r2, [r3, #4]
+ 80007a6: 4b19 ldr r3, [pc, #100] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
+ 80007a8: 685a ldr r2, [r3, #4]
+ 80007aa: 4b18 ldr r3, [pc, #96] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
+ 80007ac: 2101 movs r1, #1
+ 80007ae: 430a orrs r2, r1
+ 80007b0: 605a str r2, [r3, #4]
+ adc_dma_launch();
+ 80007b2: f7ff ff8d bl 80006d0 <adc_dma_launch>
gdb_dump();
- 800077a: f7ff ffed bl 8000758 <gdb_dump>
- static_assert(ARRAY_LEN(adc_buf) % 2 == 0, "ADC_BUFSIZE must be even for half-transfer uart tx logic to work");
-
- int rc;
- if (isr & DMA_ISR_HTIF2) /* half-transfer */
- 800077e: 683b ldr r3, [r7, #0]
- 8000780: 2240 movs r2, #64 ; 0x40
- 8000782: 4013 ands r3, r2
- 8000784: d007 beq.n 8000796 <DMA1_Channel1_IRQHandler+0x34>
- rc = usart_send_packet_nonblocking((uint8_t *)adc_buf, sizeof(adc_buf)/2);
- 8000786: 4b0e ldr r3, [pc, #56] ; (80007c0 <DMA1_Channel1_IRQHandler+0x5e>)
- 8000788: 2120 movs r1, #32
- 800078a: 0018 movs r0, r3
- 800078c: f000 f9c6 bl 8000b1c <usart_send_packet_nonblocking>
- 8000790: 0003 movs r3, r0
- 8000792: 607b str r3, [r7, #4]
- 8000794: e006 b.n 80007a4 <DMA1_Channel1_IRQHandler+0x42>
- else /* end of transfer */
- rc = usart_send_packet_nonblocking((uint8_t *)adc_buf + ARRAY_LEN(adc_buf)/2, sizeof(adc_buf)/2);
- 8000796: 4b0b ldr r3, [pc, #44] ; (80007c4 <DMA1_Channel1_IRQHandler+0x62>)
- 8000798: 2120 movs r1, #32
- 800079a: 0018 movs r0, r3
- 800079c: f000 f9be bl 8000b1c <usart_send_packet_nonblocking>
- 80007a0: 0003 movs r3, r0
- 80007a2: 607b str r3, [r7, #4]
-
- if (rc)
- 80007a4: 687b ldr r3, [r7, #4]
- 80007a6: 2b00 cmp r3, #0
- 80007a8: d004 beq.n 80007b4 <DMA1_Channel1_IRQHandler+0x52>
- usart_overruns++;
- 80007aa: 4b07 ldr r3, [pc, #28] ; (80007c8 <DMA1_Channel1_IRQHandler+0x66>)
- 80007ac: 681b ldr r3, [r3, #0]
- 80007ae: 1c5a adds r2, r3, #1
- 80007b0: 4b05 ldr r3, [pc, #20] ; (80007c8 <DMA1_Channel1_IRQHandler+0x66>)
- 80007b2: 601a str r2, [r3, #0]
+ 80007b6: f7ff ffeb bl 8000790 <gdb_dump>
+
+ adc_pkt[!current_buf].seq = current_seq++;
+ 80007ba: 4b15 ldr r3, [pc, #84] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>)
+ 80007bc: 881a ldrh r2, [r3, #0]
+ 80007be: 1c53 adds r3, r2, #1
+ 80007c0: b299 uxth r1, r3
+ 80007c2: 4b13 ldr r3, [pc, #76] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>)
+ 80007c4: 8019 strh r1, [r3, #0]
+ 80007c6: 4b13 ldr r3, [pc, #76] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>)
+ 80007c8: 681b ldr r3, [r3, #0]
+ 80007ca: 4259 negs r1, r3
+ 80007cc: 414b adcs r3, r1
+ 80007ce: b2db uxtb r3, r3
+ 80007d0: 0018 movs r0, r3
+ 80007d2: 4911 ldr r1, [pc, #68] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>)
+ 80007d4: 0003 movs r3, r0
+ 80007d6: 00db lsls r3, r3, #3
+ 80007d8: 181b adds r3, r3, r0
+ 80007da: 00db lsls r3, r3, #3
+ 80007dc: 18cb adds r3, r1, r3
+ 80007de: 3306 adds r3, #6
+ 80007e0: 801a strh r2, [r3, #0]
+ /* Ignore return value since we can't do anything here. Overruns are logged in serial.c. */
+ usart_send_packet_nonblocking(&adc_pkt[!current_buf].ll, sizeof(adc_pkt[!current_buf]));
+ 80007e2: 4b0c ldr r3, [pc, #48] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>)
+ 80007e4: 681b ldr r3, [r3, #0]
+ 80007e6: 425a negs r2, r3
+ 80007e8: 4153 adcs r3, r2
+ 80007ea: b2db uxtb r3, r3
+ 80007ec: 001a movs r2, r3
+ 80007ee: 0013 movs r3, r2
+ 80007f0: 00db lsls r3, r3, #3
+ 80007f2: 189b adds r3, r3, r2
+ 80007f4: 00db lsls r3, r3, #3
+ 80007f6: 4a08 ldr r2, [pc, #32] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>)
+ 80007f8: 189b adds r3, r3, r2
+ 80007fa: 2148 movs r1, #72 ; 0x48
+ 80007fc: 0018 movs r0, r3
+ 80007fe: f000 fadd bl 8000dbc <usart_send_packet_nonblocking>
adc_buf[i] = -255;
}
}
}
*/
}
- 80007b4: 46c0 nop ; (mov r8, r8)
- 80007b6: 46bd mov sp, r7
- 80007b8: b002 add sp, #8
- 80007ba: bd80 pop {r7, pc}
- 80007bc: 40020000 .word 0x40020000
- 80007c0: 200000d0 .word 0x200000d0
- 80007c4: 200000e0 .word 0x200000e0
- 80007c8: 200000a0 .word 0x200000a0
-
-080007cc <NVIC_EnableIRQ>:
+ 8000802: 46c0 nop ; (mov r8, r8)
+ 8000804: 46bd mov sp, r7
+ 8000806: b002 add sp, #8
+ 8000808: bd80 pop {r7, pc}
+ 800080a: 46c0 nop ; (mov r8, r8)
+ 800080c: 40020000 .word 0x40020000
+ 8000810: 20000130 .word 0x20000130
+ 8000814: 20000134 .word 0x20000134
+ 8000818: 200000a0 .word 0x200000a0
+
+0800081c <NVIC_EnableIRQ>:
{
- 80007cc: b580 push {r7, lr}
- 80007ce: b082 sub sp, #8
- 80007d0: af00 add r7, sp, #0
- 80007d2: 0002 movs r2, r0
- 80007d4: 1dfb adds r3, r7, #7
- 80007d6: 701a strb r2, [r3, #0]
+ 800081c: b580 push {r7, lr}
+ 800081e: b082 sub sp, #8
+ 8000820: af00 add r7, sp, #0
+ 8000822: 0002 movs r2, r0
+ 8000824: 1dfb adds r3, r7, #7
+ 8000826: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- 80007d8: 1dfb adds r3, r7, #7
- 80007da: 781b ldrb r3, [r3, #0]
- 80007dc: 001a movs r2, r3
- 80007de: 231f movs r3, #31
- 80007e0: 401a ands r2, r3
- 80007e2: 4b04 ldr r3, [pc, #16] ; (80007f4 <NVIC_EnableIRQ+0x28>)
- 80007e4: 2101 movs r1, #1
- 80007e6: 4091 lsls r1, r2
- 80007e8: 000a movs r2, r1
- 80007ea: 601a str r2, [r3, #0]
+ 8000828: 1dfb adds r3, r7, #7
+ 800082a: 781b ldrb r3, [r3, #0]
+ 800082c: 001a movs r2, r3
+ 800082e: 231f movs r3, #31
+ 8000830: 401a ands r2, r3
+ 8000832: 4b04 ldr r3, [pc, #16] ; (8000844 <NVIC_EnableIRQ+0x28>)
+ 8000834: 2101 movs r1, #1
+ 8000836: 4091 lsls r1, r2
+ 8000838: 000a movs r2, r1
+ 800083a: 601a str r2, [r3, #0]
}
- 80007ec: 46c0 nop ; (mov r8, r8)
- 80007ee: 46bd mov sp, r7
- 80007f0: b002 add sp, #8
- 80007f2: bd80 pop {r7, pc}
- 80007f4: e000e100 .word 0xe000e100
+ 800083c: 46c0 nop ; (mov r8, r8)
+ 800083e: 46bd mov sp, r7
+ 8000840: b002 add sp, #8
+ 8000842: bd80 pop {r7, pc}
+ 8000844: e000e100 .word 0xe000e100
-080007f8 <NVIC_DisableIRQ>:
+08000848 <NVIC_DisableIRQ>:
{
- 80007f8: b580 push {r7, lr}
- 80007fa: b082 sub sp, #8
- 80007fc: af00 add r7, sp, #0
- 80007fe: 0002 movs r2, r0
- 8000800: 1dfb adds r3, r7, #7
- 8000802: 701a strb r2, [r3, #0]
+ 8000848: b580 push {r7, lr}
+ 800084a: b082 sub sp, #8
+ 800084c: af00 add r7, sp, #0
+ 800084e: 0002 movs r2, r0
+ 8000850: 1dfb adds r3, r7, #7
+ 8000852: 701a strb r2, [r3, #0]
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- 8000804: 1dfb adds r3, r7, #7
- 8000806: 781b ldrb r3, [r3, #0]
- 8000808: 001a movs r2, r3
- 800080a: 231f movs r3, #31
- 800080c: 4013 ands r3, r2
- 800080e: 4905 ldr r1, [pc, #20] ; (8000824 <NVIC_DisableIRQ+0x2c>)
- 8000810: 2201 movs r2, #1
- 8000812: 409a lsls r2, r3
- 8000814: 0013 movs r3, r2
- 8000816: 2280 movs r2, #128 ; 0x80
- 8000818: 508b str r3, [r1, r2]
+ 8000854: 1dfb adds r3, r7, #7
+ 8000856: 781b ldrb r3, [r3, #0]
+ 8000858: 001a movs r2, r3
+ 800085a: 231f movs r3, #31
+ 800085c: 4013 ands r3, r2
+ 800085e: 4905 ldr r1, [pc, #20] ; (8000874 <NVIC_DisableIRQ+0x2c>)
+ 8000860: 2201 movs r2, #1
+ 8000862: 409a lsls r2, r3
+ 8000864: 0013 movs r3, r2
+ 8000866: 2280 movs r2, #128 ; 0x80
+ 8000868: 508b str r3, [r1, r2]
}
- 800081a: 46c0 nop ; (mov r8, r8)
- 800081c: 46bd mov sp, r7
- 800081e: b002 add sp, #8
- 8000820: bd80 pop {r7, pc}
- 8000822: 46c0 nop ; (mov r8, r8)
- 8000824: e000e100 .word 0xe000e100
-
-08000828 <NVIC_SetPriority>:
+ 800086a: 46c0 nop ; (mov r8, r8)
+ 800086c: 46bd mov sp, r7
+ 800086e: b002 add sp, #8
+ 8000870: bd80 pop {r7, pc}
+ 8000872: 46c0 nop ; (mov r8, r8)
+ 8000874: e000e100 .word 0xe000e100
+
+08000878 <NVIC_SetPriority>:
{
- 8000828: b590 push {r4, r7, lr}
- 800082a: b083 sub sp, #12
- 800082c: af00 add r7, sp, #0
- 800082e: 0002 movs r2, r0
- 8000830: 6039 str r1, [r7, #0]
- 8000832: 1dfb adds r3, r7, #7
- 8000834: 701a strb r2, [r3, #0]
+ 8000878: b590 push {r4, r7, lr}
+ 800087a: b083 sub sp, #12
+ 800087c: af00 add r7, sp, #0
+ 800087e: 0002 movs r2, r0
+ 8000880: 6039 str r1, [r7, #0]
+ 8000882: 1dfb adds r3, r7, #7
+ 8000884: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
- 8000836: 1dfb adds r3, r7, #7
- 8000838: 781b ldrb r3, [r3, #0]
- 800083a: 2b7f cmp r3, #127 ; 0x7f
- 800083c: d932 bls.n 80008a4 <NVIC_SetPriority+0x7c>
+ 8000886: 1dfb adds r3, r7, #7
+ 8000888: 781b ldrb r3, [r3, #0]
+ 800088a: 2b7f cmp r3, #127 ; 0x7f
+ 800088c: d932 bls.n 80008f4 <NVIC_SetPriority+0x7c>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800083e: 4a2f ldr r2, [pc, #188] ; (80008fc <NVIC_SetPriority+0xd4>)
- 8000840: 1dfb adds r3, r7, #7
- 8000842: 781b ldrb r3, [r3, #0]
- 8000844: 0019 movs r1, r3
- 8000846: 230f movs r3, #15
- 8000848: 400b ands r3, r1
- 800084a: 3b08 subs r3, #8
- 800084c: 089b lsrs r3, r3, #2
- 800084e: 3306 adds r3, #6
- 8000850: 009b lsls r3, r3, #2
- 8000852: 18d3 adds r3, r2, r3
- 8000854: 3304 adds r3, #4
- 8000856: 681b ldr r3, [r3, #0]
- 8000858: 1dfa adds r2, r7, #7
- 800085a: 7812 ldrb r2, [r2, #0]
- 800085c: 0011 movs r1, r2
- 800085e: 2203 movs r2, #3
- 8000860: 400a ands r2, r1
- 8000862: 00d2 lsls r2, r2, #3
- 8000864: 21ff movs r1, #255 ; 0xff
- 8000866: 4091 lsls r1, r2
- 8000868: 000a movs r2, r1
- 800086a: 43d2 mvns r2, r2
- 800086c: 401a ands r2, r3
- 800086e: 0011 movs r1, r2
+ 800088e: 4a2f ldr r2, [pc, #188] ; (800094c <NVIC_SetPriority+0xd4>)
+ 8000890: 1dfb adds r3, r7, #7
+ 8000892: 781b ldrb r3, [r3, #0]
+ 8000894: 0019 movs r1, r3
+ 8000896: 230f movs r3, #15
+ 8000898: 400b ands r3, r1
+ 800089a: 3b08 subs r3, #8
+ 800089c: 089b lsrs r3, r3, #2
+ 800089e: 3306 adds r3, #6
+ 80008a0: 009b lsls r3, r3, #2
+ 80008a2: 18d3 adds r3, r2, r3
+ 80008a4: 3304 adds r3, #4
+ 80008a6: 681b ldr r3, [r3, #0]
+ 80008a8: 1dfa adds r2, r7, #7
+ 80008aa: 7812 ldrb r2, [r2, #0]
+ 80008ac: 0011 movs r1, r2
+ 80008ae: 2203 movs r2, #3
+ 80008b0: 400a ands r2, r1
+ 80008b2: 00d2 lsls r2, r2, #3
+ 80008b4: 21ff movs r1, #255 ; 0xff
+ 80008b6: 4091 lsls r1, r2
+ 80008b8: 000a movs r2, r1
+ 80008ba: 43d2 mvns r2, r2
+ 80008bc: 401a ands r2, r3
+ 80008be: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 8000870: 683b ldr r3, [r7, #0]
- 8000872: 019b lsls r3, r3, #6
- 8000874: 22ff movs r2, #255 ; 0xff
- 8000876: 401a ands r2, r3
- 8000878: 1dfb adds r3, r7, #7
- 800087a: 781b ldrb r3, [r3, #0]
- 800087c: 0018 movs r0, r3
- 800087e: 2303 movs r3, #3
- 8000880: 4003 ands r3, r0
- 8000882: 00db lsls r3, r3, #3
- 8000884: 409a lsls r2, r3
+ 80008c0: 683b ldr r3, [r7, #0]
+ 80008c2: 019b lsls r3, r3, #6
+ 80008c4: 22ff movs r2, #255 ; 0xff
+ 80008c6: 401a ands r2, r3
+ 80008c8: 1dfb adds r3, r7, #7
+ 80008ca: 781b ldrb r3, [r3, #0]
+ 80008cc: 0018 movs r0, r3
+ 80008ce: 2303 movs r3, #3
+ 80008d0: 4003 ands r3, r0
+ 80008d2: 00db lsls r3, r3, #3
+ 80008d4: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8000886: 481d ldr r0, [pc, #116] ; (80008fc <NVIC_SetPriority+0xd4>)
- 8000888: 1dfb adds r3, r7, #7
- 800088a: 781b ldrb r3, [r3, #0]
- 800088c: 001c movs r4, r3
- 800088e: 230f movs r3, #15
- 8000890: 4023 ands r3, r4
- 8000892: 3b08 subs r3, #8
- 8000894: 089b lsrs r3, r3, #2
- 8000896: 430a orrs r2, r1
- 8000898: 3306 adds r3, #6
- 800089a: 009b lsls r3, r3, #2
- 800089c: 18c3 adds r3, r0, r3
- 800089e: 3304 adds r3, #4
- 80008a0: 601a str r2, [r3, #0]
+ 80008d6: 481d ldr r0, [pc, #116] ; (800094c <NVIC_SetPriority+0xd4>)
+ 80008d8: 1dfb adds r3, r7, #7
+ 80008da: 781b ldrb r3, [r3, #0]
+ 80008dc: 001c movs r4, r3
+ 80008de: 230f movs r3, #15
+ 80008e0: 4023 ands r3, r4
+ 80008e2: 3b08 subs r3, #8
+ 80008e4: 089b lsrs r3, r3, #2
+ 80008e6: 430a orrs r2, r1
+ 80008e8: 3306 adds r3, #6
+ 80008ea: 009b lsls r3, r3, #2
+ 80008ec: 18c3 adds r3, r0, r3
+ 80008ee: 3304 adds r3, #4
+ 80008f0: 601a str r2, [r3, #0]
}
- 80008a2: e027 b.n 80008f4 <NVIC_SetPriority+0xcc>
+ 80008f2: e027 b.n 8000944 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80008a4: 4a16 ldr r2, [pc, #88] ; (8000900 <NVIC_SetPriority+0xd8>)
- 80008a6: 1dfb adds r3, r7, #7
- 80008a8: 781b ldrb r3, [r3, #0]
- 80008aa: b25b sxtb r3, r3
- 80008ac: 089b lsrs r3, r3, #2
- 80008ae: 33c0 adds r3, #192 ; 0xc0
- 80008b0: 009b lsls r3, r3, #2
- 80008b2: 589b ldr r3, [r3, r2]
- 80008b4: 1dfa adds r2, r7, #7
- 80008b6: 7812 ldrb r2, [r2, #0]
- 80008b8: 0011 movs r1, r2
- 80008ba: 2203 movs r2, #3
- 80008bc: 400a ands r2, r1
- 80008be: 00d2 lsls r2, r2, #3
- 80008c0: 21ff movs r1, #255 ; 0xff
- 80008c2: 4091 lsls r1, r2
- 80008c4: 000a movs r2, r1
- 80008c6: 43d2 mvns r2, r2
- 80008c8: 401a ands r2, r3
- 80008ca: 0011 movs r1, r2
+ 80008f4: 4a16 ldr r2, [pc, #88] ; (8000950 <NVIC_SetPriority+0xd8>)
+ 80008f6: 1dfb adds r3, r7, #7
+ 80008f8: 781b ldrb r3, [r3, #0]
+ 80008fa: b25b sxtb r3, r3
+ 80008fc: 089b lsrs r3, r3, #2
+ 80008fe: 33c0 adds r3, #192 ; 0xc0
+ 8000900: 009b lsls r3, r3, #2
+ 8000902: 589b ldr r3, [r3, r2]
+ 8000904: 1dfa adds r2, r7, #7
+ 8000906: 7812 ldrb r2, [r2, #0]
+ 8000908: 0011 movs r1, r2
+ 800090a: 2203 movs r2, #3
+ 800090c: 400a ands r2, r1
+ 800090e: 00d2 lsls r2, r2, #3
+ 8000910: 21ff movs r1, #255 ; 0xff
+ 8000912: 4091 lsls r1, r2
+ 8000914: 000a movs r2, r1
+ 8000916: 43d2 mvns r2, r2
+ 8000918: 401a ands r2, r3
+ 800091a: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80008cc: 683b ldr r3, [r7, #0]
- 80008ce: 019b lsls r3, r3, #6
- 80008d0: 22ff movs r2, #255 ; 0xff
- 80008d2: 401a ands r2, r3
- 80008d4: 1dfb adds r3, r7, #7
- 80008d6: 781b ldrb r3, [r3, #0]
- 80008d8: 0018 movs r0, r3
- 80008da: 2303 movs r3, #3
- 80008dc: 4003 ands r3, r0
- 80008de: 00db lsls r3, r3, #3
- 80008e0: 409a lsls r2, r3
+ 800091c: 683b ldr r3, [r7, #0]
+ 800091e: 019b lsls r3, r3, #6
+ 8000920: 22ff movs r2, #255 ; 0xff
+ 8000922: 401a ands r2, r3
+ 8000924: 1dfb adds r3, r7, #7
+ 8000926: 781b ldrb r3, [r3, #0]
+ 8000928: 0018 movs r0, r3
+ 800092a: 2303 movs r3, #3
+ 800092c: 4003 ands r3, r0
+ 800092e: 00db lsls r3, r3, #3
+ 8000930: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80008e2: 4807 ldr r0, [pc, #28] ; (8000900 <NVIC_SetPriority+0xd8>)
- 80008e4: 1dfb adds r3, r7, #7
- 80008e6: 781b ldrb r3, [r3, #0]
- 80008e8: b25b sxtb r3, r3
- 80008ea: 089b lsrs r3, r3, #2
- 80008ec: 430a orrs r2, r1
- 80008ee: 33c0 adds r3, #192 ; 0xc0
- 80008f0: 009b lsls r3, r3, #2
- 80008f2: 501a str r2, [r3, r0]
+ 8000932: 4807 ldr r0, [pc, #28] ; (8000950 <NVIC_SetPriority+0xd8>)
+ 8000934: 1dfb adds r3, r7, #7
+ 8000936: 781b ldrb r3, [r3, #0]
+ 8000938: b25b sxtb r3, r3
+ 800093a: 089b lsrs r3, r3, #2
+ 800093c: 430a orrs r2, r1
+ 800093e: 33c0 adds r3, #192 ; 0xc0
+ 8000940: 009b lsls r3, r3, #2
+ 8000942: 501a str r2, [r3, r0]
}
- 80008f4: 46c0 nop ; (mov r8, r8)
- 80008f6: 46bd mov sp, r7
- 80008f8: b003 add sp, #12
- 80008fa: bd90 pop {r4, r7, pc}
- 80008fc: e000ed00 .word 0xe000ed00
- 8000900: e000e100 .word 0xe000e100
-
-08000904 <usart_dma_init>:
-
+ 8000944: 46c0 nop ; (mov r8, r8)
+ 8000946: 46bd mov sp, r7
+ 8000948: b003 add sp, #12
+ 800094a: bd90 pop {r4, r7, pc}
+ 800094c: e000ed00 .word 0xe000ed00
+ 8000950: e000e100 .word 0xe000e100
+
+08000954 <usart_dma_init>:
static void usart_schedule_dma(void);
-int usart_putc_nonblocking(char c);
-int usart_putc(char c);
+static int usart_putc_nonblocking(uint8_t c);
+static int usart_retransmit_packet(uint8_t idx);
+
void usart_dma_init() {
- 8000904: b580 push {r7, lr}
- 8000906: af00 add r7, sp, #0
- usart_tx_buf.xfr_start = -1,
- 8000908: 4b19 ldr r3, [pc, #100] ; (8000970 <usart_dma_init+0x6c>)
- 800090a: 2201 movs r2, #1
- 800090c: 4252 negs r2, r2
- 800090e: 601a str r2, [r3, #0]
- usart_tx_buf.xfr_end = 0,
- 8000910: 4b17 ldr r3, [pc, #92] ; (8000970 <usart_dma_init+0x6c>)
- 8000912: 2200 movs r2, #0
- 8000914: 605a str r2, [r3, #4]
- usart_tx_buf.wr_pos = 0,
- 8000916: 4b16 ldr r3, [pc, #88] ; (8000970 <usart_dma_init+0x6c>)
- 8000918: 2200 movs r2, #0
- 800091a: 609a str r2, [r3, #8]
+ 8000954: b580 push {r7, lr}
+ 8000956: b082 sub sp, #8
+ 8000958: af00 add r7, sp, #0
+ usart_tx_buf.xfr_start = -1;
+ 800095a: 4b2a ldr r3, [pc, #168] ; (8000a04 <usart_dma_init+0xb0>)
+ 800095c: 2201 movs r2, #1
+ 800095e: 4252 negs r2, r2
+ 8000960: 601a str r2, [r3, #0]
+ usart_tx_buf.xfr_end = 0;
+ 8000962: 4b28 ldr r3, [pc, #160] ; (8000a04 <usart_dma_init+0xb0>)
+ 8000964: 2200 movs r2, #0
+ 8000966: 605a str r2, [r3, #4]
+ usart_tx_buf.wr_pos = 0;
+ 8000968: 4b26 ldr r3, [pc, #152] ; (8000a04 <usart_dma_init+0xb0>)
+ 800096a: 2200 movs r2, #0
+ 800096c: 609a str r2, [r3, #8]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ 800096e: 2300 movs r3, #0
+ 8000970: 607b str r3, [r7, #4]
+ 8000972: e00b b.n 800098c <usart_dma_init+0x38>
+ usart_tx_buf.packet_start[i] = -1;
+ 8000974: 4a23 ldr r2, [pc, #140] ; (8000a04 <usart_dma_init+0xb0>)
+ 8000976: 687b ldr r3, [r7, #4]
+ 8000978: 3302 adds r3, #2
+ 800097a: 009b lsls r3, r3, #2
+ 800097c: 18d3 adds r3, r2, r3
+ 800097e: 3304 adds r3, #4
+ 8000980: 2201 movs r2, #1
+ 8000982: 4252 negs r2, r2
+ 8000984: 601a str r2, [r3, #0]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ 8000986: 687b ldr r3, [r7, #4]
+ 8000988: 3301 adds r3, #1
+ 800098a: 607b str r3, [r7, #4]
+ 800098c: 687b ldr r3, [r7, #4]
+ 800098e: 2b04 cmp r3, #4
+ 8000990: d9f0 bls.n 8000974 <usart_dma_init+0x20>
+
+ cobs_decode_incremental_initialize(&cobs_state);
+ 8000992: 4b1d ldr r3, [pc, #116] ; (8000a08 <usart_dma_init+0xb4>)
+ 8000994: 0018 movs r0, r3
+ 8000996: f000 fb6b bl 8001070 <cobs_decode_incremental_initialize>
/* Configure DMA 1 Channel 2 to handle uart transmission */
- DMA1_Channel2->CPAR = (unsigned int)&(USART1->TDR);
- 800091c: 4b15 ldr r3, [pc, #84] ; (8000974 <usart_dma_init+0x70>)
- 800091e: 4a16 ldr r2, [pc, #88] ; (8000978 <usart_dma_init+0x74>)
- 8000920: 609a str r2, [r3, #8]
+ DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
+ 800099a: 4b1c ldr r3, [pc, #112] ; (8000a0c <usart_dma_init+0xb8>)
+ 800099c: 4a1c ldr r2, [pc, #112] ; (8000a10 <usart_dma_init+0xbc>)
+ 800099e: 609a str r2, [r3, #8]
DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
- 8000922: 4b14 ldr r3, [pc, #80] ; (8000974 <usart_dma_init+0x70>)
- 8000924: 2292 movs r2, #146 ; 0x92
- 8000926: 601a str r2, [r3, #0]
+ 80009a0: 4b1a ldr r3, [pc, #104] ; (8000a0c <usart_dma_init+0xb8>)
+ 80009a2: 2292 movs r2, #146 ; 0x92
+ 80009a4: 601a str r2, [r3, #0]
+ | (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
+ DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR);
+ 80009a6: 4b1b ldr r3, [pc, #108] ; (8000a14 <usart_dma_init+0xc0>)
+ 80009a8: 4a1b ldr r2, [pc, #108] ; (8000a18 <usart_dma_init+0xc4>)
+ 80009aa: 60da str r2, [r3, #12]
+ DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos)
+ 80009ac: 4b19 ldr r3, [pc, #100] ; (8000a14 <usart_dma_init+0xc0>)
+ 80009ae: 4a1b ldr r2, [pc, #108] ; (8000a1c <usart_dma_init+0xc8>)
+ 80009b0: 601a str r2, [r3, #0]
+ | (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
+ | DMA_CCR_PINC
+ | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
+
/* triggered on transfer completion. We use this to process the ADC data */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000928: 200a movs r0, #10
- 800092a: f7ff ff4f bl 80007cc <NVIC_EnableIRQ>
+ 80009b2: 200a movs r0, #10
+ 80009b4: f7ff ff32 bl 800081c <NVIC_EnableIRQ>
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
- 800092e: 2120 movs r1, #32
- 8000930: 200a movs r0, #10
- 8000932: f7ff ff79 bl 8000828 <NVIC_SetPriority>
+ 80009b8: 2120 movs r1, #32
+ 80009ba: 200a movs r0, #10
+ 80009bc: f7ff ff5c bl 8000878 <NVIC_SetPriority>
USART1->CR1 = /* 8-bit -> M1, M0 clear */
- 8000936: 4b11 ldr r3, [pc, #68] ; (800097c <usart_dma_init+0x78>)
- 8000938: 4a11 ldr r2, [pc, #68] ; (8000980 <usart_dma_init+0x7c>)
- 800093a: 601a str r2, [r3, #0]
- | USART_CR1_RE;
+ 80009c0: 4b17 ldr r3, [pc, #92] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009c2: 4a18 ldr r2, [pc, #96] ; (8000a24 <usart_dma_init+0xd0>)
+ 80009c4: 601a str r2, [r3, #0]
/* Set divider for 115.2kBd @48MHz system clock. */
//USART1->BRR = 417;
//USART1->BRR = 48; /* 1MBd */
- USART1->BRR = 96; /* 500kBd */
- 800093c: 4b0f ldr r3, [pc, #60] ; (800097c <usart_dma_init+0x78>)
- 800093e: 2260 movs r2, #96 ; 0x60
- 8000940: 60da str r2, [r3, #12]
+ //USART1->BRR = 96; /* 500kBd */
USART1->BRR = 192; /* 250kBd */
- 8000942: 4b0e ldr r3, [pc, #56] ; (800097c <usart_dma_init+0x78>)
- 8000944: 22c0 movs r2, #192 ; 0xc0
- 8000946: 60da str r2, [r3, #12]
+ 80009c6: 4b16 ldr r3, [pc, #88] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009c8: 22c0 movs r2, #192 ; 0xc0
+ 80009ca: 60da str r2, [r3, #12]
//USART1->BRR = 208; /* 230400 */
USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
- 8000948: 4b0c ldr r3, [pc, #48] ; (800097c <usart_dma_init+0x78>)
- 800094a: 22c0 movs r2, #192 ; 0xc0
- 800094c: 0292 lsls r2, r2, #10
- 800094e: 605a str r2, [r3, #4]
+ 80009cc: 4b14 ldr r3, [pc, #80] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009ce: 22c0 movs r2, #192 ; 0xc0
+ 80009d0: 0292 lsls r2, r2, #10
+ 80009d2: 605a str r2, [r3, #4]
USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
- 8000950: 4b0a ldr r3, [pc, #40] ; (800097c <usart_dma_init+0x78>)
- 8000952: 689a ldr r2, [r3, #8]
- 8000954: 4b09 ldr r3, [pc, #36] ; (800097c <usart_dma_init+0x78>)
- 8000956: 2180 movs r1, #128 ; 0x80
- 8000958: 430a orrs r2, r1
- 800095a: 609a str r2, [r3, #8]
+ 80009d4: 4b12 ldr r3, [pc, #72] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009d6: 689a ldr r2, [r3, #8]
+ 80009d8: 4b11 ldr r3, [pc, #68] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009da: 2180 movs r1, #128 ; 0x80
+ 80009dc: 430a orrs r2, r1
+ 80009de: 609a str r2, [r3, #8]
+
/* Enable receive interrupt */
- //NVIC_EnableIRQ(USART1_IRQn);
- //NVIC_SetPriority(USART1_IRQn, 1);
+ NVIC_EnableIRQ(USART1_IRQn);
+ 80009e0: 201b movs r0, #27
+ 80009e2: f7ff ff1b bl 800081c <NVIC_EnableIRQ>
+ NVIC_SetPriority(USART1_IRQn, 3<<5);
+ 80009e6: 2160 movs r1, #96 ; 0x60
+ 80009e8: 201b movs r0, #27
+ 80009ea: f7ff ff45 bl 8000878 <NVIC_SetPriority>
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
- 800095c: 4b07 ldr r3, [pc, #28] ; (800097c <usart_dma_init+0x78>)
- 800095e: 681a ldr r2, [r3, #0]
- 8000960: 4b06 ldr r3, [pc, #24] ; (800097c <usart_dma_init+0x78>)
- 8000962: 2101 movs r1, #1
- 8000964: 430a orrs r2, r1
- 8000966: 601a str r2, [r3, #0]
+ 80009ee: 4b0c ldr r3, [pc, #48] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009f0: 681a ldr r2, [r3, #0]
+ 80009f2: 4b0b ldr r3, [pc, #44] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009f4: 2101 movs r1, #1
+ 80009f6: 430a orrs r2, r1
+ 80009f8: 601a str r2, [r3, #0]
}
- 8000968: 46c0 nop ; (mov r8, r8)
- 800096a: 46bd mov sp, r7
- 800096c: bd80 pop {r7, pc}
- 800096e: 46c0 nop ; (mov r8, r8)
- 8000970: 20000110 .word 0x20000110
- 8000974: 4002001c .word 0x4002001c
- 8000978: 40013828 .word 0x40013828
- 800097c: 40013800 .word 0x40013800
- 8000980: 0000202c .word 0x0000202c
-
-08000984 <usart_schedule_dma>:
+ 80009fa: 46c0 nop ; (mov r8, r8)
+ 80009fc: 46bd mov sp, r7
+ 80009fe: b002 add sp, #8
+ 8000a00: bd80 pop {r7, pc}
+ 8000a02: 46c0 nop ; (mov r8, r8)
+ 8000a04: 20000198 .word 0x20000198
+ 8000a08: 20000148 .word 0x20000148
+ 8000a0c: 4002001c .word 0x4002001c
+ 8000a10: 40013828 .word 0x40013828
+ 8000a14: 40020030 .word 0x40020030
+ 8000a18: 40023000 .word 0x40023000
+ 8000a1c: 00001042 .word 0x00001042
+ 8000a20: 40013800 .word 0x40013800
+ 8000a24: 0000202c .word 0x0000202c
+
+08000a28 <USART1_IRQHandler>:
+
+void USART1_IRQHandler() {
+ 8000a28: b580 push {r7, lr}
+ 8000a2a: b086 sub sp, #24
+ 8000a2c: af00 add r7, sp, #0
+ uint32_t isr = USART1->ISR;
+ 8000a2e: 4b41 ldr r3, [pc, #260] ; (8000b34 <USART1_IRQHandler+0x10c>)
+ 8000a30: 69db ldr r3, [r3, #28]
+ 8000a32: 613b str r3, [r7, #16]
+
+ if (isr & USART_ISR_ORE) {
+ 8000a34: 693b ldr r3, [r7, #16]
+ 8000a36: 2208 movs r2, #8
+ 8000a38: 4013 ands r3, r2
+ 8000a3a: d008 beq.n 8000a4e <USART1_IRQHandler+0x26>
+ USART1->ICR = USART_ICR_ORECF;
+ 8000a3c: 4b3d ldr r3, [pc, #244] ; (8000b34 <USART1_IRQHandler+0x10c>)
+ 8000a3e: 2208 movs r2, #8
+ 8000a40: 621a str r2, [r3, #32]
+ rx_overruns++;
+ 8000a42: 4b3d ldr r3, [pc, #244] ; (8000b38 <USART1_IRQHandler+0x110>)
+ 8000a44: 681b ldr r3, [r3, #0]
+ 8000a46: 1c5a adds r2, r3, #1
+ 8000a48: 4b3b ldr r3, [pc, #236] ; (8000b38 <USART1_IRQHandler+0x110>)
+ 8000a4a: 601a str r2, [r3, #0]
+ return;
+ 8000a4c: e06f b.n 8000b2e <USART1_IRQHandler+0x106>
+ }
+
+ if (isr & USART_ISR_RXNE) {
+ 8000a4e: 693b ldr r3, [r7, #16]
+ 8000a50: 2220 movs r2, #32
+ 8000a52: 4013 ands r3, r2
+ 8000a54: d100 bne.n 8000a58 <USART1_IRQHandler+0x30>
+ 8000a56: e06a b.n 8000b2e <USART1_IRQHandler+0x106>
+ uint8_t c = USART1->RDR;
+ 8000a58: 4b36 ldr r3, [pc, #216] ; (8000b34 <USART1_IRQHandler+0x10c>)
+ 8000a5a: 8c9b ldrh r3, [r3, #36] ; 0x24
+ 8000a5c: b29a uxth r2, r3
+ 8000a5e: 210f movs r1, #15
+ 8000a60: 187b adds r3, r7, r1
+ 8000a62: 701a strb r2, [r3, #0]
+
+ int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c);
+ 8000a64: 187b adds r3, r7, r1
+ 8000a66: 781b ldrb r3, [r3, #0]
+ 8000a68: 4934 ldr r1, [pc, #208] ; (8000b3c <USART1_IRQHandler+0x114>)
+ 8000a6a: 4835 ldr r0, [pc, #212] ; (8000b40 <USART1_IRQHandler+0x118>)
+ 8000a6c: 2220 movs r2, #32
+ 8000a6e: f000 fb0d bl 800108c <cobs_decode_incremental>
+ 8000a72: 0003 movs r3, r0
+ 8000a74: 60bb str r3, [r7, #8]
+ if (rc == 0) /* packet still incomplete */
+ 8000a76: 68bb ldr r3, [r7, #8]
+ 8000a78: 2b00 cmp r3, #0
+ 8000a7a: d057 beq.n 8000b2c <USART1_IRQHandler+0x104>
+ return;
+
+ if (rc < 0) {
+ 8000a7c: 68bb ldr r3, [r7, #8]
+ 8000a7e: 2b00 cmp r3, #0
+ 8000a80: da05 bge.n 8000a8e <USART1_IRQHandler+0x66>
+ rx_framing_errors++;
+ 8000a82: 4b30 ldr r3, [pc, #192] ; (8000b44 <USART1_IRQHandler+0x11c>)
+ 8000a84: 681b ldr r3, [r3, #0]
+ 8000a86: 1c5a adds r2, r3, #1
+ 8000a88: 4b2e ldr r3, [pc, #184] ; (8000b44 <USART1_IRQHandler+0x11c>)
+ 8000a8a: 601a str r2, [r3, #0]
+ return;
+ 8000a8c: e04f b.n 8000b2e <USART1_IRQHandler+0x106>
+ }
+
+ /* A complete frame received */
+ if (rc != 2) {
+ 8000a8e: 68bb ldr r3, [r7, #8]
+ 8000a90: 2b02 cmp r3, #2
+ 8000a92: d005 beq.n 8000aa0 <USART1_IRQHandler+0x78>
+ rx_protocol_errors++;
+ 8000a94: 4b2c ldr r3, [pc, #176] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000a96: 681b ldr r3, [r3, #0]
+ 8000a98: 1c5a adds r2, r3, #1
+ 8000a9a: 4b2b ldr r3, [pc, #172] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000a9c: 601a str r2, [r3, #0]
+ return;
+ 8000a9e: e046 b.n 8000b2e <USART1_IRQHandler+0x106>
+ }
+
+ volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf;
+ 8000aa0: 4b26 ldr r3, [pc, #152] ; (8000b3c <USART1_IRQHandler+0x114>)
+ 8000aa2: 607b str r3, [r7, #4]
+
+ switch (pkt->type) {
+ 8000aa4: 687b ldr r3, [r7, #4]
+ 8000aa6: 781b ldrb r3, [r3, #0]
+ 8000aa8: b2db uxtb r3, r3
+ 8000aaa: 2b03 cmp r3, #3
+ 8000aac: d026 beq.n 8000afc <USART1_IRQHandler+0xd4>
+ 8000aae: dc33 bgt.n 8000b18 <USART1_IRQHandler+0xf0>
+ 8000ab0: 2b01 cmp r3, #1
+ 8000ab2: d002 beq.n 8000aba <USART1_IRQHandler+0x92>
+ 8000ab4: 2b02 cmp r3, #2
+ 8000ab6: d013 beq.n 8000ae0 <USART1_IRQHandler+0xb8>
+ 8000ab8: e02e b.n 8000b18 <USART1_IRQHandler+0xf0>
+ case CTRL_PKT_RESET:
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ 8000aba: 2300 movs r3, #0
+ 8000abc: 617b str r3, [r7, #20]
+ 8000abe: e00b b.n 8000ad8 <USART1_IRQHandler+0xb0>
+ usart_tx_buf.packet_start[i] = -1;
+ 8000ac0: 4a22 ldr r2, [pc, #136] ; (8000b4c <USART1_IRQHandler+0x124>)
+ 8000ac2: 697b ldr r3, [r7, #20]
+ 8000ac4: 3302 adds r3, #2
+ 8000ac6: 009b lsls r3, r3, #2
+ 8000ac8: 18d3 adds r3, r2, r3
+ 8000aca: 3304 adds r3, #4
+ 8000acc: 2201 movs r2, #1
+ 8000ace: 4252 negs r2, r2
+ 8000ad0: 601a str r2, [r3, #0]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ 8000ad2: 697b ldr r3, [r7, #20]
+ 8000ad4: 3301 adds r3, #1
+ 8000ad6: 617b str r3, [r7, #20]
+ 8000ad8: 697b ldr r3, [r7, #20]
+ 8000ada: 2b04 cmp r3, #4
+ 8000adc: d9f0 bls.n 8000ac0 <USART1_IRQHandler+0x98>
+ break;
+ 8000ade: e024 b.n 8000b2a <USART1_IRQHandler+0x102>
+
+ case CTRL_PKT_ACK:
+ if (usart_ack_packet(pkt->orig_id))
+ 8000ae0: 687b ldr r3, [r7, #4]
+ 8000ae2: 785b ldrb r3, [r3, #1]
+ 8000ae4: b2db uxtb r3, r3
+ 8000ae6: 0018 movs r0, r3
+ 8000ae8: f000 f86c bl 8000bc4 <usart_ack_packet>
+ 8000aec: 1e03 subs r3, r0, #0
+ 8000aee: d019 beq.n 8000b24 <USART1_IRQHandler+0xfc>
+ rx_protocol_errors++;
+ 8000af0: 4b15 ldr r3, [pc, #84] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000af2: 681b ldr r3, [r3, #0]
+ 8000af4: 1c5a adds r2, r3, #1
+ 8000af6: 4b14 ldr r3, [pc, #80] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000af8: 601a str r2, [r3, #0]
+ break;
+ 8000afa: e013 b.n 8000b24 <USART1_IRQHandler+0xfc>
+
+ case CTRL_PKT_RETRANSMIT:
+ if (usart_retransmit_packet(pkt->orig_id))
+ 8000afc: 687b ldr r3, [r7, #4]
+ 8000afe: 785b ldrb r3, [r3, #1]
+ 8000b00: b2db uxtb r3, r3
+ 8000b02: 0018 movs r0, r3
+ 8000b04: f000 f904 bl 8000d10 <usart_retransmit_packet>
+ 8000b08: 1e03 subs r3, r0, #0
+ 8000b0a: d00d beq.n 8000b28 <USART1_IRQHandler+0x100>
+ rx_protocol_errors++;
+ 8000b0c: 4b0e ldr r3, [pc, #56] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000b0e: 681b ldr r3, [r3, #0]
+ 8000b10: 1c5a adds r2, r3, #1
+ 8000b12: 4b0d ldr r3, [pc, #52] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000b14: 601a str r2, [r3, #0]
+ break;
+ 8000b16: e007 b.n 8000b28 <USART1_IRQHandler+0x100>
+
+ default:
+ rx_protocol_errors++;
+ 8000b18: 4b0b ldr r3, [pc, #44] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000b1a: 681b ldr r3, [r3, #0]
+ 8000b1c: 1c5a adds r2, r3, #1
+ 8000b1e: 4b0a ldr r3, [pc, #40] ; (8000b48 <USART1_IRQHandler+0x120>)
+ 8000b20: 601a str r2, [r3, #0]
+ }
+ return;
+ 8000b22: e004 b.n 8000b2e <USART1_IRQHandler+0x106>
+ break;
+ 8000b24: 46c0 nop ; (mov r8, r8)
+ 8000b26: e002 b.n 8000b2e <USART1_IRQHandler+0x106>
+ break;
+ 8000b28: 46c0 nop ; (mov r8, r8)
+ return;
+ 8000b2a: e000 b.n 8000b2e <USART1_IRQHandler+0x106>
+ return;
+ 8000b2c: 46c0 nop ; (mov r8, r8)
+ }
+}
+ 8000b2e: 46bd mov sp, r7
+ 8000b30: b006 add sp, #24
+ 8000b32: bd80 pop {r7, pc}
+ 8000b34: 40013800 .word 0x40013800
+ 8000b38: 2000013c .word 0x2000013c
+ 8000b3c: 20000150 .word 0x20000150
+ 8000b40: 20000148 .word 0x20000148
+ 8000b44: 20000140 .word 0x20000140
+ 8000b48: 20000144 .word 0x20000144
+ 8000b4c: 20000198 .word 0x20000198
+
+08000b50 <usart_schedule_dma>:
+
void usart_schedule_dma() {
- 8000984: b580 push {r7, lr}
- 8000986: b084 sub sp, #16
- 8000988: af00 add r7, sp, #0
+ 8000b50: b580 push {r7, lr}
+ 8000b52: b084 sub sp, #16
+ 8000b54: af00 add r7, sp, #0
/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
- 800098a: 4b19 ldr r3, [pc, #100] ; (80009f0 <usart_schedule_dma+0x6c>)
- 800098c: 60bb str r3, [r7, #8]
+ 8000b56: 4b19 ldr r3, [pc, #100] ; (8000bbc <usart_schedule_dma+0x6c>)
+ 8000b58: 60bb str r3, [r7, #8]
- size_t xfr_len, xfr_start = buf->xfr_end;
- 800098e: 68bb ldr r3, [r7, #8]
- 8000990: 685b ldr r3, [r3, #4]
- 8000992: 607b str r3, [r7, #4]
+ ssize_t xfr_len, xfr_start = buf->xfr_end;
+ 8000b5a: 68bb ldr r3, [r7, #8]
+ 8000b5c: 685b ldr r3, [r3, #4]
+ 8000b5e: 607b str r3, [r7, #4]
if (buf->wr_pos > xfr_start) /* no wraparound */
- 8000994: 68bb ldr r3, [r7, #8]
- 8000996: 689b ldr r3, [r3, #8]
- 8000998: 687a ldr r2, [r7, #4]
- 800099a: 429a cmp r2, r3
- 800099c: d205 bcs.n 80009aa <usart_schedule_dma+0x26>
+ 8000b60: 68bb ldr r3, [r7, #8]
+ 8000b62: 689b ldr r3, [r3, #8]
+ 8000b64: 687a ldr r2, [r7, #4]
+ 8000b66: 429a cmp r2, r3
+ 8000b68: da05 bge.n 8000b76 <usart_schedule_dma+0x26>
xfr_len = buf->wr_pos - xfr_start;
- 800099e: 68bb ldr r3, [r7, #8]
- 80009a0: 689a ldr r2, [r3, #8]
- 80009a2: 687b ldr r3, [r7, #4]
- 80009a4: 1ad3 subs r3, r2, r3
- 80009a6: 60fb str r3, [r7, #12]
- 80009a8: e004 b.n 80009b4 <usart_schedule_dma+0x30>
+ 8000b6a: 68bb ldr r3, [r7, #8]
+ 8000b6c: 689a ldr r2, [r3, #8]
+ 8000b6e: 687b ldr r3, [r7, #4]
+ 8000b70: 1ad3 subs r3, r2, r3
+ 8000b72: 60fb str r3, [r7, #12]
+ 8000b74: e004 b.n 8000b80 <usart_schedule_dma+0x30>
else /* wraparound */
xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */
- 80009aa: 687b ldr r3, [r7, #4]
- 80009ac: 2280 movs r2, #128 ; 0x80
- 80009ae: 00d2 lsls r2, r2, #3
- 80009b0: 1ad3 subs r3, r2, r3
- 80009b2: 60fb str r3, [r7, #12]
+ 8000b76: 687b ldr r3, [r7, #4]
+ 8000b78: 2280 movs r2, #128 ; 0x80
+ 8000b7a: 0092 lsls r2, r2, #2
+ 8000b7c: 1ad3 subs r3, r2, r3
+ 8000b7e: 60fb str r3, [r7, #12]
buf->xfr_start = xfr_start;
- 80009b4: 68bb ldr r3, [r7, #8]
- 80009b6: 687a ldr r2, [r7, #4]
- 80009b8: 601a str r2, [r3, #0]
+ 8000b80: 68bb ldr r3, [r7, #8]
+ 8000b82: 687a ldr r2, [r7, #4]
+ 8000b84: 601a str r2, [r3, #0]
buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
- 80009ba: 687a ldr r2, [r7, #4]
- 80009bc: 68fb ldr r3, [r7, #12]
- 80009be: 18d3 adds r3, r2, r3
- 80009c0: 059b lsls r3, r3, #22
- 80009c2: 0d9a lsrs r2, r3, #22
- 80009c4: 68bb ldr r3, [r7, #8]
- 80009c6: 605a str r2, [r3, #4]
+ 8000b86: 687a ldr r2, [r7, #4]
+ 8000b88: 68fb ldr r3, [r7, #12]
+ 8000b8a: 18d3 adds r3, r2, r3
+ 8000b8c: 05db lsls r3, r3, #23
+ 8000b8e: 0dda lsrs r2, r3, #23
+ 8000b90: 68bb ldr r3, [r7, #8]
+ 8000b92: 605a str r2, [r3, #4]
/* initiate transmission of new buffer */
DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start);
- 80009c8: 68bb ldr r3, [r7, #8]
- 80009ca: 330c adds r3, #12
- 80009cc: 001a movs r2, r3
- 80009ce: 687b ldr r3, [r7, #4]
- 80009d0: 18d2 adds r2, r2, r3
- 80009d2: 4b08 ldr r3, [pc, #32] ; (80009f4 <usart_schedule_dma+0x70>)
- 80009d4: 60da str r2, [r3, #12]
+ 8000b94: 68bb ldr r3, [r7, #8]
+ 8000b96: 3320 adds r3, #32
+ 8000b98: 001a movs r2, r3
+ 8000b9a: 687b ldr r3, [r7, #4]
+ 8000b9c: 18d2 adds r2, r2, r3
+ 8000b9e: 4b08 ldr r3, [pc, #32] ; (8000bc0 <usart_schedule_dma+0x70>)
+ 8000ba0: 60da str r2, [r3, #12]
DMA1_Channel2->CNDTR = xfr_len;
- 80009d6: 4b07 ldr r3, [pc, #28] ; (80009f4 <usart_schedule_dma+0x70>)
- 80009d8: 68fa ldr r2, [r7, #12]
- 80009da: 605a str r2, [r3, #4]
+ 8000ba2: 4b07 ldr r3, [pc, #28] ; (8000bc0 <usart_schedule_dma+0x70>)
+ 8000ba4: 68fa ldr r2, [r7, #12]
+ 8000ba6: 605a str r2, [r3, #4]
DMA1_Channel2->CCR |= DMA_CCR_EN;
- 80009dc: 4b05 ldr r3, [pc, #20] ; (80009f4 <usart_schedule_dma+0x70>)
- 80009de: 681a ldr r2, [r3, #0]
- 80009e0: 4b04 ldr r3, [pc, #16] ; (80009f4 <usart_schedule_dma+0x70>)
- 80009e2: 2101 movs r1, #1
- 80009e4: 430a orrs r2, r1
- 80009e6: 601a str r2, [r3, #0]
+ 8000ba8: 4b05 ldr r3, [pc, #20] ; (8000bc0 <usart_schedule_dma+0x70>)
+ 8000baa: 681a ldr r2, [r3, #0]
+ 8000bac: 4b04 ldr r3, [pc, #16] ; (8000bc0 <usart_schedule_dma+0x70>)
+ 8000bae: 2101 movs r1, #1
+ 8000bb0: 430a orrs r2, r1
+ 8000bb2: 601a str r2, [r3, #0]
+}
+ 8000bb4: 46c0 nop ; (mov r8, r8)
+ 8000bb6: 46bd mov sp, r7
+ 8000bb8: b004 add sp, #16
+ 8000bba: bd80 pop {r7, pc}
+ 8000bbc: 20000198 .word 0x20000198
+ 8000bc0: 4002001c .word 0x4002001c
+
+08000bc4 <usart_ack_packet>:
+
+int usart_ack_packet(uint8_t idx) {
+ 8000bc4: b580 push {r7, lr}
+ 8000bc6: b082 sub sp, #8
+ 8000bc8: af00 add r7, sp, #0
+ 8000bca: 0002 movs r2, r0
+ 8000bcc: 1dfb adds r3, r7, #7
+ 8000bce: 701a strb r2, [r3, #0]
+ if (idx > ARRAY_LEN(usart_tx_buf.packet_start))
+ 8000bd0: 1dfb adds r3, r7, #7
+ 8000bd2: 781b ldrb r3, [r3, #0]
+ 8000bd4: 2b05 cmp r3, #5
+ 8000bd6: d902 bls.n 8000bde <usart_ack_packet+0x1a>
+ return -EINVAL;
+ 8000bd8: 2316 movs r3, #22
+ 8000bda: 425b negs r3, r3
+ 8000bdc: e00a b.n 8000bf4 <usart_ack_packet+0x30>
+
+ usart_tx_buf.packet_start[idx] = -1;
+ 8000bde: 1dfb adds r3, r7, #7
+ 8000be0: 781b ldrb r3, [r3, #0]
+ 8000be2: 4a06 ldr r2, [pc, #24] ; (8000bfc <usart_ack_packet+0x38>)
+ 8000be4: 3302 adds r3, #2
+ 8000be6: 009b lsls r3, r3, #2
+ 8000be8: 18d3 adds r3, r2, r3
+ 8000bea: 3304 adds r3, #4
+ 8000bec: 2201 movs r2, #1
+ 8000bee: 4252 negs r2, r2
+ 8000bf0: 601a str r2, [r3, #0]
+ return 0;
+ 8000bf2: 2300 movs r3, #0
}
- 80009e8: 46c0 nop ; (mov r8, r8)
- 80009ea: 46bd mov sp, r7
- 80009ec: b004 add sp, #16
- 80009ee: bd80 pop {r7, pc}
- 80009f0: 20000110 .word 0x20000110
- 80009f4: 4002001c .word 0x4002001c
-
-080009f8 <usart_dma_fifo_push>:
-
-int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) {
- 80009f8: b580 push {r7, lr}
- 80009fa: b082 sub sp, #8
- 80009fc: af00 add r7, sp, #0
- 80009fe: 6078 str r0, [r7, #4]
- 8000a00: 000a movs r2, r1
- 8000a02: 1cfb adds r3, r7, #3
- 8000a04: 701a strb r2, [r3, #0]
+ 8000bf4: 0018 movs r0, r3
+ 8000bf6: 46bd mov sp, r7
+ 8000bf8: b002 add sp, #8
+ 8000bfa: bd80 pop {r7, pc}
+ 8000bfc: 20000198 .word 0x20000198
+
+08000c00 <usart_dma_fifo_push>:
+
+int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
+ 8000c00: b580 push {r7, lr}
+ 8000c02: b084 sub sp, #16
+ 8000c04: af00 add r7, sp, #0
+ 8000c06: 6078 str r0, [r7, #4]
+ 8000c08: 000a movs r2, r1
+ 8000c0a: 1cfb adds r3, r7, #3
+ 8000c0c: 701a strb r2, [r3, #0]
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
- 8000a06: 200a movs r0, #10
- 8000a08: f7ff fef6 bl 80007f8 <NVIC_DisableIRQ>
-
- if (buf->wr_pos == buf->xfr_start) {
- 8000a0c: 687b ldr r3, [r7, #4]
- 8000a0e: 689a ldr r2, [r3, #8]
- 8000a10: 687b ldr r3, [r7, #4]
- 8000a12: 681b ldr r3, [r3, #0]
- 8000a14: 429a cmp r2, r3
- 8000a16: d105 bne.n 8000a24 <usart_dma_fifo_push+0x2c>
- NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000a18: 200a movs r0, #10
- 8000a1a: f7ff fed7 bl 80007cc <NVIC_EnableIRQ>
- return -EBUSY;
- 8000a1e: 2310 movs r3, #16
- 8000a20: 425b negs r3, r3
- 8000a22: e011 b.n 8000a48 <usart_dma_fifo_push+0x50>
+ 8000c0e: 200a movs r0, #10
+ 8000c10: f7ff fe1a bl 8000848 <NVIC_DisableIRQ>
+
+ /* If the write pointer hit any unacknowledged packet start position we can't advance it.
+ * Packet start positions are unordered and we have to scan here. */
+ for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
+ 8000c14: 2300 movs r3, #0
+ 8000c16: 60fb str r3, [r7, #12]
+ 8000c18: e013 b.n 8000c42 <usart_dma_fifo_push+0x42>
+ if (buf->wr_pos == buf->packet_start[i]) {
+ 8000c1a: 687b ldr r3, [r7, #4]
+ 8000c1c: 689a ldr r2, [r3, #8]
+ 8000c1e: 6879 ldr r1, [r7, #4]
+ 8000c20: 68fb ldr r3, [r7, #12]
+ 8000c22: 3302 adds r3, #2
+ 8000c24: 009b lsls r3, r3, #2
+ 8000c26: 18cb adds r3, r1, r3
+ 8000c28: 3304 adds r3, #4
+ 8000c2a: 681b ldr r3, [r3, #0]
+ 8000c2c: 429a cmp r2, r3
+ 8000c2e: d105 bne.n 8000c3c <usart_dma_fifo_push+0x3c>
+ NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ 8000c30: 200a movs r0, #10
+ 8000c32: f7ff fdf3 bl 800081c <NVIC_EnableIRQ>
+ return -EBUSY;
+ 8000c36: 2310 movs r3, #16
+ 8000c38: 425b negs r3, r3
+ 8000c3a: e019 b.n 8000c70 <usart_dma_fifo_push+0x70>
+ for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
+ 8000c3c: 68fb ldr r3, [r7, #12]
+ 8000c3e: 3301 adds r3, #1
+ 8000c40: 60fb str r3, [r7, #12]
+ 8000c42: 68fb ldr r3, [r7, #12]
+ 8000c44: 2b04 cmp r3, #4
+ 8000c46: d9e8 bls.n 8000c1a <usart_dma_fifo_push+0x1a>
+ }
}
+ /* write byte, then increment to avoid racing the DMA ISR reading wr_pos */
buf->data[buf->wr_pos] = c;
- 8000a24: 687b ldr r3, [r7, #4]
- 8000a26: 689b ldr r3, [r3, #8]
- 8000a28: 687a ldr r2, [r7, #4]
- 8000a2a: 18d3 adds r3, r2, r3
- 8000a2c: 1cfa adds r2, r7, #3
- 8000a2e: 7812 ldrb r2, [r2, #0]
- 8000a30: 731a strb r2, [r3, #12]
+ 8000c48: 687b ldr r3, [r7, #4]
+ 8000c4a: 689b ldr r3, [r3, #8]
+ 8000c4c: 687a ldr r2, [r7, #4]
+ 8000c4e: 2120 movs r1, #32
+ 8000c50: 18d3 adds r3, r2, r3
+ 8000c52: 185b adds r3, r3, r1
+ 8000c54: 1cfa adds r2, r7, #3
+ 8000c56: 7812 ldrb r2, [r2, #0]
+ 8000c58: 701a strb r2, [r3, #0]
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
- 8000a32: 687b ldr r3, [r7, #4]
- 8000a34: 689b ldr r3, [r3, #8]
- 8000a36: 3301 adds r3, #1
- 8000a38: 059b lsls r3, r3, #22
- 8000a3a: 0d9a lsrs r2, r3, #22
- 8000a3c: 687b ldr r3, [r7, #4]
- 8000a3e: 609a str r2, [r3, #8]
+ 8000c5a: 687b ldr r3, [r7, #4]
+ 8000c5c: 689b ldr r3, [r3, #8]
+ 8000c5e: 3301 adds r3, #1
+ 8000c60: 05db lsls r3, r3, #23
+ 8000c62: 0dda lsrs r2, r3, #23
+ 8000c64: 687b ldr r3, [r7, #4]
+ 8000c66: 609a str r2, [r3, #8]
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000a40: 200a movs r0, #10
- 8000a42: f7ff fec3 bl 80007cc <NVIC_EnableIRQ>
+ 8000c68: 200a movs r0, #10
+ 8000c6a: f7ff fdd7 bl 800081c <NVIC_EnableIRQ>
return 0;
- 8000a46: 2300 movs r3, #0
+ 8000c6e: 2300 movs r3, #0
}
- 8000a48: 0018 movs r0, r3
- 8000a4a: 46bd mov sp, r7
- 8000a4c: b002 add sp, #8
- 8000a4e: bd80 pop {r7, pc}
-
-08000a50 <usart_putc>:
-
-int usart_putc(char c) {
- 8000a50: b580 push {r7, lr}
- 8000a52: b082 sub sp, #8
- 8000a54: af00 add r7, sp, #0
- 8000a56: 0002 movs r2, r0
- 8000a58: 1dfb adds r3, r7, #7
- 8000a5a: 701a strb r2, [r3, #0]
+ 8000c70: 0018 movs r0, r3
+ 8000c72: 46bd mov sp, r7
+ 8000c74: b004 add sp, #16
+ 8000c76: bd80 pop {r7, pc}
+
+08000c78 <usart_putc>:
+
+int usart_putc(uint8_t c) {
+ 8000c78: b580 push {r7, lr}
+ 8000c7a: b082 sub sp, #8
+ 8000c7c: af00 add r7, sp, #0
+ 8000c7e: 0002 movs r2, r0
+ 8000c80: 1dfb adds r3, r7, #7
+ 8000c82: 701a strb r2, [r3, #0]
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
- 8000a5c: 46c0 nop ; (mov r8, r8)
- 8000a5e: 1dfb adds r3, r7, #7
- 8000a60: 781a ldrb r2, [r3, #0]
- 8000a62: 4b06 ldr r3, [pc, #24] ; (8000a7c <usart_putc+0x2c>)
- 8000a64: 0011 movs r1, r2
- 8000a66: 0018 movs r0, r3
- 8000a68: f7ff ffc6 bl 80009f8 <usart_dma_fifo_push>
- 8000a6c: 0003 movs r3, r0
- 8000a6e: 3310 adds r3, #16
- 8000a70: d0f5 beq.n 8000a5e <usart_putc+0xe>
+ 8000c84: 46c0 nop ; (mov r8, r8)
+ 8000c86: 1dfb adds r3, r7, #7
+ 8000c88: 781a ldrb r2, [r3, #0]
+ 8000c8a: 4b06 ldr r3, [pc, #24] ; (8000ca4 <usart_putc+0x2c>)
+ 8000c8c: 0011 movs r1, r2
+ 8000c8e: 0018 movs r0, r3
+ 8000c90: f7ff ffb6 bl 8000c00 <usart_dma_fifo_push>
+ 8000c94: 0003 movs r3, r0
+ 8000c96: 3310 adds r3, #16
+ 8000c98: d0f5 beq.n 8000c86 <usart_putc+0xe>
/* idle */
}
return 0;
- 8000a72: 2300 movs r3, #0
+ 8000c9a: 2300 movs r3, #0
}
- 8000a74: 0018 movs r0, r3
- 8000a76: 46bd mov sp, r7
- 8000a78: b002 add sp, #8
- 8000a7a: bd80 pop {r7, pc}
- 8000a7c: 20000110 .word 0x20000110
-
-08000a80 <usart_putc_nonblocking>:
-
-int usart_putc_nonblocking(char c) {
- 8000a80: b580 push {r7, lr}
- 8000a82: b082 sub sp, #8
- 8000a84: af00 add r7, sp, #0
- 8000a86: 0002 movs r2, r0
- 8000a88: 1dfb adds r3, r7, #7
- 8000a8a: 701a strb r2, [r3, #0]
+ 8000c9c: 0018 movs r0, r3
+ 8000c9e: 46bd mov sp, r7
+ 8000ca0: b002 add sp, #8
+ 8000ca2: bd80 pop {r7, pc}
+ 8000ca4: 20000198 .word 0x20000198
+
+08000ca8 <usart_putc_nonblocking>:
+
+int usart_putc_nonblocking(uint8_t c) {
+ 8000ca8: b580 push {r7, lr}
+ 8000caa: b082 sub sp, #8
+ 8000cac: af00 add r7, sp, #0
+ 8000cae: 0002 movs r2, r0
+ 8000cb0: 1dfb adds r3, r7, #7
+ 8000cb2: 701a strb r2, [r3, #0]
return usart_dma_fifo_push(&usart_tx_buf, c);
- 8000a8c: 1dfb adds r3, r7, #7
- 8000a8e: 781a ldrb r2, [r3, #0]
- 8000a90: 4b04 ldr r3, [pc, #16] ; (8000aa4 <usart_putc_nonblocking+0x24>)
- 8000a92: 0011 movs r1, r2
- 8000a94: 0018 movs r0, r3
- 8000a96: f7ff ffaf bl 80009f8 <usart_dma_fifo_push>
- 8000a9a: 0003 movs r3, r0
+ 8000cb4: 1dfb adds r3, r7, #7
+ 8000cb6: 781a ldrb r2, [r3, #0]
+ 8000cb8: 4b04 ldr r3, [pc, #16] ; (8000ccc <usart_putc_nonblocking+0x24>)
+ 8000cba: 0011 movs r1, r2
+ 8000cbc: 0018 movs r0, r3
+ 8000cbe: f7ff ff9f bl 8000c00 <usart_dma_fifo_push>
+ 8000cc2: 0003 movs r3, r0
}
- 8000a9c: 0018 movs r0, r3
- 8000a9e: 46bd mov sp, r7
- 8000aa0: b002 add sp, #8
- 8000aa2: bd80 pop {r7, pc}
- 8000aa4: 20000110 .word 0x20000110
+ 8000cc4: 0018 movs r0, r3
+ 8000cc6: 46bd mov sp, r7
+ 8000cc8: b002 add sp, #8
+ 8000cca: bd80 pop {r7, pc}
+ 8000ccc: 20000198 .word 0x20000198
-08000aa8 <DMA1_Channel2_3_IRQHandler>:
+08000cd0 <DMA1_Channel2_3_IRQHandler>:
void DMA1_Channel2_3_IRQHandler(void) {
- 8000aa8: b580 push {r7, lr}
- 8000aaa: af00 add r7, sp, #0
+ 8000cd0: b580 push {r7, lr}
+ 8000cd2: af00 add r7, sp, #0
/* Transfer complete */
DMA1->IFCR |= DMA_IFCR_CTCIF2;
- 8000aac: 4b0b ldr r3, [pc, #44] ; (8000adc <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000aae: 685a ldr r2, [r3, #4]
- 8000ab0: 4b0a ldr r3, [pc, #40] ; (8000adc <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000ab2: 2120 movs r1, #32
- 8000ab4: 430a orrs r2, r1
- 8000ab6: 605a str r2, [r3, #4]
+ 8000cd4: 4b0b ldr r3, [pc, #44] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
+ 8000cd6: 685a ldr r2, [r3, #4]
+ 8000cd8: 4b0a ldr r3, [pc, #40] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
+ 8000cda: 2120 movs r1, #32
+ 8000cdc: 430a orrs r2, r1
+ 8000cde: 605a str r2, [r3, #4]
DMA1_Channel2->CCR &= ~DMA_CCR_EN;
- 8000ab8: 4b09 ldr r3, [pc, #36] ; (8000ae0 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000aba: 681a ldr r2, [r3, #0]
- 8000abc: 4b08 ldr r3, [pc, #32] ; (8000ae0 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000abe: 2101 movs r1, #1
- 8000ac0: 438a bics r2, r1
- 8000ac2: 601a str r2, [r3, #0]
+ 8000ce0: 4b09 ldr r3, [pc, #36] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000ce2: 681a ldr r2, [r3, #0]
+ 8000ce4: 4b08 ldr r3, [pc, #32] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000ce6: 2101 movs r1, #1
+ 8000ce8: 438a bics r2, r1
+ 8000cea: 601a str r2, [r3, #0]
if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */
- 8000ac4: 4b07 ldr r3, [pc, #28] ; (8000ae4 <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000ac6: 689a ldr r2, [r3, #8]
- 8000ac8: 4b06 ldr r3, [pc, #24] ; (8000ae4 <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000aca: 685b ldr r3, [r3, #4]
- 8000acc: 429a cmp r2, r3
- 8000ace: d001 beq.n 8000ad4 <DMA1_Channel2_3_IRQHandler+0x2c>
+ 8000cec: 4b07 ldr r3, [pc, #28] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000cee: 689a ldr r2, [r3, #8]
+ 8000cf0: 4b06 ldr r3, [pc, #24] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000cf2: 685b ldr r3, [r3, #4]
+ 8000cf4: 429a cmp r2, r3
+ 8000cf6: d001 beq.n 8000cfc <DMA1_Channel2_3_IRQHandler+0x2c>
usart_schedule_dma();
- 8000ad0: f7ff ff58 bl 8000984 <usart_schedule_dma>
+ 8000cf8: f7ff ff2a bl 8000b50 <usart_schedule_dma>
}
- 8000ad4: 46c0 nop ; (mov r8, r8)
- 8000ad6: 46bd mov sp, r7
- 8000ad8: bd80 pop {r7, pc}
- 8000ada: 46c0 nop ; (mov r8, r8)
- 8000adc: 40020000 .word 0x40020000
- 8000ae0: 4002001c .word 0x4002001c
- 8000ae4: 20000110 .word 0x20000110
-
-08000ae8 <usart_send_packet>:
-
-void usart_send_packet(const uint8_t *data, size_t len) {
- 8000ae8: b580 push {r7, lr}
- 8000aea: b082 sub sp, #8
- 8000aec: af00 add r7, sp, #0
- 8000aee: 6078 str r0, [r7, #4]
- 8000af0: 6039 str r1, [r7, #0]
- /* ignore return value as putf is blocking and always succeeds */
- (void)cobs_encode_usart(usart_putc, (char *)data, len);
- 8000af2: 683a ldr r2, [r7, #0]
- 8000af4: 6879 ldr r1, [r7, #4]
- 8000af6: 4b07 ldr r3, [pc, #28] ; (8000b14 <usart_send_packet+0x2c>)
- 8000af8: 0018 movs r0, r3
- 8000afa: f000 f89c bl 8000c36 <cobs_encode_usart>
+ 8000cfc: 46c0 nop ; (mov r8, r8)
+ 8000cfe: 46bd mov sp, r7
+ 8000d00: bd80 pop {r7, pc}
+ 8000d02: 46c0 nop ; (mov r8, r8)
+ 8000d04: 40020000 .word 0x40020000
+ 8000d08: 4002001c .word 0x4002001c
+ 8000d0c: 20000198 .word 0x20000198
+
+08000d10 <usart_retransmit_packet>:
+
+int usart_retransmit_packet(uint8_t idx) {
+ 8000d10: b590 push {r4, r7, lr}
+ 8000d12: b087 sub sp, #28
+ 8000d14: af00 add r7, sp, #0
+ 8000d16: 0002 movs r2, r0
+ 8000d18: 1dfb adds r3, r7, #7
+ 8000d1a: 701a strb r2, [r3, #0]
+ /* Disable ADC DMA IRQ to prevent write races */
+ NVIC_DisableIRQ(DMA1_Channel1_IRQn);
+ 8000d1c: 2009 movs r0, #9
+ 8000d1e: f7ff fd93 bl 8000848 <NVIC_DisableIRQ>
+
+ ssize_t i = usart_tx_buf.packet_start[idx];
+ 8000d22: 1dfb adds r3, r7, #7
+ 8000d24: 781b ldrb r3, [r3, #0]
+ 8000d26: 4a23 ldr r2, [pc, #140] ; (8000db4 <usart_retransmit_packet+0xa4>)
+ 8000d28: 3302 adds r3, #2
+ 8000d2a: 009b lsls r3, r3, #2
+ 8000d2c: 18d3 adds r3, r2, r3
+ 8000d2e: 3304 adds r3, #4
+ 8000d30: 681b ldr r3, [r3, #0]
+ 8000d32: 617b str r3, [r7, #20]
+ ssize_t start = i;
+ 8000d34: 697b ldr r3, [r7, #20]
+ 8000d36: 613b str r3, [r7, #16]
+
+ /* Copy packet */
+ uint8_t c;
+ while ((c = usart_tx_buf.data[i++])) {
+ 8000d38: e00f b.n 8000d5a <usart_retransmit_packet+0x4a>
+ if (usart_putc_nonblocking(c)) {
+ 8000d3a: 230f movs r3, #15
+ 8000d3c: 18fb adds r3, r7, r3
+ 8000d3e: 781b ldrb r3, [r3, #0]
+ 8000d40: 0018 movs r0, r3
+ 8000d42: f7ff ffb1 bl 8000ca8 <usart_putc_nonblocking>
+ 8000d46: 1e03 subs r3, r0, #0
+ 8000d48: d007 beq.n 8000d5a <usart_retransmit_packet+0x4a>
+ tx_overruns++;
+ 8000d4a: 4b1b ldr r3, [pc, #108] ; (8000db8 <usart_retransmit_packet+0xa8>)
+ 8000d4c: 681b ldr r3, [r3, #0]
+ 8000d4e: 1c5a adds r2, r3, #1
+ 8000d50: 4b19 ldr r3, [pc, #100] ; (8000db8 <usart_retransmit_packet+0xa8>)
+ 8000d52: 601a str r2, [r3, #0]
+ return -EBUSY;
+ 8000d54: 2310 movs r3, #16
+ 8000d56: 425b negs r3, r3
+ 8000d58: e028 b.n 8000dac <usart_retransmit_packet+0x9c>
+ while ((c = usart_tx_buf.data[i++])) {
+ 8000d5a: 697b ldr r3, [r7, #20]
+ 8000d5c: 1c5a adds r2, r3, #1
+ 8000d5e: 617a str r2, [r7, #20]
+ 8000d60: 240f movs r4, #15
+ 8000d62: 193a adds r2, r7, r4
+ 8000d64: 4913 ldr r1, [pc, #76] ; (8000db4 <usart_retransmit_packet+0xa4>)
+ 8000d66: 2020 movs r0, #32
+ 8000d68: 18cb adds r3, r1, r3
+ 8000d6a: 181b adds r3, r3, r0
+ 8000d6c: 781b ldrb r3, [r3, #0]
+ 8000d6e: 7013 strb r3, [r2, #0]
+ 8000d70: 193b adds r3, r7, r4
+ 8000d72: 781b ldrb r3, [r3, #0]
+ 8000d74: 2b00 cmp r3, #0
+ 8000d76: d1e0 bne.n 8000d3a <usart_retransmit_packet+0x2a>
+ }
+ }
- /* If the DMA stream is idle right now, schedule a transfer */
- if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
- 8000afe: 4b06 ldr r3, [pc, #24] ; (8000b18 <usart_send_packet+0x30>)
- 8000b00: 681b ldr r3, [r3, #0]
- 8000b02: 2201 movs r2, #1
- 8000b04: 4013 ands r3, r2
- 8000b06: d101 bne.n 8000b0c <usart_send_packet+0x24>
- usart_schedule_dma();
- 8000b08: f7ff ff3c bl 8000984 <usart_schedule_dma>
-}
- 8000b0c: 46c0 nop ; (mov r8, r8)
- 8000b0e: 46bd mov sp, r7
- 8000b10: b002 add sp, #8
- 8000b12: bd80 pop {r7, pc}
- 8000b14: 08000a51 .word 0x08000a51
- 8000b18: 4002001c .word 0x4002001c
-
-08000b1c <usart_send_packet_nonblocking>:
-
-int usart_send_packet_nonblocking(const uint8_t *data, size_t len) {
- 8000b1c: b580 push {r7, lr}
- 8000b1e: b084 sub sp, #16
- 8000b20: af00 add r7, sp, #0
- 8000b22: 6078 str r0, [r7, #4]
- 8000b24: 6039 str r1, [r7, #0]
- //if (rc)
- // return rc;
- /* END */
- static uint8_t x = 0;
+ /* Terminating null byte */
+ if (usart_putc_nonblocking(0)) {
+ 8000d78: 2000 movs r0, #0
+ 8000d7a: f7ff ff95 bl 8000ca8 <usart_putc_nonblocking>
+ 8000d7e: 1e03 subs r3, r0, #0
+ 8000d80: d007 beq.n 8000d92 <usart_retransmit_packet+0x82>
+ tx_overruns++;
+ 8000d82: 4b0d ldr r3, [pc, #52] ; (8000db8 <usart_retransmit_packet+0xa8>)
+ 8000d84: 681b ldr r3, [r3, #0]
+ 8000d86: 1c5a adds r2, r3, #1
+ 8000d88: 4b0b ldr r3, [pc, #44] ; (8000db8 <usart_retransmit_packet+0xa8>)
+ 8000d8a: 601a str r2, [r3, #0]
+ return -EBUSY;
+ 8000d8c: 2310 movs r3, #16
+ 8000d8e: 425b negs r3, r3
+ 8000d90: e00c b.n 8000dac <usart_retransmit_packet+0x9c>
+ }
+
+ /* Update start index */
+ usart_tx_buf.packet_start[idx] = start;
+ 8000d92: 1dfb adds r3, r7, #7
+ 8000d94: 781b ldrb r3, [r3, #0]
+ 8000d96: 4a07 ldr r2, [pc, #28] ; (8000db4 <usart_retransmit_packet+0xa4>)
+ 8000d98: 3302 adds r3, #2
+ 8000d9a: 009b lsls r3, r3, #2
+ 8000d9c: 18d3 adds r3, r2, r3
+ 8000d9e: 3304 adds r3, #4
+ 8000da0: 693a ldr r2, [r7, #16]
+ 8000da2: 601a str r2, [r3, #0]
+ NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+ 8000da4: 2009 movs r0, #9
+ 8000da6: f7ff fd39 bl 800081c <NVIC_EnableIRQ>
+ return 0;
+ 8000daa: 2300 movs r3, #0
+}
+ 8000dac: 0018 movs r0, r3
+ 8000dae: 46bd mov sp, r7
+ 8000db0: b007 add sp, #28
+ 8000db2: bd90 pop {r4, r7, pc}
+ 8000db4: 20000198 .word 0x20000198
+ 8000db8: 20000138 .word 0x20000138
+
+08000dbc <usart_send_packet_nonblocking>:
+
+/* len is the packet length including headers */
+int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
+ 8000dbc: b590 push {r4, r7, lr}
+ 8000dbe: b087 sub sp, #28
+ 8000dc0: af00 add r7, sp, #0
+ 8000dc2: 6078 str r0, [r7, #4]
+ 8000dc4: 6039 str r1, [r7, #0]
+
+ ssize_t start = usart_tx_buf.wr_pos;
+ 8000dc6: 4b40 ldr r3, [pc, #256] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
+ 8000dc8: 689b ldr r3, [r3, #8]
+ 8000dca: 60fb str r3, [r7, #12]
+ /* Find a free slot for this packet */
+ size_t packet_idx = 0;
+ 8000dcc: 2300 movs r3, #0
+ 8000dce: 617b str r3, [r7, #20]
+ do {
+ if (usart_tx_buf.packet_start[packet_idx] == -1)
+ 8000dd0: 4a3d ldr r2, [pc, #244] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
+ 8000dd2: 697b ldr r3, [r7, #20]
+ 8000dd4: 3302 adds r3, #2
+ 8000dd6: 009b lsls r3, r3, #2
+ 8000dd8: 18d3 adds r3, r2, r3
+ 8000dda: 3304 adds r3, #4
+ 8000ddc: 681b ldr r3, [r3, #0]
+ 8000dde: 3301 adds r3, #1
+ 8000de0: d00d beq.n 8000dfe <usart_send_packet_nonblocking+0x42>
+ goto success;
+ } while (++packet_idx <ARRAY_LEN(usart_tx_buf.packet_start));
+ 8000de2: 697b ldr r3, [r7, #20]
+ 8000de4: 3301 adds r3, #1
+ 8000de6: 617b str r3, [r7, #20]
+ 8000de8: 697b ldr r3, [r7, #20]
+ 8000dea: 2b04 cmp r3, #4
+ 8000dec: d9f0 bls.n 8000dd0 <usart_send_packet_nonblocking+0x14>
+
+ tx_overruns++;
+ 8000dee: 4b37 ldr r3, [pc, #220] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
+ 8000df0: 681b ldr r3, [r3, #0]
+ 8000df2: 1c5a adds r2, r3, #1
+ 8000df4: 4b35 ldr r3, [pc, #212] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
+ 8000df6: 601a str r2, [r3, #0]
+ return -EBUSY;
+ 8000df8: 2310 movs r3, #16
+ 8000dfa: 425b negs r3, r3
+ 8000dfc: e060 b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
+ goto success;
+ 8000dfe: 46c0 nop ; (mov r8, r8)
+
+success:
+ pkt->pid = packet_idx;
+ 8000e00: 697b ldr r3, [r7, #20]
+ 8000e02: b2da uxtb r2, r3
+ 8000e04: 687b ldr r3, [r7, #4]
+ 8000e06: 711a strb r2, [r3, #4]
+
+ /* make the value this wonky-ass CRC implementation produces match zlib etc. */
+ CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET;
+ 8000e08: 4b31 ldr r3, [pc, #196] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
+ 8000e0a: 22a1 movs r2, #161 ; 0xa1
+ 8000e0c: 609a str r2, [r3, #8]
+ for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
+ 8000e0e: 2304 movs r3, #4
+ 8000e10: 613b str r3, [r7, #16]
+ 8000e12: e008 b.n 8000e26 <usart_send_packet_nonblocking+0x6a>
+ CRC->DR = ((uint8_t *)pkt)[i];
+ 8000e14: 687a ldr r2, [r7, #4]
+ 8000e16: 693b ldr r3, [r7, #16]
+ 8000e18: 18d3 adds r3, r2, r3
+ 8000e1a: 781a ldrb r2, [r3, #0]
+ 8000e1c: 4b2c ldr r3, [pc, #176] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
+ 8000e1e: 601a str r2, [r3, #0]
+ for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
+ 8000e20: 693b ldr r3, [r7, #16]
+ 8000e22: 3301 adds r3, #1
+ 8000e24: 613b str r3, [r7, #16]
+ 8000e26: 693a ldr r2, [r7, #16]
+ 8000e28: 683b ldr r3, [r7, #0]
+ 8000e2a: 429a cmp r2, r3
+ 8000e2c: d3f2 bcc.n 8000e14 <usart_send_packet_nonblocking+0x58>
+
+ pkt->crc32 = ~CRC->DR;
+ 8000e2e: 4b28 ldr r3, [pc, #160] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
+ 8000e30: 681b ldr r3, [r3, #0]
+ 8000e32: 43da mvns r2, r3
+ 8000e34: 687b ldr r3, [r7, #4]
+ 8000e36: 21ff movs r1, #255 ; 0xff
+ 8000e38: 4011 ands r1, r2
+ 8000e3a: 000c movs r4, r1
+ 8000e3c: 7819 ldrb r1, [r3, #0]
+ 8000e3e: 2000 movs r0, #0
+ 8000e40: 4001 ands r1, r0
+ 8000e42: 1c08 adds r0, r1, #0
+ 8000e44: 1c21 adds r1, r4, #0
+ 8000e46: 4301 orrs r1, r0
+ 8000e48: 7019 strb r1, [r3, #0]
+ 8000e4a: 0a11 lsrs r1, r2, #8
+ 8000e4c: 20ff movs r0, #255 ; 0xff
+ 8000e4e: 4001 ands r1, r0
+ 8000e50: 000c movs r4, r1
+ 8000e52: 7859 ldrb r1, [r3, #1]
+ 8000e54: 2000 movs r0, #0
+ 8000e56: 4001 ands r1, r0
+ 8000e58: 1c08 adds r0, r1, #0
+ 8000e5a: 1c21 adds r1, r4, #0
+ 8000e5c: 4301 orrs r1, r0
+ 8000e5e: 7059 strb r1, [r3, #1]
+ 8000e60: 0c11 lsrs r1, r2, #16
+ 8000e62: 20ff movs r0, #255 ; 0xff
+ 8000e64: 4001 ands r1, r0
+ 8000e66: 000c movs r4, r1
+ 8000e68: 7899 ldrb r1, [r3, #2]
+ 8000e6a: 2000 movs r0, #0
+ 8000e6c: 4001 ands r1, r0
+ 8000e6e: 1c08 adds r0, r1, #0
+ 8000e70: 1c21 adds r1, r4, #0
+ 8000e72: 4301 orrs r1, r0
+ 8000e74: 7099 strb r1, [r3, #2]
+ 8000e76: 0e10 lsrs r0, r2, #24
+ 8000e78: 78da ldrb r2, [r3, #3]
+ 8000e7a: 2100 movs r1, #0
+ 8000e7c: 400a ands r2, r1
+ 8000e7e: 1c11 adds r1, r2, #0
+ 8000e80: 1c02 adds r2, r0, #0
+ 8000e82: 430a orrs r2, r1
+ 8000e84: 70da strb r2, [r3, #3]
+ int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
+ 8000e86: 683a ldr r2, [r7, #0]
+ 8000e88: 6879 ldr r1, [r7, #4]
+ 8000e8a: 4b12 ldr r3, [pc, #72] ; (8000ed4 <usart_send_packet_nonblocking+0x118>)
+ 8000e8c: 0018 movs r0, r3
+ 8000e8e: f000 f825 bl 8000edc <cobs_encode_usart>
+ 8000e92: 0003 movs r3, r0
+ 8000e94: 60bb str r3, [r7, #8]
+ if (rc)
+ 8000e96: 68bb ldr r3, [r7, #8]
+ 8000e98: 2b00 cmp r3, #0
+ 8000e9a: d001 beq.n 8000ea0 <usart_send_packet_nonblocking+0xe4>
+ return rc;
+ 8000e9c: 68bb ldr r3, [r7, #8]
+ 8000e9e: e00f b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
+
+ /* Checkpoint packet start index to prevent overwriting before ack */
+ usart_tx_buf.packet_start[packet_idx] = start;
+ 8000ea0: 4a09 ldr r2, [pc, #36] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
+ 8000ea2: 697b ldr r3, [r7, #20]
+ 8000ea4: 3302 adds r3, #2
+ 8000ea6: 009b lsls r3, r3, #2
+ 8000ea8: 18d3 adds r3, r2, r3
+ 8000eaa: 3304 adds r3, #4
+ 8000eac: 68fa ldr r2, [r7, #12]
+ 8000eae: 601a str r2, [r3, #0]
for (size_t i=0; i<351; i++)
- 8000b26: 2300 movs r3, #0
- 8000b28: 60fb str r3, [r7, #12]
- 8000b2a: e00b b.n 8000b44 <usart_send_packet_nonblocking+0x28>
usart_putc_nonblocking(x++);
- 8000b2c: 4b0e ldr r3, [pc, #56] ; (8000b68 <usart_send_packet_nonblocking+0x4c>)
- 8000b2e: 781b ldrb r3, [r3, #0]
- 8000b30: 1c5a adds r2, r3, #1
- 8000b32: b2d1 uxtb r1, r2
- 8000b34: 4a0c ldr r2, [pc, #48] ; (8000b68 <usart_send_packet_nonblocking+0x4c>)
- 8000b36: 7011 strb r1, [r2, #0]
- 8000b38: 0018 movs r0, r3
- 8000b3a: f7ff ffa1 bl 8000a80 <usart_putc_nonblocking>
- for (size_t i=0; i<351; i++)
- 8000b3e: 68fb ldr r3, [r7, #12]
- 8000b40: 3301 adds r3, #1
- 8000b42: 60fb str r3, [r7, #12]
- 8000b44: 68fa ldr r2, [r7, #12]
- 8000b46: 23af movs r3, #175 ; 0xaf
- 8000b48: 005b lsls r3, r3, #1
- 8000b4a: 429a cmp r2, r3
- 8000b4c: d9ee bls.n 8000b2c <usart_send_packet_nonblocking+0x10>
+ */
/* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
- 8000b4e: 4b07 ldr r3, [pc, #28] ; (8000b6c <usart_send_packet_nonblocking+0x50>)
- 8000b50: 681b ldr r3, [r3, #0]
- 8000b52: 2201 movs r2, #1
- 8000b54: 4013 ands r3, r2
- 8000b56: d101 bne.n 8000b5c <usart_send_packet_nonblocking+0x40>
+ 8000eb0: 4b09 ldr r3, [pc, #36] ; (8000ed8 <usart_send_packet_nonblocking+0x11c>)
+ 8000eb2: 681b ldr r3, [r3, #0]
+ 8000eb4: 2201 movs r2, #1
+ 8000eb6: 4013 ands r3, r2
+ 8000eb8: d101 bne.n 8000ebe <usart_send_packet_nonblocking+0x102>
usart_schedule_dma();
- 8000b58: f7ff ff14 bl 8000984 <usart_schedule_dma>
+ 8000eba: f7ff fe49 bl 8000b50 <usart_schedule_dma>
return 0;
- 8000b5c: 2300 movs r3, #0
+ 8000ebe: 2300 movs r3, #0
}
- 8000b5e: 0018 movs r0, r3
- 8000b60: 46bd mov sp, r7
- 8000b62: b004 add sp, #16
- 8000b64: bd80 pop {r7, pc}
- 8000b66: 46c0 nop ; (mov r8, r8)
- 8000b68: 200000a4 .word 0x200000a4
- 8000b6c: 4002001c .word 0x4002001c
-
-08000b70 <cobs_encode>:
- @ ensures \result == -1;
- @
- @ complete behaviors;
- @ disjoint behaviors;
- @*/
-ssize_t cobs_encode(char *dst, size_t dstlen, char *src, size_t srclen) {
- 8000b70: b580 push {r7, lr}
- 8000b72: b088 sub sp, #32
- 8000b74: af00 add r7, sp, #0
- 8000b76: 60f8 str r0, [r7, #12]
- 8000b78: 60b9 str r1, [r7, #8]
- 8000b7a: 607a str r2, [r7, #4]
- 8000b7c: 603b str r3, [r7, #0]
- if (dstlen > 65535 || srclen > 254)
- 8000b7e: 68ba ldr r2, [r7, #8]
- 8000b80: 2380 movs r3, #128 ; 0x80
- 8000b82: 025b lsls r3, r3, #9
- 8000b84: 429a cmp r2, r3
- 8000b86: d202 bcs.n 8000b8e <cobs_encode+0x1e>
- 8000b88: 683b ldr r3, [r7, #0]
- 8000b8a: 2bfe cmp r3, #254 ; 0xfe
- 8000b8c: d902 bls.n 8000b94 <cobs_encode+0x24>
- return -1;
- 8000b8e: 2301 movs r3, #1
- 8000b90: 425b negs r3, r3
- 8000b92: e04c b.n 8000c2e <cobs_encode+0xbe>
- //@ assert 0 <= dstlen <= 65535 && 0 <= srclen <= 254;
-
- if (dstlen < srclen+2)
- 8000b94: 683b ldr r3, [r7, #0]
- 8000b96: 3302 adds r3, #2
- 8000b98: 68ba ldr r2, [r7, #8]
- 8000b9a: 429a cmp r2, r3
- 8000b9c: d202 bcs.n 8000ba4 <cobs_encode+0x34>
- return -1;
- 8000b9e: 2301 movs r3, #1
- 8000ba0: 425b negs r3, r3
- 8000ba2: e044 b.n 8000c2e <cobs_encode+0xbe>
- //@ assert 0 <= srclen < srclen+2 <= dstlen;
-
- size_t p = 0;
- 8000ba4: 2300 movs r3, #0
- 8000ba6: 61fb str r3, [r7, #28]
- @ loop invariant \forall integer i; 0 <= i < p ==> dst[i] != 0;
- @ loop invariant \forall integer i; 0 < i < p ==> (src[i-1] != 0 ==> dst[i] == src[i-1]);
- @ loop assigns p, dst[0..srclen+1];
- @ loop variant srclen-p+1;
- @*/
- while (p <= srclen) {
- 8000ba8: e036 b.n 8000c18 <cobs_encode+0xa8>
-
- char val;
- if (p != 0 && src[p-1] != 0) {
- 8000baa: 69fb ldr r3, [r7, #28]
- 8000bac: 2b00 cmp r3, #0
- 8000bae: d00f beq.n 8000bd0 <cobs_encode+0x60>
- 8000bb0: 69fb ldr r3, [r7, #28]
- 8000bb2: 3b01 subs r3, #1
- 8000bb4: 687a ldr r2, [r7, #4]
- 8000bb6: 18d3 adds r3, r2, r3
- 8000bb8: 781b ldrb r3, [r3, #0]
- 8000bba: 2b00 cmp r3, #0
- 8000bbc: d008 beq.n 8000bd0 <cobs_encode+0x60>
- val = src[p-1];
- 8000bbe: 69fb ldr r3, [r7, #28]
- 8000bc0: 3b01 subs r3, #1
- 8000bc2: 687a ldr r2, [r7, #4]
- 8000bc4: 18d2 adds r2, r2, r3
- 8000bc6: 231b movs r3, #27
- 8000bc8: 18fb adds r3, r7, r3
- 8000bca: 7812 ldrb r2, [r2, #0]
- 8000bcc: 701a strb r2, [r3, #0]
- 8000bce: e019 b.n 8000c04 <cobs_encode+0x94>
-
- } else {
- size_t q = p;
- 8000bd0: 69fb ldr r3, [r7, #28]
- 8000bd2: 617b str r3, [r7, #20]
- /*@ loop invariant 0 <= p <= q <= srclen;
- @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
- @ loop assigns q;
- @ loop variant srclen-q;
- @*/
- while (q < srclen && src[q] != 0)
- 8000bd4: e002 b.n 8000bdc <cobs_encode+0x6c>
- q++;
- 8000bd6: 697b ldr r3, [r7, #20]
- 8000bd8: 3301 adds r3, #1
- 8000bda: 617b str r3, [r7, #20]
- while (q < srclen && src[q] != 0)
- 8000bdc: 697a ldr r2, [r7, #20]
- 8000bde: 683b ldr r3, [r7, #0]
- 8000be0: 429a cmp r2, r3
- 8000be2: d205 bcs.n 8000bf0 <cobs_encode+0x80>
- 8000be4: 687a ldr r2, [r7, #4]
- 8000be6: 697b ldr r3, [r7, #20]
- 8000be8: 18d3 adds r3, r2, r3
- 8000bea: 781b ldrb r3, [r3, #0]
- 8000bec: 2b00 cmp r3, #0
- 8000bee: d1f2 bne.n 8000bd6 <cobs_encode+0x66>
- //@ assert q == srclen || src[q] == 0;
- //@ assert q <= srclen <= 254;
- val = (char)q-p+1;
- 8000bf0: 697b ldr r3, [r7, #20]
- 8000bf2: b2da uxtb r2, r3
- 8000bf4: 69fb ldr r3, [r7, #28]
- 8000bf6: b2db uxtb r3, r3
- 8000bf8: 1ad3 subs r3, r2, r3
- 8000bfa: b2da uxtb r2, r3
- 8000bfc: 231b movs r3, #27
- 8000bfe: 18fb adds r3, r7, r3
- 8000c00: 3201 adds r2, #1
- 8000c02: 701a strb r2, [r3, #0]
- //@ assert val != 0;
- }
-
- dst[p] = val;
- 8000c04: 68fa ldr r2, [r7, #12]
- 8000c06: 69fb ldr r3, [r7, #28]
- 8000c08: 18d3 adds r3, r2, r3
- 8000c0a: 221b movs r2, #27
- 8000c0c: 18ba adds r2, r7, r2
- 8000c0e: 7812 ldrb r2, [r2, #0]
- 8000c10: 701a strb r2, [r3, #0]
- p++;
- 8000c12: 69fb ldr r3, [r7, #28]
- 8000c14: 3301 adds r3, #1
- 8000c16: 61fb str r3, [r7, #28]
- while (p <= srclen) {
- 8000c18: 69fa ldr r2, [r7, #28]
- 8000c1a: 683b ldr r3, [r7, #0]
- 8000c1c: 429a cmp r2, r3
- 8000c1e: d9c4 bls.n 8000baa <cobs_encode+0x3a>
- }
+ 8000ec0: 0018 movs r0, r3
+ 8000ec2: 46bd mov sp, r7
+ 8000ec4: b007 add sp, #28
+ 8000ec6: bd90 pop {r4, r7, pc}
+ 8000ec8: 20000198 .word 0x20000198
+ 8000ecc: 20000138 .word 0x20000138
+ 8000ed0: 40023000 .word 0x40023000
+ 8000ed4: 08000ca9 .word 0x08000ca9
+ 8000ed8: 4002001c .word 0x4002001c
- dst[p] = 0;
- 8000c20: 68fa ldr r2, [r7, #12]
- 8000c22: 69fb ldr r3, [r7, #28]
- 8000c24: 18d3 adds r3, r2, r3
- 8000c26: 2200 movs r2, #0
- 8000c28: 701a strb r2, [r3, #0]
- //@ assert p == srclen+1;
-
- return srclen+2;
- 8000c2a: 683b ldr r3, [r7, #0]
- 8000c2c: 3302 adds r3, #2
-}
- 8000c2e: 0018 movs r0, r3
- 8000c30: 46bd mov sp, r7
- 8000c32: b008 add sp, #32
- 8000c34: bd80 pop {r7, pc}
+08000edc <cobs_encode_usart>:
-08000c36 <cobs_encode_usart>:
+#include "serial.h"
+#include "cobs.h"
int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) {
- 8000c36: b580 push {r7, lr}
- 8000c38: b08a sub sp, #40 ; 0x28
- 8000c3a: af00 add r7, sp, #0
- 8000c3c: 60f8 str r0, [r7, #12]
- 8000c3e: 60b9 str r1, [r7, #8]
- 8000c40: 607a str r2, [r7, #4]
+ 8000edc: b580 push {r7, lr}
+ 8000ede: b08a sub sp, #40 ; 0x28
+ 8000ee0: af00 add r7, sp, #0
+ 8000ee2: 60f8 str r0, [r7, #12]
+ 8000ee4: 60b9 str r1, [r7, #8]
+ 8000ee6: 607a str r2, [r7, #4]
if (srclen > 254)
- 8000c42: 687b ldr r3, [r7, #4]
- 8000c44: 2bfe cmp r3, #254 ; 0xfe
- 8000c46: d902 bls.n 8000c4e <cobs_encode_usart+0x18>
+ 8000ee8: 687b ldr r3, [r7, #4]
+ 8000eea: 2bfe cmp r3, #254 ; 0xfe
+ 8000eec: d902 bls.n 8000ef4 <cobs_encode_usart+0x18>
return -1;
- 8000c48: 2301 movs r3, #1
- 8000c4a: 425b negs r3, r3
- 8000c4c: e04e b.n 8000cec <cobs_encode_usart+0xb6>
- //@ assert 0 <= srclen <= 254;
+ 8000eee: 2301 movs r3, #1
+ 8000ef0: 425b negs r3, r3
+ 8000ef2: e04e b.n 8000f92 <cobs_encode_usart+0xb6>
size_t p = 0;
- 8000c4e: 2300 movs r3, #0
- 8000c50: 627b str r3, [r7, #36] ; 0x24
- /*@ loop invariant 0 <= p <= srclen+1;
- @ loop assigns p;
- @ loop variant srclen-p+1;
- @*/
+ 8000ef4: 2300 movs r3, #0
+ 8000ef6: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
- 8000c52: e03c b.n 8000cce <cobs_encode_usart+0x98>
+ 8000ef8: e03c b.n 8000f74 <cobs_encode_usart+0x98>
char val;
if (p != 0 && src[p-1] != 0) {
- 8000c54: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000c56: 2b00 cmp r3, #0
- 8000c58: d00f beq.n 8000c7a <cobs_encode_usart+0x44>
- 8000c5a: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000c5c: 3b01 subs r3, #1
- 8000c5e: 68ba ldr r2, [r7, #8]
- 8000c60: 18d3 adds r3, r2, r3
- 8000c62: 781b ldrb r3, [r3, #0]
- 8000c64: 2b00 cmp r3, #0
- 8000c66: d008 beq.n 8000c7a <cobs_encode_usart+0x44>
+ 8000efa: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000efc: 2b00 cmp r3, #0
+ 8000efe: d00f beq.n 8000f20 <cobs_encode_usart+0x44>
+ 8000f00: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f02: 3b01 subs r3, #1
+ 8000f04: 68ba ldr r2, [r7, #8]
+ 8000f06: 18d3 adds r3, r2, r3
+ 8000f08: 781b ldrb r3, [r3, #0]
+ 8000f0a: 2b00 cmp r3, #0
+ 8000f0c: d008 beq.n 8000f20 <cobs_encode_usart+0x44>
val = src[p-1];
- 8000c68: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000c6a: 3b01 subs r3, #1
- 8000c6c: 68ba ldr r2, [r7, #8]
- 8000c6e: 18d2 adds r2, r2, r3
- 8000c70: 2323 movs r3, #35 ; 0x23
- 8000c72: 18fb adds r3, r7, r3
- 8000c74: 7812 ldrb r2, [r2, #0]
- 8000c76: 701a strb r2, [r3, #0]
- 8000c78: e019 b.n 8000cae <cobs_encode_usart+0x78>
+ 8000f0e: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f10: 3b01 subs r3, #1
+ 8000f12: 68ba ldr r2, [r7, #8]
+ 8000f14: 18d2 adds r2, r2, r3
+ 8000f16: 2323 movs r3, #35 ; 0x23
+ 8000f18: 18fb adds r3, r7, r3
+ 8000f1a: 7812 ldrb r2, [r2, #0]
+ 8000f1c: 701a strb r2, [r3, #0]
+ 8000f1e: e019 b.n 8000f54 <cobs_encode_usart+0x78>
} else {
size_t q = p;
- 8000c7a: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000c7c: 61fb str r3, [r7, #28]
- /*@ loop invariant 0 <= p <= q <= srclen;
- @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
- @ loop assigns q;
- @ loop variant srclen-q;
- @*/
+ 8000f20: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f22: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
- 8000c7e: e002 b.n 8000c86 <cobs_encode_usart+0x50>
+ 8000f24: e002 b.n 8000f2c <cobs_encode_usart+0x50>
q++;
- 8000c80: 69fb ldr r3, [r7, #28]
- 8000c82: 3301 adds r3, #1
- 8000c84: 61fb str r3, [r7, #28]
+ 8000f26: 69fb ldr r3, [r7, #28]
+ 8000f28: 3301 adds r3, #1
+ 8000f2a: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
- 8000c86: 69fa ldr r2, [r7, #28]
- 8000c88: 687b ldr r3, [r7, #4]
- 8000c8a: 429a cmp r2, r3
- 8000c8c: d205 bcs.n 8000c9a <cobs_encode_usart+0x64>
- 8000c8e: 68ba ldr r2, [r7, #8]
- 8000c90: 69fb ldr r3, [r7, #28]
- 8000c92: 18d3 adds r3, r2, r3
- 8000c94: 781b ldrb r3, [r3, #0]
- 8000c96: 2b00 cmp r3, #0
- 8000c98: d1f2 bne.n 8000c80 <cobs_encode_usart+0x4a>
- //@ assert q == srclen || src[q] == 0;
- //@ assert q <= srclen <= 254;
+ 8000f2c: 69fa ldr r2, [r7, #28]
+ 8000f2e: 687b ldr r3, [r7, #4]
+ 8000f30: 429a cmp r2, r3
+ 8000f32: d205 bcs.n 8000f40 <cobs_encode_usart+0x64>
+ 8000f34: 68ba ldr r2, [r7, #8]
+ 8000f36: 69fb ldr r3, [r7, #28]
+ 8000f38: 18d3 adds r3, r2, r3
+ 8000f3a: 781b ldrb r3, [r3, #0]
+ 8000f3c: 2b00 cmp r3, #0
+ 8000f3e: d1f2 bne.n 8000f26 <cobs_encode_usart+0x4a>
val = (char)q-p+1;
- 8000c9a: 69fb ldr r3, [r7, #28]
- 8000c9c: b2da uxtb r2, r3
- 8000c9e: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000ca0: b2db uxtb r3, r3
- 8000ca2: 1ad3 subs r3, r2, r3
- 8000ca4: b2da uxtb r2, r3
- 8000ca6: 2323 movs r3, #35 ; 0x23
- 8000ca8: 18fb adds r3, r7, r3
- 8000caa: 3201 adds r2, #1
- 8000cac: 701a strb r2, [r3, #0]
- //@ assert val != 0;
+ 8000f40: 69fb ldr r3, [r7, #28]
+ 8000f42: b2da uxtb r2, r3
+ 8000f44: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f46: b2db uxtb r3, r3
+ 8000f48: 1ad3 subs r3, r2, r3
+ 8000f4a: b2da uxtb r2, r3
+ 8000f4c: 2323 movs r3, #35 ; 0x23
+ 8000f4e: 18fb adds r3, r7, r3
+ 8000f50: 3201 adds r2, #1
+ 8000f52: 701a strb r2, [r3, #0]
}
int rv = output(val);
- 8000cae: 2323 movs r3, #35 ; 0x23
- 8000cb0: 18fb adds r3, r7, r3
- 8000cb2: 781a ldrb r2, [r3, #0]
- 8000cb4: 68fb ldr r3, [r7, #12]
- 8000cb6: 0010 movs r0, r2
- 8000cb8: 4798 blx r3
- 8000cba: 0003 movs r3, r0
- 8000cbc: 617b str r3, [r7, #20]
+ 8000f54: 2323 movs r3, #35 ; 0x23
+ 8000f56: 18fb adds r3, r7, r3
+ 8000f58: 781a ldrb r2, [r3, #0]
+ 8000f5a: 68fb ldr r3, [r7, #12]
+ 8000f5c: 0010 movs r0, r2
+ 8000f5e: 4798 blx r3
+ 8000f60: 0003 movs r3, r0
+ 8000f62: 617b str r3, [r7, #20]
if (rv)
- 8000cbe: 697b ldr r3, [r7, #20]
- 8000cc0: 2b00 cmp r3, #0
- 8000cc2: d001 beq.n 8000cc8 <cobs_encode_usart+0x92>
+ 8000f64: 697b ldr r3, [r7, #20]
+ 8000f66: 2b00 cmp r3, #0
+ 8000f68: d001 beq.n 8000f6e <cobs_encode_usart+0x92>
return rv;
- 8000cc4: 697b ldr r3, [r7, #20]
- 8000cc6: e011 b.n 8000cec <cobs_encode_usart+0xb6>
+ 8000f6a: 697b ldr r3, [r7, #20]
+ 8000f6c: e011 b.n 8000f92 <cobs_encode_usart+0xb6>
p++;
- 8000cc8: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000cca: 3301 adds r3, #1
- 8000ccc: 627b str r3, [r7, #36] ; 0x24
+ 8000f6e: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f70: 3301 adds r3, #1
+ 8000f72: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
- 8000cce: 6a7a ldr r2, [r7, #36] ; 0x24
- 8000cd0: 687b ldr r3, [r7, #4]
- 8000cd2: 429a cmp r2, r3
- 8000cd4: d9be bls.n 8000c54 <cobs_encode_usart+0x1e>
+ 8000f74: 6a7a ldr r2, [r7, #36] ; 0x24
+ 8000f76: 687b ldr r3, [r7, #4]
+ 8000f78: 429a cmp r2, r3
+ 8000f7a: d9be bls.n 8000efa <cobs_encode_usart+0x1e>
}
int rv = output(0);
- 8000cd6: 68fb ldr r3, [r7, #12]
- 8000cd8: 2000 movs r0, #0
- 8000cda: 4798 blx r3
- 8000cdc: 0003 movs r3, r0
- 8000cde: 61bb str r3, [r7, #24]
+ 8000f7c: 68fb ldr r3, [r7, #12]
+ 8000f7e: 2000 movs r0, #0
+ 8000f80: 4798 blx r3
+ 8000f82: 0003 movs r3, r0
+ 8000f84: 61bb str r3, [r7, #24]
if (rv)
- 8000ce0: 69bb ldr r3, [r7, #24]
- 8000ce2: 2b00 cmp r3, #0
- 8000ce4: d001 beq.n 8000cea <cobs_encode_usart+0xb4>
+ 8000f86: 69bb ldr r3, [r7, #24]
+ 8000f88: 2b00 cmp r3, #0
+ 8000f8a: d001 beq.n 8000f90 <cobs_encode_usart+0xb4>
return rv;
- 8000ce6: 69bb ldr r3, [r7, #24]
- 8000ce8: e000 b.n 8000cec <cobs_encode_usart+0xb6>
- //@ assert p == srclen+1;
+ 8000f8c: 69bb ldr r3, [r7, #24]
+ 8000f8e: e000 b.n 8000f92 <cobs_encode_usart+0xb6>
return 0;
- 8000cea: 2300 movs r3, #0
+ 8000f90: 2300 movs r3, #0
}
- 8000cec: 0018 movs r0, r3
- 8000cee: 46bd mov sp, r7
- 8000cf0: b00a add sp, #40 ; 0x28
- 8000cf2: bd80 pop {r7, pc}
+ 8000f92: 0018 movs r0, r3
+ 8000f94: 46bd mov sp, r7
+ 8000f96: b00a add sp, #40 ; 0x28
+ 8000f98: bd80 pop {r7, pc}
-08000cf4 <cobs_decode>:
+08000f9a <cobs_decode>:
@ ensures \result == -1;
@
@ complete behaviors;
@ disjoint behaviors;
@*/
ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) {
- 8000cf4: b580 push {r7, lr}
- 8000cf6: b088 sub sp, #32
- 8000cf8: af00 add r7, sp, #0
- 8000cfa: 60f8 str r0, [r7, #12]
- 8000cfc: 60b9 str r1, [r7, #8]
- 8000cfe: 607a str r2, [r7, #4]
- 8000d00: 603b str r3, [r7, #0]
+ 8000f9a: b580 push {r7, lr}
+ 8000f9c: b088 sub sp, #32
+ 8000f9e: af00 add r7, sp, #0
+ 8000fa0: 60f8 str r0, [r7, #12]
+ 8000fa2: 60b9 str r1, [r7, #8]
+ 8000fa4: 607a str r2, [r7, #4]
+ 8000fa6: 603b str r3, [r7, #0]
if (dstlen > 65535 || srclen > 65535)
- 8000d02: 68ba ldr r2, [r7, #8]
- 8000d04: 2380 movs r3, #128 ; 0x80
- 8000d06: 025b lsls r3, r3, #9
- 8000d08: 429a cmp r2, r3
- 8000d0a: d204 bcs.n 8000d16 <cobs_decode+0x22>
- 8000d0c: 683a ldr r2, [r7, #0]
- 8000d0e: 2380 movs r3, #128 ; 0x80
- 8000d10: 025b lsls r3, r3, #9
- 8000d12: 429a cmp r2, r3
- 8000d14: d302 bcc.n 8000d1c <cobs_decode+0x28>
+ 8000fa8: 68ba ldr r2, [r7, #8]
+ 8000faa: 2380 movs r3, #128 ; 0x80
+ 8000fac: 025b lsls r3, r3, #9
+ 8000fae: 429a cmp r2, r3
+ 8000fb0: d204 bcs.n 8000fbc <cobs_decode+0x22>
+ 8000fb2: 683a ldr r2, [r7, #0]
+ 8000fb4: 2380 movs r3, #128 ; 0x80
+ 8000fb6: 025b lsls r3, r3, #9
+ 8000fb8: 429a cmp r2, r3
+ 8000fba: d302 bcc.n 8000fc2 <cobs_decode+0x28>
return -1;
- 8000d16: 2301 movs r3, #1
- 8000d18: 425b negs r3, r3
- 8000d1a: e052 b.n 8000dc2 <cobs_decode+0xce>
+ 8000fbc: 2301 movs r3, #1
+ 8000fbe: 425b negs r3, r3
+ 8000fc0: e052 b.n 8001068 <cobs_decode+0xce>
if (srclen < 1)
- 8000d1c: 683b ldr r3, [r7, #0]
- 8000d1e: 2b00 cmp r3, #0
- 8000d20: d102 bne.n 8000d28 <cobs_decode+0x34>
+ 8000fc2: 683b ldr r3, [r7, #0]
+ 8000fc4: 2b00 cmp r3, #0
+ 8000fc6: d102 bne.n 8000fce <cobs_decode+0x34>
return -1;
- 8000d22: 2301 movs r3, #1
- 8000d24: 425b negs r3, r3
- 8000d26: e04c b.n 8000dc2 <cobs_decode+0xce>
+ 8000fc8: 2301 movs r3, #1
+ 8000fca: 425b negs r3, r3
+ 8000fcc: e04c b.n 8001068 <cobs_decode+0xce>
if (dstlen < srclen)
- 8000d28: 68ba ldr r2, [r7, #8]
- 8000d2a: 683b ldr r3, [r7, #0]
- 8000d2c: 429a cmp r2, r3
- 8000d2e: d202 bcs.n 8000d36 <cobs_decode+0x42>
+ 8000fce: 68ba ldr r2, [r7, #8]
+ 8000fd0: 683b ldr r3, [r7, #0]
+ 8000fd2: 429a cmp r2, r3
+ 8000fd4: d202 bcs.n 8000fdc <cobs_decode+0x42>
return -1;
- 8000d30: 2301 movs r3, #1
- 8000d32: 425b negs r3, r3
- 8000d34: e045 b.n 8000dc2 <cobs_decode+0xce>
+ 8000fd6: 2301 movs r3, #1
+ 8000fd8: 425b negs r3, r3
+ 8000fda: e045 b.n 8001068 <cobs_decode+0xce>
size_t p = 1;
- 8000d36: 2301 movs r3, #1
- 8000d38: 61fb str r3, [r7, #28]
+ 8000fdc: 2301 movs r3, #1
+ 8000fde: 61fb str r3, [r7, #28]
size_t c = (unsigned char)src[0];
- 8000d3a: 687b ldr r3, [r7, #4]
- 8000d3c: 781b ldrb r3, [r3, #0]
- 8000d3e: 61bb str r3, [r7, #24]
+ 8000fe0: 687b ldr r3, [r7, #4]
+ 8000fe2: 781b ldrb r3, [r3, #0]
+ 8000fe4: 61bb str r3, [r7, #24]
//@ assert 0 <= c < 256;
//@ assert 0 <= c;
//@ assert c < 256;
if (c == 0)
- 8000d40: 69bb ldr r3, [r7, #24]
- 8000d42: 2b00 cmp r3, #0
- 8000d44: d124 bne.n 8000d90 <cobs_decode+0x9c>
+ 8000fe6: 69bb ldr r3, [r7, #24]
+ 8000fe8: 2b00 cmp r3, #0
+ 8000fea: d124 bne.n 8001036 <cobs_decode+0x9c>
return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8000d46: 2302 movs r3, #2
- 8000d48: 425b negs r3, r3
- 8000d4a: e03a b.n 8000dc2 <cobs_decode+0xce>
+ 8000fec: 2302 movs r3, #2
+ 8000fee: 425b negs r3, r3
+ 8000ff0: e03a b.n 8001068 <cobs_decode+0xce>
@ loop assigns dst[0..dstlen-1], p, c;
@ loop variant srclen-p;
@*/
while (p < srclen && src[p]) {
char val;
c--;
- 8000d4c: 69bb ldr r3, [r7, #24]
- 8000d4e: 3b01 subs r3, #1
- 8000d50: 61bb str r3, [r7, #24]
+ 8000ff2: 69bb ldr r3, [r7, #24]
+ 8000ff4: 3b01 subs r3, #1
+ 8000ff6: 61bb str r3, [r7, #24]
//@ assert src[p] != 0;
if (c == 0) {
- 8000d52: 69bb ldr r3, [r7, #24]
- 8000d54: 2b00 cmp r3, #0
- 8000d56: d109 bne.n 8000d6c <cobs_decode+0x78>
+ 8000ff8: 69bb ldr r3, [r7, #24]
+ 8000ffa: 2b00 cmp r3, #0
+ 8000ffc: d109 bne.n 8001012 <cobs_decode+0x78>
c = (unsigned char)src[p];
- 8000d58: 687a ldr r2, [r7, #4]
- 8000d5a: 69fb ldr r3, [r7, #28]
- 8000d5c: 18d3 adds r3, r2, r3
- 8000d5e: 781b ldrb r3, [r3, #0]
- 8000d60: 61bb str r3, [r7, #24]
+ 8000ffe: 687a ldr r2, [r7, #4]
+ 8001000: 69fb ldr r3, [r7, #28]
+ 8001002: 18d3 adds r3, r2, r3
+ 8001004: 781b ldrb r3, [r3, #0]
+ 8001006: 61bb str r3, [r7, #24]
val = 0;
- 8000d62: 2317 movs r3, #23
- 8000d64: 18fb adds r3, r7, r3
- 8000d66: 2200 movs r2, #0
- 8000d68: 701a strb r2, [r3, #0]
- 8000d6a: e006 b.n 8000d7a <cobs_decode+0x86>
+ 8001008: 2317 movs r3, #23
+ 800100a: 18fb adds r3, r7, r3
+ 800100c: 2200 movs r2, #0
+ 800100e: 701a strb r2, [r3, #0]
+ 8001010: e006 b.n 8001020 <cobs_decode+0x86>
} else {
val = src[p];
- 8000d6c: 687a ldr r2, [r7, #4]
- 8000d6e: 69fb ldr r3, [r7, #28]
- 8000d70: 18d2 adds r2, r2, r3
- 8000d72: 2317 movs r3, #23
- 8000d74: 18fb adds r3, r7, r3
- 8000d76: 7812 ldrb r2, [r2, #0]
- 8000d78: 701a strb r2, [r3, #0]
+ 8001012: 687a ldr r2, [r7, #4]
+ 8001014: 69fb ldr r3, [r7, #28]
+ 8001016: 18d2 adds r2, r2, r3
+ 8001018: 2317 movs r3, #23
+ 800101a: 18fb adds r3, r7, r3
+ 800101c: 7812 ldrb r2, [r2, #0]
+ 800101e: 701a strb r2, [r3, #0]
}
//@ assert 0 <= p-1 <= dstlen-1;
dst[p-1] = val;
- 8000d7a: 69fb ldr r3, [r7, #28]
- 8000d7c: 3b01 subs r3, #1
- 8000d7e: 68fa ldr r2, [r7, #12]
- 8000d80: 18d3 adds r3, r2, r3
- 8000d82: 2217 movs r2, #23
- 8000d84: 18ba adds r2, r7, r2
- 8000d86: 7812 ldrb r2, [r2, #0]
- 8000d88: 701a strb r2, [r3, #0]
+ 8001020: 69fb ldr r3, [r7, #28]
+ 8001022: 3b01 subs r3, #1
+ 8001024: 68fa ldr r2, [r7, #12]
+ 8001026: 18d3 adds r3, r2, r3
+ 8001028: 2217 movs r2, #23
+ 800102a: 18ba adds r2, r7, r2
+ 800102c: 7812 ldrb r2, [r2, #0]
+ 800102e: 701a strb r2, [r3, #0]
p++;
- 8000d8a: 69fb ldr r3, [r7, #28]
- 8000d8c: 3301 adds r3, #1
- 8000d8e: 61fb str r3, [r7, #28]
+ 8001030: 69fb ldr r3, [r7, #28]
+ 8001032: 3301 adds r3, #1
+ 8001034: 61fb str r3, [r7, #28]
while (p < srclen && src[p]) {
- 8000d90: 69fa ldr r2, [r7, #28]
- 8000d92: 683b ldr r3, [r7, #0]
- 8000d94: 429a cmp r2, r3
- 8000d96: d205 bcs.n 8000da4 <cobs_decode+0xb0>
- 8000d98: 687a ldr r2, [r7, #4]
- 8000d9a: 69fb ldr r3, [r7, #28]
- 8000d9c: 18d3 adds r3, r2, r3
- 8000d9e: 781b ldrb r3, [r3, #0]
- 8000da0: 2b00 cmp r3, #0
- 8000da2: d1d3 bne.n 8000d4c <cobs_decode+0x58>
+ 8001036: 69fa ldr r2, [r7, #28]
+ 8001038: 683b ldr r3, [r7, #0]
+ 800103a: 429a cmp r2, r3
+ 800103c: d205 bcs.n 800104a <cobs_decode+0xb0>
+ 800103e: 687a ldr r2, [r7, #4]
+ 8001040: 69fb ldr r3, [r7, #28]
+ 8001042: 18d3 adds r3, r2, r3
+ 8001044: 781b ldrb r3, [r3, #0]
+ 8001046: 2b00 cmp r3, #0
+ 8001048: d1d3 bne.n 8000ff2 <cobs_decode+0x58>
}
if (p == srclen)
- 8000da4: 69fa ldr r2, [r7, #28]
- 8000da6: 683b ldr r3, [r7, #0]
- 8000da8: 429a cmp r2, r3
- 8000daa: d102 bne.n 8000db2 <cobs_decode+0xbe>
+ 800104a: 69fa ldr r2, [r7, #28]
+ 800104c: 683b ldr r3, [r7, #0]
+ 800104e: 429a cmp r2, r3
+ 8001050: d102 bne.n 8001058 <cobs_decode+0xbe>
return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */
- 8000dac: 2302 movs r3, #2
- 8000dae: 425b negs r3, r3
- 8000db0: e007 b.n 8000dc2 <cobs_decode+0xce>
+ 8001052: 2302 movs r3, #2
+ 8001054: 425b negs r3, r3
+ 8001056: e007 b.n 8001068 <cobs_decode+0xce>
if (c != 1)
- 8000db2: 69bb ldr r3, [r7, #24]
- 8000db4: 2b01 cmp r3, #1
- 8000db6: d002 beq.n 8000dbe <cobs_decode+0xca>
+ 8001058: 69bb ldr r3, [r7, #24]
+ 800105a: 2b01 cmp r3, #1
+ 800105c: d002 beq.n 8001064 <cobs_decode+0xca>
return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 8000db8: 2303 movs r3, #3
- 8000dba: 425b negs r3, r3
- 8000dbc: e001 b.n 8000dc2 <cobs_decode+0xce>
+ 800105e: 2303 movs r3, #3
+ 8001060: 425b negs r3, r3
+ 8001062: e001 b.n 8001068 <cobs_decode+0xce>
//@ assert 0 < p <= srclen <= 65535;
//@ assert src[p] == 0;
//@ assert \forall integer i; 1 <= i < p ==> src[i] != 0;
return p-1;
- 8000dbe: 69fb ldr r3, [r7, #28]
- 8000dc0: 3b01 subs r3, #1
+ 8001064: 69fb ldr r3, [r7, #28]
+ 8001066: 3b01 subs r3, #1
}
- 8000dc2: 0018 movs r0, r3
- 8000dc4: 46bd mov sp, r7
- 8000dc6: b008 add sp, #32
- 8000dc8: bd80 pop {r7, pc}
+ 8001068: 0018 movs r0, r3
+ 800106a: 46bd mov sp, r7
+ 800106c: b008 add sp, #32
+ 800106e: bd80 pop {r7, pc}
-08000dca <cobs_decode_incremental_initialize>:
+08001070 <cobs_decode_incremental_initialize>:
void cobs_decode_incremental_initialize(struct cobs_decode_state *state) {
- 8000dca: b580 push {r7, lr}
- 8000dcc: b082 sub sp, #8
- 8000dce: af00 add r7, sp, #0
- 8000dd0: 6078 str r0, [r7, #4]
+ 8001070: b580 push {r7, lr}
+ 8001072: b082 sub sp, #8
+ 8001074: af00 add r7, sp, #0
+ 8001076: 6078 str r0, [r7, #4]
state->p = 0;
- 8000dd2: 687b ldr r3, [r7, #4]
- 8000dd4: 2200 movs r2, #0
- 8000dd6: 601a str r2, [r3, #0]
+ 8001078: 687b ldr r3, [r7, #4]
+ 800107a: 2200 movs r2, #0
+ 800107c: 601a str r2, [r3, #0]
state->c = 0;
- 8000dd8: 687b ldr r3, [r7, #4]
- 8000dda: 2200 movs r2, #0
- 8000ddc: 605a str r2, [r3, #4]
+ 800107e: 687b ldr r3, [r7, #4]
+ 8001080: 2200 movs r2, #0
+ 8001082: 605a str r2, [r3, #4]
}
- 8000dde: 46c0 nop ; (mov r8, r8)
- 8000de0: 46bd mov sp, r7
- 8000de2: b002 add sp, #8
- 8000de4: bd80 pop {r7, pc}
+ 8001084: 46c0 nop ; (mov r8, r8)
+ 8001086: 46bd mov sp, r7
+ 8001088: b002 add sp, #8
+ 800108a: bd80 pop {r7, pc}
-08000de6 <cobs_decode_incremental>:
+0800108c <cobs_decode_incremental>:
int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) {
- 8000de6: b580 push {r7, lr}
- 8000de8: b088 sub sp, #32
- 8000dea: af00 add r7, sp, #0
- 8000dec: 60f8 str r0, [r7, #12]
- 8000dee: 60b9 str r1, [r7, #8]
- 8000df0: 607a str r2, [r7, #4]
- 8000df2: 001a movs r2, r3
- 8000df4: 1cfb adds r3, r7, #3
- 8000df6: 701a strb r2, [r3, #0]
+ 800108c: b580 push {r7, lr}
+ 800108e: b088 sub sp, #32
+ 8001090: af00 add r7, sp, #0
+ 8001092: 60f8 str r0, [r7, #12]
+ 8001094: 60b9 str r1, [r7, #8]
+ 8001096: 607a str r2, [r7, #4]
+ 8001098: 001a movs r2, r3
+ 800109a: 1cfb adds r3, r7, #3
+ 800109c: 701a strb r2, [r3, #0]
if (state->p == 0) {
- 8000df8: 68fb ldr r3, [r7, #12]
- 8000dfa: 681b ldr r3, [r3, #0]
- 8000dfc: 2b00 cmp r3, #0
- 8000dfe: d10e bne.n 8000e1e <cobs_decode_incremental+0x38>
+ 800109e: 68fb ldr r3, [r7, #12]
+ 80010a0: 681b ldr r3, [r3, #0]
+ 80010a2: 2b00 cmp r3, #0
+ 80010a4: d10e bne.n 80010c4 <cobs_decode_incremental+0x38>
if (src == 0)
- 8000e00: 1cfb adds r3, r7, #3
- 8000e02: 781b ldrb r3, [r3, #0]
- 8000e04: 2b00 cmp r3, #0
- 8000e06: d054 beq.n 8000eb2 <cobs_decode_incremental+0xcc>
+ 80010a6: 1cfb adds r3, r7, #3
+ 80010a8: 781b ldrb r3, [r3, #0]
+ 80010aa: 2b00 cmp r3, #0
+ 80010ac: d054 beq.n 8001158 <cobs_decode_incremental+0xcc>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
state->c = (unsigned char)src;
- 8000e08: 1cfb adds r3, r7, #3
- 8000e0a: 781a ldrb r2, [r3, #0]
- 8000e0c: 68fb ldr r3, [r7, #12]
- 8000e0e: 605a str r2, [r3, #4]
+ 80010ae: 1cfb adds r3, r7, #3
+ 80010b0: 781a ldrb r2, [r3, #0]
+ 80010b2: 68fb ldr r3, [r7, #12]
+ 80010b4: 605a str r2, [r3, #4]
state->p++;
- 8000e10: 68fb ldr r3, [r7, #12]
- 8000e12: 681b ldr r3, [r3, #0]
- 8000e14: 1c5a adds r2, r3, #1
- 8000e16: 68fb ldr r3, [r7, #12]
- 8000e18: 601a str r2, [r3, #0]
+ 80010b6: 68fb ldr r3, [r7, #12]
+ 80010b8: 681b ldr r3, [r3, #0]
+ 80010ba: 1c5a adds r2, r3, #1
+ 80010bc: 68fb ldr r3, [r7, #12]
+ 80010be: 601a str r2, [r3, #0]
return 0;
- 8000e1a: 2300 movs r3, #0
- 8000e1c: e050 b.n 8000ec0 <cobs_decode_incremental+0xda>
+ 80010c0: 2300 movs r3, #0
+ 80010c2: e050 b.n 8001166 <cobs_decode_incremental+0xda>
}
if (!src) {
- 8000e1e: 1cfb adds r3, r7, #3
- 8000e20: 781b ldrb r3, [r3, #0]
- 8000e22: 2b00 cmp r3, #0
- 8000e24: d10d bne.n 8000e42 <cobs_decode_incremental+0x5c>
+ 80010c4: 1cfb adds r3, r7, #3
+ 80010c6: 781b ldrb r3, [r3, #0]
+ 80010c8: 2b00 cmp r3, #0
+ 80010ca: d10d bne.n 80010e8 <cobs_decode_incremental+0x5c>
if (state->c != 1)
- 8000e26: 68fb ldr r3, [r7, #12]
- 8000e28: 685b ldr r3, [r3, #4]
- 8000e2a: 2b01 cmp r3, #1
- 8000e2c: d139 bne.n 8000ea2 <cobs_decode_incremental+0xbc>
+ 80010cc: 68fb ldr r3, [r7, #12]
+ 80010ce: 685b ldr r3, [r3, #4]
+ 80010d0: 2b01 cmp r3, #1
+ 80010d2: d139 bne.n 8001148 <cobs_decode_incremental+0xbc>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
int rv = state->p-1;
- 8000e2e: 68fb ldr r3, [r7, #12]
- 8000e30: 681b ldr r3, [r3, #0]
- 8000e32: 3b01 subs r3, #1
- 8000e34: 617b str r3, [r7, #20]
+ 80010d4: 68fb ldr r3, [r7, #12]
+ 80010d6: 681b ldr r3, [r3, #0]
+ 80010d8: 3b01 subs r3, #1
+ 80010da: 617b str r3, [r7, #20]
cobs_decode_incremental_initialize(state);
- 8000e36: 68fb ldr r3, [r7, #12]
- 8000e38: 0018 movs r0, r3
- 8000e3a: f7ff ffc6 bl 8000dca <cobs_decode_incremental_initialize>
+ 80010dc: 68fb ldr r3, [r7, #12]
+ 80010de: 0018 movs r0, r3
+ 80010e0: f7ff ffc6 bl 8001070 <cobs_decode_incremental_initialize>
return rv;
- 8000e3e: 697b ldr r3, [r7, #20]
- 8000e40: e03e b.n 8000ec0 <cobs_decode_incremental+0xda>
+ 80010e4: 697b ldr r3, [r7, #20]
+ 80010e6: e03e b.n 8001166 <cobs_decode_incremental+0xda>
}
char val;
state->c--;
- 8000e42: 68fb ldr r3, [r7, #12]
- 8000e44: 685b ldr r3, [r3, #4]
- 8000e46: 1e5a subs r2, r3, #1
- 8000e48: 68fb ldr r3, [r7, #12]
- 8000e4a: 605a str r2, [r3, #4]
+ 80010e8: 68fb ldr r3, [r7, #12]
+ 80010ea: 685b ldr r3, [r3, #4]
+ 80010ec: 1e5a subs r2, r3, #1
+ 80010ee: 68fb ldr r3, [r7, #12]
+ 80010f0: 605a str r2, [r3, #4]
if (state->c == 0) {
- 8000e4c: 68fb ldr r3, [r7, #12]
- 8000e4e: 685b ldr r3, [r3, #4]
- 8000e50: 2b00 cmp r3, #0
- 8000e52: d108 bne.n 8000e66 <cobs_decode_incremental+0x80>
+ 80010f2: 68fb ldr r3, [r7, #12]
+ 80010f4: 685b ldr r3, [r3, #4]
+ 80010f6: 2b00 cmp r3, #0
+ 80010f8: d108 bne.n 800110c <cobs_decode_incremental+0x80>
state->c = (unsigned char)src;
- 8000e54: 1cfb adds r3, r7, #3
- 8000e56: 781a ldrb r2, [r3, #0]
- 8000e58: 68fb ldr r3, [r7, #12]
- 8000e5a: 605a str r2, [r3, #4]
+ 80010fa: 1cfb adds r3, r7, #3
+ 80010fc: 781a ldrb r2, [r3, #0]
+ 80010fe: 68fb ldr r3, [r7, #12]
+ 8001100: 605a str r2, [r3, #4]
val = 0;
- 8000e5c: 231f movs r3, #31
- 8000e5e: 18fb adds r3, r7, r3
- 8000e60: 2200 movs r2, #0
- 8000e62: 701a strb r2, [r3, #0]
- 8000e64: e004 b.n 8000e70 <cobs_decode_incremental+0x8a>
+ 8001102: 231f movs r3, #31
+ 8001104: 18fb adds r3, r7, r3
+ 8001106: 2200 movs r2, #0
+ 8001108: 701a strb r2, [r3, #0]
+ 800110a: e004 b.n 8001116 <cobs_decode_incremental+0x8a>
} else {
val = src;
- 8000e66: 231f movs r3, #31
- 8000e68: 18fb adds r3, r7, r3
- 8000e6a: 1cfa adds r2, r7, #3
- 8000e6c: 7812 ldrb r2, [r2, #0]
- 8000e6e: 701a strb r2, [r3, #0]
+ 800110c: 231f movs r3, #31
+ 800110e: 18fb adds r3, r7, r3
+ 8001110: 1cfa adds r2, r7, #3
+ 8001112: 7812 ldrb r2, [r2, #0]
+ 8001114: 701a strb r2, [r3, #0]
}
size_t pos = state->p-1;
- 8000e70: 68fb ldr r3, [r7, #12]
- 8000e72: 681b ldr r3, [r3, #0]
- 8000e74: 3b01 subs r3, #1
- 8000e76: 61bb str r3, [r7, #24]
+ 8001116: 68fb ldr r3, [r7, #12]
+ 8001118: 681b ldr r3, [r3, #0]
+ 800111a: 3b01 subs r3, #1
+ 800111c: 61bb str r3, [r7, #24]
if (pos >= dstlen)
- 8000e78: 69ba ldr r2, [r7, #24]
- 8000e7a: 687b ldr r3, [r7, #4]
- 8000e7c: 429a cmp r2, r3
- 8000e7e: d302 bcc.n 8000e86 <cobs_decode_incremental+0xa0>
+ 800111e: 69ba ldr r2, [r7, #24]
+ 8001120: 687b ldr r3, [r7, #4]
+ 8001122: 429a cmp r2, r3
+ 8001124: d302 bcc.n 800112c <cobs_decode_incremental+0xa0>
return -2; /* output buffer too small */
- 8000e80: 2302 movs r3, #2
- 8000e82: 425b negs r3, r3
- 8000e84: e01c b.n 8000ec0 <cobs_decode_incremental+0xda>
+ 8001126: 2302 movs r3, #2
+ 8001128: 425b negs r3, r3
+ 800112a: e01c b.n 8001166 <cobs_decode_incremental+0xda>
dst[pos] = val;
- 8000e86: 68ba ldr r2, [r7, #8]
- 8000e88: 69bb ldr r3, [r7, #24]
- 8000e8a: 18d3 adds r3, r2, r3
- 8000e8c: 221f movs r2, #31
- 8000e8e: 18ba adds r2, r7, r2
- 8000e90: 7812 ldrb r2, [r2, #0]
- 8000e92: 701a strb r2, [r3, #0]
+ 800112c: 68ba ldr r2, [r7, #8]
+ 800112e: 69bb ldr r3, [r7, #24]
+ 8001130: 18d3 adds r3, r2, r3
+ 8001132: 221f movs r2, #31
+ 8001134: 18ba adds r2, r7, r2
+ 8001136: 7812 ldrb r2, [r2, #0]
+ 8001138: 701a strb r2, [r3, #0]
state->p++;
- 8000e94: 68fb ldr r3, [r7, #12]
- 8000e96: 681b ldr r3, [r3, #0]
- 8000e98: 1c5a adds r2, r3, #1
- 8000e9a: 68fb ldr r3, [r7, #12]
- 8000e9c: 601a str r2, [r3, #0]
+ 800113a: 68fb ldr r3, [r7, #12]
+ 800113c: 681b ldr r3, [r3, #0]
+ 800113e: 1c5a adds r2, r3, #1
+ 8001140: 68fb ldr r3, [r7, #12]
+ 8001142: 601a str r2, [r3, #0]
return 0;
- 8000e9e: 2300 movs r3, #0
- 8000ea0: e00e b.n 8000ec0 <cobs_decode_incremental+0xda>
+ 8001144: 2300 movs r3, #0
+ 8001146: e00e b.n 8001166 <cobs_decode_incremental+0xda>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 8000ea2: 46c0 nop ; (mov r8, r8)
+ 8001148: 46c0 nop ; (mov r8, r8)
errout:
cobs_decode_incremental_initialize(state);
- 8000ea4: 68fb ldr r3, [r7, #12]
- 8000ea6: 0018 movs r0, r3
- 8000ea8: f7ff ff8f bl 8000dca <cobs_decode_incremental_initialize>
+ 800114a: 68fb ldr r3, [r7, #12]
+ 800114c: 0018 movs r0, r3
+ 800114e: f7ff ff8f bl 8001070 <cobs_decode_incremental_initialize>
return -1;
- 8000eac: 2301 movs r3, #1
- 8000eae: 425b negs r3, r3
- 8000eb0: e006 b.n 8000ec0 <cobs_decode_incremental+0xda>
+ 8001152: 2301 movs r3, #1
+ 8001154: 425b negs r3, r3
+ 8001156: e006 b.n 8001166 <cobs_decode_incremental+0xda>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8000eb2: 46c0 nop ; (mov r8, r8)
+ 8001158: 46c0 nop ; (mov r8, r8)
empty_errout:
cobs_decode_incremental_initialize(state);
- 8000eb4: 68fb ldr r3, [r7, #12]
- 8000eb6: 0018 movs r0, r3
- 8000eb8: f7ff ff87 bl 8000dca <cobs_decode_incremental_initialize>
+ 800115a: 68fb ldr r3, [r7, #12]
+ 800115c: 0018 movs r0, r3
+ 800115e: f7ff ff87 bl 8001070 <cobs_decode_incremental_initialize>
return -3;
- 8000ebc: 2303 movs r3, #3
- 8000ebe: 425b negs r3, r3
+ 8001162: 2303 movs r3, #3
+ 8001164: 425b negs r3, r3
}
- 8000ec0: 0018 movs r0, r3
- 8000ec2: 46bd mov sp, r7
- 8000ec4: b008 add sp, #32
- 8000ec6: bd80 pop {r7, pc}
- 8000ec8: 080019bc .word 0x080019bc
- 8000ecc: 20000000 .word 0x20000000
- 8000ed0: 20000094 .word 0x20000094
- 8000ed4: 20000094 .word 0x20000094
- 8000ed8: 2000051c .word 0x2000051c
-
-08000edc <SystemInit>:
+ 8001166: 0018 movs r0, r3
+ 8001168: 46bd mov sp, r7
+ 800116a: b008 add sp, #32
+ 800116c: bd80 pop {r7, pc}
+ 800116e: 1c64 .short 0x1c64
+ 8001170: 00000800 .word 0x00000800
+ 8001174: 00942000 .word 0x00942000
+ 8001178: 00942000 .word 0x00942000
+ 800117c: 03b82000 .word 0x03b82000
+ 8001180: 00002000 .word 0x00002000
+
+08001184 <SystemInit>:
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 8000edc: b580 push {r7, lr}
- 8000ede: af00 add r7, sp, #0
+ 8001184: b580 push {r7, lr}
+ 8001186: af00 add r7, sp, #0
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
- 8000ee0: 4b1a ldr r3, [pc, #104] ; (8000f4c <SystemInit+0x70>)
- 8000ee2: 681a ldr r2, [r3, #0]
- 8000ee4: 4b19 ldr r3, [pc, #100] ; (8000f4c <SystemInit+0x70>)
- 8000ee6: 2101 movs r1, #1
- 8000ee8: 430a orrs r2, r1
- 8000eea: 601a str r2, [r3, #0]
+ 8001188: 4b1a ldr r3, [pc, #104] ; (80011f4 <SystemInit+0x70>)
+ 800118a: 681a ldr r2, [r3, #0]
+ 800118c: 4b19 ldr r3, [pc, #100] ; (80011f4 <SystemInit+0x70>)
+ 800118e: 2101 movs r1, #1
+ 8001190: 430a orrs r2, r1
+ 8001192: 601a str r2, [r3, #0]
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
- 8000eec: 4b17 ldr r3, [pc, #92] ; (8000f4c <SystemInit+0x70>)
- 8000eee: 685a ldr r2, [r3, #4]
- 8000ef0: 4b16 ldr r3, [pc, #88] ; (8000f4c <SystemInit+0x70>)
- 8000ef2: 4917 ldr r1, [pc, #92] ; (8000f50 <SystemInit+0x74>)
- 8000ef4: 400a ands r2, r1
- 8000ef6: 605a str r2, [r3, #4]
+ 8001194: 4b17 ldr r3, [pc, #92] ; (80011f4 <SystemInit+0x70>)
+ 8001196: 685a ldr r2, [r3, #4]
+ 8001198: 4b16 ldr r3, [pc, #88] ; (80011f4 <SystemInit+0x70>)
+ 800119a: 4917 ldr r1, [pc, #92] ; (80011f8 <SystemInit+0x74>)
+ 800119c: 400a ands r2, r1
+ 800119e: 605a str r2, [r3, #4]
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
- 8000ef8: 4b14 ldr r3, [pc, #80] ; (8000f4c <SystemInit+0x70>)
- 8000efa: 681a ldr r2, [r3, #0]
- 8000efc: 4b13 ldr r3, [pc, #76] ; (8000f4c <SystemInit+0x70>)
- 8000efe: 4915 ldr r1, [pc, #84] ; (8000f54 <SystemInit+0x78>)
- 8000f00: 400a ands r2, r1
- 8000f02: 601a str r2, [r3, #0]
+ 80011a0: 4b14 ldr r3, [pc, #80] ; (80011f4 <SystemInit+0x70>)
+ 80011a2: 681a ldr r2, [r3, #0]
+ 80011a4: 4b13 ldr r3, [pc, #76] ; (80011f4 <SystemInit+0x70>)
+ 80011a6: 4915 ldr r1, [pc, #84] ; (80011fc <SystemInit+0x78>)
+ 80011a8: 400a ands r2, r1
+ 80011aa: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
- 8000f04: 4b11 ldr r3, [pc, #68] ; (8000f4c <SystemInit+0x70>)
- 8000f06: 681a ldr r2, [r3, #0]
- 8000f08: 4b10 ldr r3, [pc, #64] ; (8000f4c <SystemInit+0x70>)
- 8000f0a: 4913 ldr r1, [pc, #76] ; (8000f58 <SystemInit+0x7c>)
- 8000f0c: 400a ands r2, r1
- 8000f0e: 601a str r2, [r3, #0]
+ 80011ac: 4b11 ldr r3, [pc, #68] ; (80011f4 <SystemInit+0x70>)
+ 80011ae: 681a ldr r2, [r3, #0]
+ 80011b0: 4b10 ldr r3, [pc, #64] ; (80011f4 <SystemInit+0x70>)
+ 80011b2: 4913 ldr r1, [pc, #76] ; (8001200 <SystemInit+0x7c>)
+ 80011b4: 400a ands r2, r1
+ 80011b6: 601a str r2, [r3, #0]
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
- 8000f10: 4b0e ldr r3, [pc, #56] ; (8000f4c <SystemInit+0x70>)
- 8000f12: 685a ldr r2, [r3, #4]
- 8000f14: 4b0d ldr r3, [pc, #52] ; (8000f4c <SystemInit+0x70>)
- 8000f16: 4911 ldr r1, [pc, #68] ; (8000f5c <SystemInit+0x80>)
- 8000f18: 400a ands r2, r1
- 8000f1a: 605a str r2, [r3, #4]
+ 80011b8: 4b0e ldr r3, [pc, #56] ; (80011f4 <SystemInit+0x70>)
+ 80011ba: 685a ldr r2, [r3, #4]
+ 80011bc: 4b0d ldr r3, [pc, #52] ; (80011f4 <SystemInit+0x70>)
+ 80011be: 4911 ldr r1, [pc, #68] ; (8001204 <SystemInit+0x80>)
+ 80011c0: 400a ands r2, r1
+ 80011c2: 605a str r2, [r3, #4]
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
- 8000f1c: 4b0b ldr r3, [pc, #44] ; (8000f4c <SystemInit+0x70>)
- 8000f1e: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000f20: 4b0a ldr r3, [pc, #40] ; (8000f4c <SystemInit+0x70>)
- 8000f22: 210f movs r1, #15
- 8000f24: 438a bics r2, r1
- 8000f26: 62da str r2, [r3, #44] ; 0x2c
+ 80011c4: 4b0b ldr r3, [pc, #44] ; (80011f4 <SystemInit+0x70>)
+ 80011c6: 6ada ldr r2, [r3, #44] ; 0x2c
+ 80011c8: 4b0a ldr r3, [pc, #40] ; (80011f4 <SystemInit+0x70>)
+ 80011ca: 210f movs r1, #15
+ 80011cc: 438a bics r2, r1
+ 80011ce: 62da str r2, [r3, #44] ; 0x2c
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
- 8000f28: 4b08 ldr r3, [pc, #32] ; (8000f4c <SystemInit+0x70>)
- 8000f2a: 6b1a ldr r2, [r3, #48] ; 0x30
- 8000f2c: 4b07 ldr r3, [pc, #28] ; (8000f4c <SystemInit+0x70>)
- 8000f2e: 490c ldr r1, [pc, #48] ; (8000f60 <SystemInit+0x84>)
- 8000f30: 400a ands r2, r1
- 8000f32: 631a str r2, [r3, #48] ; 0x30
+ 80011d0: 4b08 ldr r3, [pc, #32] ; (80011f4 <SystemInit+0x70>)
+ 80011d2: 6b1a ldr r2, [r3, #48] ; 0x30
+ 80011d4: 4b07 ldr r3, [pc, #28] ; (80011f4 <SystemInit+0x70>)
+ 80011d6: 490c ldr r1, [pc, #48] ; (8001208 <SystemInit+0x84>)
+ 80011d8: 400a ands r2, r1
+ 80011da: 631a str r2, [r3, #48] ; 0x30
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
- 8000f34: 4b05 ldr r3, [pc, #20] ; (8000f4c <SystemInit+0x70>)
- 8000f36: 6b5a ldr r2, [r3, #52] ; 0x34
- 8000f38: 4b04 ldr r3, [pc, #16] ; (8000f4c <SystemInit+0x70>)
- 8000f3a: 2101 movs r1, #1
- 8000f3c: 438a bics r2, r1
- 8000f3e: 635a str r2, [r3, #52] ; 0x34
+ 80011dc: 4b05 ldr r3, [pc, #20] ; (80011f4 <SystemInit+0x70>)
+ 80011de: 6b5a ldr r2, [r3, #52] ; 0x34
+ 80011e0: 4b04 ldr r3, [pc, #16] ; (80011f4 <SystemInit+0x70>)
+ 80011e2: 2101 movs r1, #1
+ 80011e4: 438a bics r2, r1
+ 80011e6: 635a str r2, [r3, #52] ; 0x34
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
- 8000f40: 4b02 ldr r3, [pc, #8] ; (8000f4c <SystemInit+0x70>)
- 8000f42: 2200 movs r2, #0
- 8000f44: 609a str r2, [r3, #8]
+ 80011e8: 4b02 ldr r3, [pc, #8] ; (80011f4 <SystemInit+0x70>)
+ 80011ea: 2200 movs r2, #0
+ 80011ec: 609a str r2, [r3, #8]
}
- 8000f46: 46c0 nop ; (mov r8, r8)
- 8000f48: 46bd mov sp, r7
- 8000f4a: bd80 pop {r7, pc}
- 8000f4c: 40021000 .word 0x40021000
- 8000f50: 08ffb80c .word 0x08ffb80c
- 8000f54: fef6ffff .word 0xfef6ffff
- 8000f58: fffbffff .word 0xfffbffff
- 8000f5c: ffc0ffff .word 0xffc0ffff
- 8000f60: fffffeec .word 0xfffffeec
-
-08000f64 <SystemCoreClockUpdate>:
+ 80011ee: 46c0 nop ; (mov r8, r8)
+ 80011f0: 46bd mov sp, r7
+ 80011f2: bd80 pop {r7, pc}
+ 80011f4: 40021000 .word 0x40021000
+ 80011f8: 08ffb80c .word 0x08ffb80c
+ 80011fc: fef6ffff .word 0xfef6ffff
+ 8001200: fffbffff .word 0xfffbffff
+ 8001204: ffc0ffff .word 0xffc0ffff
+ 8001208: fffffeec .word 0xfffffeec
+
+0800120c <SystemCoreClockUpdate>:
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
- 8000f64: b580 push {r7, lr}
- 8000f66: b084 sub sp, #16
- 8000f68: af00 add r7, sp, #0
+ 800120c: b580 push {r7, lr}
+ 800120e: b084 sub sp, #16
+ 8001210: af00 add r7, sp, #0
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
- 8000f6a: 2300 movs r3, #0
- 8000f6c: 60fb str r3, [r7, #12]
- 8000f6e: 2300 movs r3, #0
- 8000f70: 60bb str r3, [r7, #8]
- 8000f72: 2300 movs r3, #0
- 8000f74: 607b str r3, [r7, #4]
- 8000f76: 2300 movs r3, #0
- 8000f78: 603b str r3, [r7, #0]
+ 8001212: 2300 movs r3, #0
+ 8001214: 60fb str r3, [r7, #12]
+ 8001216: 2300 movs r3, #0
+ 8001218: 60bb str r3, [r7, #8]
+ 800121a: 2300 movs r3, #0
+ 800121c: 607b str r3, [r7, #4]
+ 800121e: 2300 movs r3, #0
+ 8001220: 603b str r3, [r7, #0]
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
- 8000f7a: 4b31 ldr r3, [pc, #196] ; (8001040 <SystemCoreClockUpdate+0xdc>)
- 8000f7c: 685b ldr r3, [r3, #4]
- 8000f7e: 220c movs r2, #12
- 8000f80: 4013 ands r3, r2
- 8000f82: 60fb str r3, [r7, #12]
+ 8001222: 4b31 ldr r3, [pc, #196] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
+ 8001224: 685b ldr r3, [r3, #4]
+ 8001226: 220c movs r2, #12
+ 8001228: 4013 ands r3, r2
+ 800122a: 60fb str r3, [r7, #12]
switch (tmp)
- 8000f84: 68fb ldr r3, [r7, #12]
- 8000f86: 2b08 cmp r3, #8
- 8000f88: d011 beq.n 8000fae <SystemCoreClockUpdate+0x4a>
- 8000f8a: 68fb ldr r3, [r7, #12]
- 8000f8c: 2b08 cmp r3, #8
- 8000f8e: d841 bhi.n 8001014 <SystemCoreClockUpdate+0xb0>
- 8000f90: 68fb ldr r3, [r7, #12]
- 8000f92: 2b00 cmp r3, #0
- 8000f94: d003 beq.n 8000f9e <SystemCoreClockUpdate+0x3a>
- 8000f96: 68fb ldr r3, [r7, #12]
- 8000f98: 2b04 cmp r3, #4
- 8000f9a: d004 beq.n 8000fa6 <SystemCoreClockUpdate+0x42>
- 8000f9c: e03a b.n 8001014 <SystemCoreClockUpdate+0xb0>
+ 800122c: 68fb ldr r3, [r7, #12]
+ 800122e: 2b08 cmp r3, #8
+ 8001230: d011 beq.n 8001256 <SystemCoreClockUpdate+0x4a>
+ 8001232: 68fb ldr r3, [r7, #12]
+ 8001234: 2b08 cmp r3, #8
+ 8001236: d841 bhi.n 80012bc <SystemCoreClockUpdate+0xb0>
+ 8001238: 68fb ldr r3, [r7, #12]
+ 800123a: 2b00 cmp r3, #0
+ 800123c: d003 beq.n 8001246 <SystemCoreClockUpdate+0x3a>
+ 800123e: 68fb ldr r3, [r7, #12]
+ 8001240: 2b04 cmp r3, #4
+ 8001242: d004 beq.n 800124e <SystemCoreClockUpdate+0x42>
+ 8001244: e03a b.n 80012bc <SystemCoreClockUpdate+0xb0>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 8000f9e: 4b29 ldr r3, [pc, #164] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8000fa0: 4a29 ldr r2, [pc, #164] ; (8001048 <SystemCoreClockUpdate+0xe4>)
- 8000fa2: 601a str r2, [r3, #0]
+ 8001246: 4b29 ldr r3, [pc, #164] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 8001248: 4a29 ldr r2, [pc, #164] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
+ 800124a: 601a str r2, [r3, #0]
break;
- 8000fa4: e03a b.n 800101c <SystemCoreClockUpdate+0xb8>
+ 800124c: e03a b.n 80012c4 <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
- 8000fa6: 4b27 ldr r3, [pc, #156] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8000fa8: 4a27 ldr r2, [pc, #156] ; (8001048 <SystemCoreClockUpdate+0xe4>)
- 8000faa: 601a str r2, [r3, #0]
+ 800124e: 4b27 ldr r3, [pc, #156] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 8001250: 4a27 ldr r2, [pc, #156] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
+ 8001252: 601a str r2, [r3, #0]
break;
- 8000fac: e036 b.n 800101c <SystemCoreClockUpdate+0xb8>
+ 8001254: e036 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- 8000fae: 4b24 ldr r3, [pc, #144] ; (8001040 <SystemCoreClockUpdate+0xdc>)
- 8000fb0: 685a ldr r2, [r3, #4]
- 8000fb2: 23f0 movs r3, #240 ; 0xf0
- 8000fb4: 039b lsls r3, r3, #14
- 8000fb6: 4013 ands r3, r2
- 8000fb8: 60bb str r3, [r7, #8]
+ 8001256: 4b24 ldr r3, [pc, #144] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
+ 8001258: 685a ldr r2, [r3, #4]
+ 800125a: 23f0 movs r3, #240 ; 0xf0
+ 800125c: 039b lsls r3, r3, #14
+ 800125e: 4013 ands r3, r2
+ 8001260: 60bb str r3, [r7, #8]
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- 8000fba: 4b21 ldr r3, [pc, #132] ; (8001040 <SystemCoreClockUpdate+0xdc>)
- 8000fbc: 685a ldr r2, [r3, #4]
- 8000fbe: 2380 movs r3, #128 ; 0x80
- 8000fc0: 025b lsls r3, r3, #9
- 8000fc2: 4013 ands r3, r2
- 8000fc4: 607b str r3, [r7, #4]
+ 8001262: 4b21 ldr r3, [pc, #132] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
+ 8001264: 685a ldr r2, [r3, #4]
+ 8001266: 2380 movs r3, #128 ; 0x80
+ 8001268: 025b lsls r3, r3, #9
+ 800126a: 4013 ands r3, r2
+ 800126c: 607b str r3, [r7, #4]
pllmull = ( pllmull >> 18) + 2;
- 8000fc6: 68bb ldr r3, [r7, #8]
- 8000fc8: 0c9b lsrs r3, r3, #18
- 8000fca: 3302 adds r3, #2
- 8000fcc: 60bb str r3, [r7, #8]
+ 800126e: 68bb ldr r3, [r7, #8]
+ 8001270: 0c9b lsrs r3, r3, #18
+ 8001272: 3302 adds r3, #2
+ 8001274: 60bb str r3, [r7, #8]
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- 8000fce: 4b1c ldr r3, [pc, #112] ; (8001040 <SystemCoreClockUpdate+0xdc>)
- 8000fd0: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000fd2: 220f movs r2, #15
- 8000fd4: 4013 ands r3, r2
- 8000fd6: 3301 adds r3, #1
- 8000fd8: 603b str r3, [r7, #0]
+ 8001276: 4b1c ldr r3, [pc, #112] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
+ 8001278: 6adb ldr r3, [r3, #44] ; 0x2c
+ 800127a: 220f movs r2, #15
+ 800127c: 4013 ands r3, r2
+ 800127e: 3301 adds r3, #1
+ 8001280: 603b str r3, [r7, #0]
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- 8000fda: 687a ldr r2, [r7, #4]
- 8000fdc: 2380 movs r3, #128 ; 0x80
- 8000fde: 025b lsls r3, r3, #9
- 8000fe0: 429a cmp r2, r3
- 8000fe2: d10a bne.n 8000ffa <SystemCoreClockUpdate+0x96>
+ 8001282: 687a ldr r2, [r7, #4]
+ 8001284: 2380 movs r3, #128 ; 0x80
+ 8001286: 025b lsls r3, r3, #9
+ 8001288: 429a cmp r2, r3
+ 800128a: d10a bne.n 80012a2 <SystemCoreClockUpdate+0x96>
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- 8000fe4: 6839 ldr r1, [r7, #0]
- 8000fe6: 4818 ldr r0, [pc, #96] ; (8001048 <SystemCoreClockUpdate+0xe4>)
- 8000fe8: f000 fb3e bl 8001668 <__udivsi3>
- 8000fec: 0003 movs r3, r0
- 8000fee: 001a movs r2, r3
- 8000ff0: 68bb ldr r3, [r7, #8]
- 8000ff2: 435a muls r2, r3
- 8000ff4: 4b13 ldr r3, [pc, #76] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8000ff6: 601a str r2, [r3, #0]
+ 800128c: 6839 ldr r1, [r7, #0]
+ 800128e: 4818 ldr r0, [pc, #96] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
+ 8001290: f000 fb3e bl 8001910 <__udivsi3>
+ 8001294: 0003 movs r3, r0
+ 8001296: 001a movs r2, r3
+ 8001298: 68bb ldr r3, [r7, #8]
+ 800129a: 435a muls r2, r3
+ 800129c: 4b13 ldr r3, [pc, #76] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 800129e: 601a str r2, [r3, #0]
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
- 8000ff8: e010 b.n 800101c <SystemCoreClockUpdate+0xb8>
+ 80012a0: e010 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- 8000ffa: 68b9 ldr r1, [r7, #8]
- 8000ffc: 000a movs r2, r1
- 8000ffe: 0152 lsls r2, r2, #5
- 8001000: 1a52 subs r2, r2, r1
- 8001002: 0193 lsls r3, r2, #6
- 8001004: 1a9b subs r3, r3, r2
- 8001006: 00db lsls r3, r3, #3
- 8001008: 185b adds r3, r3, r1
- 800100a: 021b lsls r3, r3, #8
- 800100c: 001a movs r2, r3
- 800100e: 4b0d ldr r3, [pc, #52] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8001010: 601a str r2, [r3, #0]
+ 80012a2: 68b9 ldr r1, [r7, #8]
+ 80012a4: 000a movs r2, r1
+ 80012a6: 0152 lsls r2, r2, #5
+ 80012a8: 1a52 subs r2, r2, r1
+ 80012aa: 0193 lsls r3, r2, #6
+ 80012ac: 1a9b subs r3, r3, r2
+ 80012ae: 00db lsls r3, r3, #3
+ 80012b0: 185b adds r3, r3, r1
+ 80012b2: 021b lsls r3, r3, #8
+ 80012b4: 001a movs r2, r3
+ 80012b6: 4b0d ldr r3, [pc, #52] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 80012b8: 601a str r2, [r3, #0]
break;
- 8001012: e003 b.n 800101c <SystemCoreClockUpdate+0xb8>
+ 80012ba: e003 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 8001014: 4b0b ldr r3, [pc, #44] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8001016: 4a0c ldr r2, [pc, #48] ; (8001048 <SystemCoreClockUpdate+0xe4>)
- 8001018: 601a str r2, [r3, #0]
+ 80012bc: 4b0b ldr r3, [pc, #44] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 80012be: 4a0c ldr r2, [pc, #48] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
+ 80012c0: 601a str r2, [r3, #0]
break;
- 800101a: 46c0 nop ; (mov r8, r8)
+ 80012c2: 46c0 nop ; (mov r8, r8)
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- 800101c: 4b08 ldr r3, [pc, #32] ; (8001040 <SystemCoreClockUpdate+0xdc>)
- 800101e: 685b ldr r3, [r3, #4]
- 8001020: 091b lsrs r3, r3, #4
- 8001022: 220f movs r2, #15
- 8001024: 4013 ands r3, r2
- 8001026: 4a09 ldr r2, [pc, #36] ; (800104c <SystemCoreClockUpdate+0xe8>)
- 8001028: 5cd3 ldrb r3, [r2, r3]
- 800102a: 60fb str r3, [r7, #12]
+ 80012c4: 4b08 ldr r3, [pc, #32] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
+ 80012c6: 685b ldr r3, [r3, #4]
+ 80012c8: 091b lsrs r3, r3, #4
+ 80012ca: 220f movs r2, #15
+ 80012cc: 4013 ands r3, r2
+ 80012ce: 4a09 ldr r2, [pc, #36] ; (80012f4 <SystemCoreClockUpdate+0xe8>)
+ 80012d0: 5cd3 ldrb r3, [r2, r3]
+ 80012d2: 60fb str r3, [r7, #12]
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
- 800102c: 4b05 ldr r3, [pc, #20] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 800102e: 681a ldr r2, [r3, #0]
- 8001030: 68fb ldr r3, [r7, #12]
- 8001032: 40da lsrs r2, r3
- 8001034: 4b03 ldr r3, [pc, #12] ; (8001044 <SystemCoreClockUpdate+0xe0>)
- 8001036: 601a str r2, [r3, #0]
+ 80012d4: 4b05 ldr r3, [pc, #20] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 80012d6: 681a ldr r2, [r3, #0]
+ 80012d8: 68fb ldr r3, [r7, #12]
+ 80012da: 40da lsrs r2, r3
+ 80012dc: 4b03 ldr r3, [pc, #12] ; (80012ec <SystemCoreClockUpdate+0xe0>)
+ 80012de: 601a str r2, [r3, #0]
}
- 8001038: 46c0 nop ; (mov r8, r8)
- 800103a: 46bd mov sp, r7
- 800103c: b004 add sp, #16
- 800103e: bd80 pop {r7, pc}
- 8001040: 40021000 .word 0x40021000
- 8001044: 20000000 .word 0x20000000
- 8001048: 007a1200 .word 0x007a1200
- 800104c: 080019a4 .word 0x080019a4
-
-08001050 <LL_RCC_HSE_EnableBypass>:
+ 80012e0: 46c0 nop ; (mov r8, r8)
+ 80012e2: 46bd mov sp, r7
+ 80012e4: b004 add sp, #16
+ 80012e6: bd80 pop {r7, pc}
+ 80012e8: 40021000 .word 0x40021000
+ 80012ec: 20000000 .word 0x20000000
+ 80012f0: 007a1200 .word 0x007a1200
+ 80012f4: 08001c4c .word 0x08001c4c
+
+080012f8 <LL_RCC_HSE_EnableBypass>:
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
- 8001050: b580 push {r7, lr}
- 8001052: af00 add r7, sp, #0
+ 80012f8: b580 push {r7, lr}
+ 80012fa: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
- 8001054: 4b04 ldr r3, [pc, #16] ; (8001068 <LL_RCC_HSE_EnableBypass+0x18>)
- 8001056: 681a ldr r2, [r3, #0]
- 8001058: 4b03 ldr r3, [pc, #12] ; (8001068 <LL_RCC_HSE_EnableBypass+0x18>)
- 800105a: 2180 movs r1, #128 ; 0x80
- 800105c: 02c9 lsls r1, r1, #11
- 800105e: 430a orrs r2, r1
- 8001060: 601a str r2, [r3, #0]
+ 80012fc: 4b04 ldr r3, [pc, #16] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
+ 80012fe: 681a ldr r2, [r3, #0]
+ 8001300: 4b03 ldr r3, [pc, #12] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
+ 8001302: 2180 movs r1, #128 ; 0x80
+ 8001304: 02c9 lsls r1, r1, #11
+ 8001306: 430a orrs r2, r1
+ 8001308: 601a str r2, [r3, #0]
}
- 8001062: 46c0 nop ; (mov r8, r8)
- 8001064: 46bd mov sp, r7
- 8001066: bd80 pop {r7, pc}
- 8001068: 40021000 .word 0x40021000
+ 800130a: 46c0 nop ; (mov r8, r8)
+ 800130c: 46bd mov sp, r7
+ 800130e: bd80 pop {r7, pc}
+ 8001310: 40021000 .word 0x40021000
-0800106c <LL_RCC_HSE_DisableBypass>:
+08001314 <LL_RCC_HSE_DisableBypass>:
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
- 800106c: b580 push {r7, lr}
- 800106e: af00 add r7, sp, #0
+ 8001314: b580 push {r7, lr}
+ 8001316: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
- 8001070: 4b04 ldr r3, [pc, #16] ; (8001084 <LL_RCC_HSE_DisableBypass+0x18>)
- 8001072: 681a ldr r2, [r3, #0]
- 8001074: 4b03 ldr r3, [pc, #12] ; (8001084 <LL_RCC_HSE_DisableBypass+0x18>)
- 8001076: 4904 ldr r1, [pc, #16] ; (8001088 <LL_RCC_HSE_DisableBypass+0x1c>)
- 8001078: 400a ands r2, r1
- 800107a: 601a str r2, [r3, #0]
+ 8001318: 4b04 ldr r3, [pc, #16] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
+ 800131a: 681a ldr r2, [r3, #0]
+ 800131c: 4b03 ldr r3, [pc, #12] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
+ 800131e: 4904 ldr r1, [pc, #16] ; (8001330 <LL_RCC_HSE_DisableBypass+0x1c>)
+ 8001320: 400a ands r2, r1
+ 8001322: 601a str r2, [r3, #0]
}
- 800107c: 46c0 nop ; (mov r8, r8)
- 800107e: 46bd mov sp, r7
- 8001080: bd80 pop {r7, pc}
- 8001082: 46c0 nop ; (mov r8, r8)
- 8001084: 40021000 .word 0x40021000
- 8001088: fffbffff .word 0xfffbffff
-
-0800108c <LL_RCC_HSE_Enable>:
+ 8001324: 46c0 nop ; (mov r8, r8)
+ 8001326: 46bd mov sp, r7
+ 8001328: bd80 pop {r7, pc}
+ 800132a: 46c0 nop ; (mov r8, r8)
+ 800132c: 40021000 .word 0x40021000
+ 8001330: fffbffff .word 0xfffbffff
+
+08001334 <LL_RCC_HSE_Enable>:
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
- 800108c: b580 push {r7, lr}
- 800108e: af00 add r7, sp, #0
+ 8001334: b580 push {r7, lr}
+ 8001336: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEON);
- 8001090: 4b04 ldr r3, [pc, #16] ; (80010a4 <LL_RCC_HSE_Enable+0x18>)
- 8001092: 681a ldr r2, [r3, #0]
- 8001094: 4b03 ldr r3, [pc, #12] ; (80010a4 <LL_RCC_HSE_Enable+0x18>)
- 8001096: 2180 movs r1, #128 ; 0x80
- 8001098: 0249 lsls r1, r1, #9
- 800109a: 430a orrs r2, r1
- 800109c: 601a str r2, [r3, #0]
+ 8001338: 4b04 ldr r3, [pc, #16] ; (800134c <LL_RCC_HSE_Enable+0x18>)
+ 800133a: 681a ldr r2, [r3, #0]
+ 800133c: 4b03 ldr r3, [pc, #12] ; (800134c <LL_RCC_HSE_Enable+0x18>)
+ 800133e: 2180 movs r1, #128 ; 0x80
+ 8001340: 0249 lsls r1, r1, #9
+ 8001342: 430a orrs r2, r1
+ 8001344: 601a str r2, [r3, #0]
}
- 800109e: 46c0 nop ; (mov r8, r8)
- 80010a0: 46bd mov sp, r7
- 80010a2: bd80 pop {r7, pc}
- 80010a4: 40021000 .word 0x40021000
+ 8001346: 46c0 nop ; (mov r8, r8)
+ 8001348: 46bd mov sp, r7
+ 800134a: bd80 pop {r7, pc}
+ 800134c: 40021000 .word 0x40021000
-080010a8 <LL_RCC_HSE_IsReady>:
+08001350 <LL_RCC_HSE_IsReady>:
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
- 80010a8: b580 push {r7, lr}
- 80010aa: af00 add r7, sp, #0
+ 8001350: b580 push {r7, lr}
+ 8001352: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
- 80010ac: 4b06 ldr r3, [pc, #24] ; (80010c8 <LL_RCC_HSE_IsReady+0x20>)
- 80010ae: 681a ldr r2, [r3, #0]
- 80010b0: 2380 movs r3, #128 ; 0x80
- 80010b2: 029b lsls r3, r3, #10
- 80010b4: 4013 ands r3, r2
- 80010b6: 4a05 ldr r2, [pc, #20] ; (80010cc <LL_RCC_HSE_IsReady+0x24>)
- 80010b8: 4694 mov ip, r2
- 80010ba: 4463 add r3, ip
- 80010bc: 425a negs r2, r3
- 80010be: 4153 adcs r3, r2
- 80010c0: b2db uxtb r3, r3
+ 8001354: 4b06 ldr r3, [pc, #24] ; (8001370 <LL_RCC_HSE_IsReady+0x20>)
+ 8001356: 681a ldr r2, [r3, #0]
+ 8001358: 2380 movs r3, #128 ; 0x80
+ 800135a: 029b lsls r3, r3, #10
+ 800135c: 4013 ands r3, r2
+ 800135e: 4a05 ldr r2, [pc, #20] ; (8001374 <LL_RCC_HSE_IsReady+0x24>)
+ 8001360: 4694 mov ip, r2
+ 8001362: 4463 add r3, ip
+ 8001364: 425a negs r2, r3
+ 8001366: 4153 adcs r3, r2
+ 8001368: b2db uxtb r3, r3
}
- 80010c2: 0018 movs r0, r3
- 80010c4: 46bd mov sp, r7
- 80010c6: bd80 pop {r7, pc}
- 80010c8: 40021000 .word 0x40021000
- 80010cc: fffe0000 .word 0xfffe0000
+ 800136a: 0018 movs r0, r3
+ 800136c: 46bd mov sp, r7
+ 800136e: bd80 pop {r7, pc}
+ 8001370: 40021000 .word 0x40021000
+ 8001374: fffe0000 .word 0xfffe0000
-080010d0 <LL_RCC_HSI_Enable>:
+08001378 <LL_RCC_HSI_Enable>:
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
- 80010d0: b580 push {r7, lr}
- 80010d2: af00 add r7, sp, #0
+ 8001378: b580 push {r7, lr}
+ 800137a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSION);
- 80010d4: 4b04 ldr r3, [pc, #16] ; (80010e8 <LL_RCC_HSI_Enable+0x18>)
- 80010d6: 681a ldr r2, [r3, #0]
- 80010d8: 4b03 ldr r3, [pc, #12] ; (80010e8 <LL_RCC_HSI_Enable+0x18>)
- 80010da: 2101 movs r1, #1
- 80010dc: 430a orrs r2, r1
- 80010de: 601a str r2, [r3, #0]
+ 800137c: 4b04 ldr r3, [pc, #16] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
+ 800137e: 681a ldr r2, [r3, #0]
+ 8001380: 4b03 ldr r3, [pc, #12] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
+ 8001382: 2101 movs r1, #1
+ 8001384: 430a orrs r2, r1
+ 8001386: 601a str r2, [r3, #0]
}
- 80010e0: 46c0 nop ; (mov r8, r8)
- 80010e2: 46bd mov sp, r7
- 80010e4: bd80 pop {r7, pc}
- 80010e6: 46c0 nop ; (mov r8, r8)
- 80010e8: 40021000 .word 0x40021000
+ 8001388: 46c0 nop ; (mov r8, r8)
+ 800138a: 46bd mov sp, r7
+ 800138c: bd80 pop {r7, pc}
+ 800138e: 46c0 nop ; (mov r8, r8)
+ 8001390: 40021000 .word 0x40021000
-080010ec <LL_RCC_HSI_IsReady>:
+08001394 <LL_RCC_HSI_IsReady>:
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
- 80010ec: b580 push {r7, lr}
- 80010ee: af00 add r7, sp, #0
+ 8001394: b580 push {r7, lr}
+ 8001396: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
- 80010f0: 4b05 ldr r3, [pc, #20] ; (8001108 <LL_RCC_HSI_IsReady+0x1c>)
- 80010f2: 681b ldr r3, [r3, #0]
- 80010f4: 2202 movs r2, #2
- 80010f6: 4013 ands r3, r2
- 80010f8: 3b02 subs r3, #2
- 80010fa: 425a negs r2, r3
- 80010fc: 4153 adcs r3, r2
- 80010fe: b2db uxtb r3, r3
+ 8001398: 4b05 ldr r3, [pc, #20] ; (80013b0 <LL_RCC_HSI_IsReady+0x1c>)
+ 800139a: 681b ldr r3, [r3, #0]
+ 800139c: 2202 movs r2, #2
+ 800139e: 4013 ands r3, r2
+ 80013a0: 3b02 subs r3, #2
+ 80013a2: 425a negs r2, r3
+ 80013a4: 4153 adcs r3, r2
+ 80013a6: b2db uxtb r3, r3
}
- 8001100: 0018 movs r0, r3
- 8001102: 46bd mov sp, r7
- 8001104: bd80 pop {r7, pc}
- 8001106: 46c0 nop ; (mov r8, r8)
- 8001108: 40021000 .word 0x40021000
+ 80013a8: 0018 movs r0, r3
+ 80013aa: 46bd mov sp, r7
+ 80013ac: bd80 pop {r7, pc}
+ 80013ae: 46c0 nop ; (mov r8, r8)
+ 80013b0: 40021000 .word 0x40021000
-0800110c <LL_RCC_SetSysClkSource>:
+080013b4 <LL_RCC_SetSysClkSource>:
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
- 800110c: b580 push {r7, lr}
- 800110e: b082 sub sp, #8
- 8001110: af00 add r7, sp, #0
- 8001112: 6078 str r0, [r7, #4]
+ 80013b4: b580 push {r7, lr}
+ 80013b6: b082 sub sp, #8
+ 80013b8: af00 add r7, sp, #0
+ 80013ba: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
- 8001114: 4b06 ldr r3, [pc, #24] ; (8001130 <LL_RCC_SetSysClkSource+0x24>)
- 8001116: 685b ldr r3, [r3, #4]
- 8001118: 2203 movs r2, #3
- 800111a: 4393 bics r3, r2
- 800111c: 0019 movs r1, r3
- 800111e: 4b04 ldr r3, [pc, #16] ; (8001130 <LL_RCC_SetSysClkSource+0x24>)
- 8001120: 687a ldr r2, [r7, #4]
- 8001122: 430a orrs r2, r1
- 8001124: 605a str r2, [r3, #4]
+ 80013bc: 4b06 ldr r3, [pc, #24] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
+ 80013be: 685b ldr r3, [r3, #4]
+ 80013c0: 2203 movs r2, #3
+ 80013c2: 4393 bics r3, r2
+ 80013c4: 0019 movs r1, r3
+ 80013c6: 4b04 ldr r3, [pc, #16] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
+ 80013c8: 687a ldr r2, [r7, #4]
+ 80013ca: 430a orrs r2, r1
+ 80013cc: 605a str r2, [r3, #4]
}
- 8001126: 46c0 nop ; (mov r8, r8)
- 8001128: 46bd mov sp, r7
- 800112a: b002 add sp, #8
- 800112c: bd80 pop {r7, pc}
- 800112e: 46c0 nop ; (mov r8, r8)
- 8001130: 40021000 .word 0x40021000
-
-08001134 <LL_RCC_GetSysClkSource>:
+ 80013ce: 46c0 nop ; (mov r8, r8)
+ 80013d0: 46bd mov sp, r7
+ 80013d2: b002 add sp, #8
+ 80013d4: bd80 pop {r7, pc}
+ 80013d6: 46c0 nop ; (mov r8, r8)
+ 80013d8: 40021000 .word 0x40021000
+
+080013dc <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
- 8001134: b580 push {r7, lr}
- 8001136: af00 add r7, sp, #0
+ 80013dc: b580 push {r7, lr}
+ 80013de: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
- 8001138: 4b03 ldr r3, [pc, #12] ; (8001148 <LL_RCC_GetSysClkSource+0x14>)
- 800113a: 685b ldr r3, [r3, #4]
- 800113c: 220c movs r2, #12
- 800113e: 4013 ands r3, r2
+ 80013e0: 4b03 ldr r3, [pc, #12] ; (80013f0 <LL_RCC_GetSysClkSource+0x14>)
+ 80013e2: 685b ldr r3, [r3, #4]
+ 80013e4: 220c movs r2, #12
+ 80013e6: 4013 ands r3, r2
}
- 8001140: 0018 movs r0, r3
- 8001142: 46bd mov sp, r7
- 8001144: bd80 pop {r7, pc}
- 8001146: 46c0 nop ; (mov r8, r8)
- 8001148: 40021000 .word 0x40021000
+ 80013e8: 0018 movs r0, r3
+ 80013ea: 46bd mov sp, r7
+ 80013ec: bd80 pop {r7, pc}
+ 80013ee: 46c0 nop ; (mov r8, r8)
+ 80013f0: 40021000 .word 0x40021000
-0800114c <LL_RCC_SetAHBPrescaler>:
+080013f4 <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
- 800114c: b580 push {r7, lr}
- 800114e: b082 sub sp, #8
- 8001150: af00 add r7, sp, #0
- 8001152: 6078 str r0, [r7, #4]
+ 80013f4: b580 push {r7, lr}
+ 80013f6: b082 sub sp, #8
+ 80013f8: af00 add r7, sp, #0
+ 80013fa: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
- 8001154: 4b06 ldr r3, [pc, #24] ; (8001170 <LL_RCC_SetAHBPrescaler+0x24>)
- 8001156: 685b ldr r3, [r3, #4]
- 8001158: 22f0 movs r2, #240 ; 0xf0
- 800115a: 4393 bics r3, r2
- 800115c: 0019 movs r1, r3
- 800115e: 4b04 ldr r3, [pc, #16] ; (8001170 <LL_RCC_SetAHBPrescaler+0x24>)
- 8001160: 687a ldr r2, [r7, #4]
- 8001162: 430a orrs r2, r1
- 8001164: 605a str r2, [r3, #4]
+ 80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
+ 80013fe: 685b ldr r3, [r3, #4]
+ 8001400: 22f0 movs r2, #240 ; 0xf0
+ 8001402: 4393 bics r3, r2
+ 8001404: 0019 movs r1, r3
+ 8001406: 4b04 ldr r3, [pc, #16] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
+ 8001408: 687a ldr r2, [r7, #4]
+ 800140a: 430a orrs r2, r1
+ 800140c: 605a str r2, [r3, #4]
}
- 8001166: 46c0 nop ; (mov r8, r8)
- 8001168: 46bd mov sp, r7
- 800116a: b002 add sp, #8
- 800116c: bd80 pop {r7, pc}
- 800116e: 46c0 nop ; (mov r8, r8)
- 8001170: 40021000 .word 0x40021000
-
-08001174 <LL_RCC_SetAPB1Prescaler>:
+ 800140e: 46c0 nop ; (mov r8, r8)
+ 8001410: 46bd mov sp, r7
+ 8001412: b002 add sp, #8
+ 8001414: bd80 pop {r7, pc}
+ 8001416: 46c0 nop ; (mov r8, r8)
+ 8001418: 40021000 .word 0x40021000
+
+0800141c <LL_RCC_SetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
- 8001174: b580 push {r7, lr}
- 8001176: b082 sub sp, #8
- 8001178: af00 add r7, sp, #0
- 800117a: 6078 str r0, [r7, #4]
+ 800141c: b580 push {r7, lr}
+ 800141e: b082 sub sp, #8
+ 8001420: af00 add r7, sp, #0
+ 8001422: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
- 800117c: 4b06 ldr r3, [pc, #24] ; (8001198 <LL_RCC_SetAPB1Prescaler+0x24>)
- 800117e: 685b ldr r3, [r3, #4]
- 8001180: 4a06 ldr r2, [pc, #24] ; (800119c <LL_RCC_SetAPB1Prescaler+0x28>)
- 8001182: 4013 ands r3, r2
- 8001184: 0019 movs r1, r3
- 8001186: 4b04 ldr r3, [pc, #16] ; (8001198 <LL_RCC_SetAPB1Prescaler+0x24>)
- 8001188: 687a ldr r2, [r7, #4]
- 800118a: 430a orrs r2, r1
- 800118c: 605a str r2, [r3, #4]
+ 8001424: 4b06 ldr r3, [pc, #24] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
+ 8001426: 685b ldr r3, [r3, #4]
+ 8001428: 4a06 ldr r2, [pc, #24] ; (8001444 <LL_RCC_SetAPB1Prescaler+0x28>)
+ 800142a: 4013 ands r3, r2
+ 800142c: 0019 movs r1, r3
+ 800142e: 4b04 ldr r3, [pc, #16] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
+ 8001430: 687a ldr r2, [r7, #4]
+ 8001432: 430a orrs r2, r1
+ 8001434: 605a str r2, [r3, #4]
}
- 800118e: 46c0 nop ; (mov r8, r8)
- 8001190: 46bd mov sp, r7
- 8001192: b002 add sp, #8
- 8001194: bd80 pop {r7, pc}
- 8001196: 46c0 nop ; (mov r8, r8)
- 8001198: 40021000 .word 0x40021000
- 800119c: fffff8ff .word 0xfffff8ff
-
-080011a0 <LL_RCC_PLL_Enable>:
+ 8001436: 46c0 nop ; (mov r8, r8)
+ 8001438: 46bd mov sp, r7
+ 800143a: b002 add sp, #8
+ 800143c: bd80 pop {r7, pc}
+ 800143e: 46c0 nop ; (mov r8, r8)
+ 8001440: 40021000 .word 0x40021000
+ 8001444: fffff8ff .word 0xfffff8ff
+
+08001448 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
- 80011a0: b580 push {r7, lr}
- 80011a2: af00 add r7, sp, #0
+ 8001448: b580 push {r7, lr}
+ 800144a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
- 80011a4: 4b04 ldr r3, [pc, #16] ; (80011b8 <LL_RCC_PLL_Enable+0x18>)
- 80011a6: 681a ldr r2, [r3, #0]
- 80011a8: 4b03 ldr r3, [pc, #12] ; (80011b8 <LL_RCC_PLL_Enable+0x18>)
- 80011aa: 2180 movs r1, #128 ; 0x80
- 80011ac: 0449 lsls r1, r1, #17
- 80011ae: 430a orrs r2, r1
- 80011b0: 601a str r2, [r3, #0]
+ 800144c: 4b04 ldr r3, [pc, #16] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
+ 800144e: 681a ldr r2, [r3, #0]
+ 8001450: 4b03 ldr r3, [pc, #12] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
+ 8001452: 2180 movs r1, #128 ; 0x80
+ 8001454: 0449 lsls r1, r1, #17
+ 8001456: 430a orrs r2, r1
+ 8001458: 601a str r2, [r3, #0]
}
- 80011b2: 46c0 nop ; (mov r8, r8)
- 80011b4: 46bd mov sp, r7
- 80011b6: bd80 pop {r7, pc}
- 80011b8: 40021000 .word 0x40021000
+ 800145a: 46c0 nop ; (mov r8, r8)
+ 800145c: 46bd mov sp, r7
+ 800145e: bd80 pop {r7, pc}
+ 8001460: 40021000 .word 0x40021000
-080011bc <LL_RCC_PLL_IsReady>:
+08001464 <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
- 80011bc: b580 push {r7, lr}
- 80011be: af00 add r7, sp, #0
+ 8001464: b580 push {r7, lr}
+ 8001466: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
- 80011c0: 4b07 ldr r3, [pc, #28] ; (80011e0 <LL_RCC_PLL_IsReady+0x24>)
- 80011c2: 681a ldr r2, [r3, #0]
- 80011c4: 2380 movs r3, #128 ; 0x80
- 80011c6: 049b lsls r3, r3, #18
- 80011c8: 4013 ands r3, r2
- 80011ca: 22fe movs r2, #254 ; 0xfe
- 80011cc: 0612 lsls r2, r2, #24
- 80011ce: 4694 mov ip, r2
- 80011d0: 4463 add r3, ip
- 80011d2: 425a negs r2, r3
- 80011d4: 4153 adcs r3, r2
- 80011d6: b2db uxtb r3, r3
+ 8001468: 4b07 ldr r3, [pc, #28] ; (8001488 <LL_RCC_PLL_IsReady+0x24>)
+ 800146a: 681a ldr r2, [r3, #0]
+ 800146c: 2380 movs r3, #128 ; 0x80
+ 800146e: 049b lsls r3, r3, #18
+ 8001470: 4013 ands r3, r2
+ 8001472: 22fe movs r2, #254 ; 0xfe
+ 8001474: 0612 lsls r2, r2, #24
+ 8001476: 4694 mov ip, r2
+ 8001478: 4463 add r3, ip
+ 800147a: 425a negs r2, r3
+ 800147c: 4153 adcs r3, r2
+ 800147e: b2db uxtb r3, r3
}
- 80011d8: 0018 movs r0, r3
- 80011da: 46bd mov sp, r7
- 80011dc: bd80 pop {r7, pc}
- 80011de: 46c0 nop ; (mov r8, r8)
- 80011e0: 40021000 .word 0x40021000
+ 8001480: 0018 movs r0, r3
+ 8001482: 46bd mov sp, r7
+ 8001484: bd80 pop {r7, pc}
+ 8001486: 46c0 nop ; (mov r8, r8)
+ 8001488: 40021000 .word 0x40021000
-080011e4 <LL_RCC_PLL_ConfigDomain_SYS>:
+0800148c <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLL_MUL_15
* @arg @ref LL_RCC_PLL_MUL_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
{
- 80011e4: b580 push {r7, lr}
- 80011e6: b082 sub sp, #8
- 80011e8: af00 add r7, sp, #0
- 80011ea: 6078 str r0, [r7, #4]
- 80011ec: 6039 str r1, [r7, #0]
+ 800148c: b580 push {r7, lr}
+ 800148e: b082 sub sp, #8
+ 8001490: af00 add r7, sp, #0
+ 8001492: 6078 str r0, [r7, #4]
+ 8001494: 6039 str r1, [r7, #0]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
- 80011ee: 4b0e ldr r3, [pc, #56] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 80011f0: 685b ldr r3, [r3, #4]
- 80011f2: 4a0e ldr r2, [pc, #56] ; (800122c <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
- 80011f4: 4013 ands r3, r2
- 80011f6: 0019 movs r1, r3
- 80011f8: 687a ldr r2, [r7, #4]
- 80011fa: 2380 movs r3, #128 ; 0x80
- 80011fc: 025b lsls r3, r3, #9
- 80011fe: 401a ands r2, r3
- 8001200: 683b ldr r3, [r7, #0]
- 8001202: 431a orrs r2, r3
- 8001204: 4b08 ldr r3, [pc, #32] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 8001206: 430a orrs r2, r1
- 8001208: 605a str r2, [r3, #4]
+ 8001496: 4b0e ldr r3, [pc, #56] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 8001498: 685b ldr r3, [r3, #4]
+ 800149a: 4a0e ldr r2, [pc, #56] ; (80014d4 <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
+ 800149c: 4013 ands r3, r2
+ 800149e: 0019 movs r1, r3
+ 80014a0: 687a ldr r2, [r7, #4]
+ 80014a2: 2380 movs r3, #128 ; 0x80
+ 80014a4: 025b lsls r3, r3, #9
+ 80014a6: 401a ands r2, r3
+ 80014a8: 683b ldr r3, [r7, #0]
+ 80014aa: 431a orrs r2, r3
+ 80014ac: 4b08 ldr r3, [pc, #32] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 80014ae: 430a orrs r2, r1
+ 80014b0: 605a str r2, [r3, #4]
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
- 800120a: 4b07 ldr r3, [pc, #28] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 800120c: 6adb ldr r3, [r3, #44] ; 0x2c
- 800120e: 220f movs r2, #15
- 8001210: 4393 bics r3, r2
- 8001212: 0019 movs r1, r3
- 8001214: 687b ldr r3, [r7, #4]
- 8001216: 220f movs r2, #15
- 8001218: 401a ands r2, r3
- 800121a: 4b03 ldr r3, [pc, #12] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 800121c: 430a orrs r2, r1
- 800121e: 62da str r2, [r3, #44] ; 0x2c
+ 80014b2: 4b07 ldr r3, [pc, #28] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 80014b4: 6adb ldr r3, [r3, #44] ; 0x2c
+ 80014b6: 220f movs r2, #15
+ 80014b8: 4393 bics r3, r2
+ 80014ba: 0019 movs r1, r3
+ 80014bc: 687b ldr r3, [r7, #4]
+ 80014be: 220f movs r2, #15
+ 80014c0: 401a ands r2, r3
+ 80014c2: 4b03 ldr r3, [pc, #12] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 80014c4: 430a orrs r2, r1
+ 80014c6: 62da str r2, [r3, #44] ; 0x2c
}
- 8001220: 46c0 nop ; (mov r8, r8)
- 8001222: 46bd mov sp, r7
- 8001224: b002 add sp, #8
- 8001226: bd80 pop {r7, pc}
- 8001228: 40021000 .word 0x40021000
- 800122c: ffc2ffff .word 0xffc2ffff
-
-08001230 <LL_InitTick>:
+ 80014c8: 46c0 nop ; (mov r8, r8)
+ 80014ca: 46bd mov sp, r7
+ 80014cc: b002 add sp, #8
+ 80014ce: bd80 pop {r7, pc}
+ 80014d0: 40021000 .word 0x40021000
+ 80014d4: ffc2ffff .word 0xffc2ffff
+
+080014d8 <LL_InitTick>:
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
- 8001230: b580 push {r7, lr}
- 8001232: b082 sub sp, #8
- 8001234: af00 add r7, sp, #0
- 8001236: 6078 str r0, [r7, #4]
- 8001238: 6039 str r1, [r7, #0]
+ 80014d8: b580 push {r7, lr}
+ 80014da: b082 sub sp, #8
+ 80014dc: af00 add r7, sp, #0
+ 80014de: 6078 str r0, [r7, #4]
+ 80014e0: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- 800123a: 6839 ldr r1, [r7, #0]
- 800123c: 6878 ldr r0, [r7, #4]
- 800123e: f000 fa13 bl 8001668 <__udivsi3>
- 8001242: 0003 movs r3, r0
- 8001244: 001a movs r2, r3
- 8001246: 4b06 ldr r3, [pc, #24] ; (8001260 <LL_InitTick+0x30>)
- 8001248: 3a01 subs r2, #1
- 800124a: 605a str r2, [r3, #4]
+ 80014e2: 6839 ldr r1, [r7, #0]
+ 80014e4: 6878 ldr r0, [r7, #4]
+ 80014e6: f000 fa13 bl 8001910 <__udivsi3>
+ 80014ea: 0003 movs r3, r0
+ 80014ec: 001a movs r2, r3
+ 80014ee: 4b06 ldr r3, [pc, #24] ; (8001508 <LL_InitTick+0x30>)
+ 80014f0: 3a01 subs r2, #1
+ 80014f2: 605a str r2, [r3, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 800124c: 4b04 ldr r3, [pc, #16] ; (8001260 <LL_InitTick+0x30>)
- 800124e: 2200 movs r2, #0
- 8001250: 609a str r2, [r3, #8]
+ 80014f4: 4b04 ldr r3, [pc, #16] ; (8001508 <LL_InitTick+0x30>)
+ 80014f6: 2200 movs r2, #0
+ 80014f8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001252: 4b03 ldr r3, [pc, #12] ; (8001260 <LL_InitTick+0x30>)
- 8001254: 2205 movs r2, #5
- 8001256: 601a str r2, [r3, #0]
+ 80014fa: 4b03 ldr r3, [pc, #12] ; (8001508 <LL_InitTick+0x30>)
+ 80014fc: 2205 movs r2, #5
+ 80014fe: 601a str r2, [r3, #0]
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
- 8001258: 46c0 nop ; (mov r8, r8)
- 800125a: 46bd mov sp, r7
- 800125c: b002 add sp, #8
- 800125e: bd80 pop {r7, pc}
- 8001260: e000e010 .word 0xe000e010
+ 8001500: 46c0 nop ; (mov r8, r8)
+ 8001502: 46bd mov sp, r7
+ 8001504: b002 add sp, #8
+ 8001506: bd80 pop {r7, pc}
+ 8001508: e000e010 .word 0xe000e010
-08001264 <LL_FLASH_SetLatency>:
+0800150c <LL_FLASH_SetLatency>:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
- 8001264: b580 push {r7, lr}
- 8001266: b082 sub sp, #8
- 8001268: af00 add r7, sp, #0
- 800126a: 6078 str r0, [r7, #4]
+ 800150c: b580 push {r7, lr}
+ 800150e: b082 sub sp, #8
+ 8001510: af00 add r7, sp, #0
+ 8001512: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- 800126c: 4b06 ldr r3, [pc, #24] ; (8001288 <LL_FLASH_SetLatency+0x24>)
- 800126e: 681b ldr r3, [r3, #0]
- 8001270: 2201 movs r2, #1
- 8001272: 4393 bics r3, r2
- 8001274: 0019 movs r1, r3
- 8001276: 4b04 ldr r3, [pc, #16] ; (8001288 <LL_FLASH_SetLatency+0x24>)
- 8001278: 687a ldr r2, [r7, #4]
- 800127a: 430a orrs r2, r1
- 800127c: 601a str r2, [r3, #0]
+ 8001514: 4b06 ldr r3, [pc, #24] ; (8001530 <LL_FLASH_SetLatency+0x24>)
+ 8001516: 681b ldr r3, [r3, #0]
+ 8001518: 2201 movs r2, #1
+ 800151a: 4393 bics r3, r2
+ 800151c: 0019 movs r1, r3
+ 800151e: 4b04 ldr r3, [pc, #16] ; (8001530 <LL_FLASH_SetLatency+0x24>)
+ 8001520: 687a ldr r2, [r7, #4]
+ 8001522: 430a orrs r2, r1
+ 8001524: 601a str r2, [r3, #0]
}
- 800127e: 46c0 nop ; (mov r8, r8)
- 8001280: 46bd mov sp, r7
- 8001282: b002 add sp, #8
- 8001284: bd80 pop {r7, pc}
- 8001286: 46c0 nop ; (mov r8, r8)
- 8001288: 40022000 .word 0x40022000
-
-0800128c <LL_FLASH_GetLatency>:
+ 8001526: 46c0 nop ; (mov r8, r8)
+ 8001528: 46bd mov sp, r7
+ 800152a: b002 add sp, #8
+ 800152c: bd80 pop {r7, pc}
+ 800152e: 46c0 nop ; (mov r8, r8)
+ 8001530: 40022000 .word 0x40022000
+
+08001534 <LL_FLASH_GetLatency>:
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
- 800128c: b580 push {r7, lr}
- 800128e: af00 add r7, sp, #0
+ 8001534: b580 push {r7, lr}
+ 8001536: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
- 8001290: 4b03 ldr r3, [pc, #12] ; (80012a0 <LL_FLASH_GetLatency+0x14>)
- 8001292: 681b ldr r3, [r3, #0]
- 8001294: 2201 movs r2, #1
- 8001296: 4013 ands r3, r2
+ 8001538: 4b03 ldr r3, [pc, #12] ; (8001548 <LL_FLASH_GetLatency+0x14>)
+ 800153a: 681b ldr r3, [r3, #0]
+ 800153c: 2201 movs r2, #1
+ 800153e: 4013 ands r3, r2
}
- 8001298: 0018 movs r0, r3
- 800129a: 46bd mov sp, r7
- 800129c: bd80 pop {r7, pc}
- 800129e: 46c0 nop ; (mov r8, r8)
- 80012a0: 40022000 .word 0x40022000
+ 8001540: 0018 movs r0, r3
+ 8001542: 46bd mov sp, r7
+ 8001544: bd80 pop {r7, pc}
+ 8001546: 46c0 nop ; (mov r8, r8)
+ 8001548: 40022000 .word 0x40022000
-080012a4 <LL_Init1msTick>:
+0800154c <LL_Init1msTick>:
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
- 80012a4: b580 push {r7, lr}
- 80012a6: b082 sub sp, #8
- 80012a8: af00 add r7, sp, #0
- 80012aa: 6078 str r0, [r7, #4]
+ 800154c: b580 push {r7, lr}
+ 800154e: b082 sub sp, #8
+ 8001550: af00 add r7, sp, #0
+ 8001552: 6078 str r0, [r7, #4]
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
- 80012ac: 23fa movs r3, #250 ; 0xfa
- 80012ae: 009a lsls r2, r3, #2
- 80012b0: 687b ldr r3, [r7, #4]
- 80012b2: 0011 movs r1, r2
- 80012b4: 0018 movs r0, r3
- 80012b6: f7ff ffbb bl 8001230 <LL_InitTick>
+ 8001554: 23fa movs r3, #250 ; 0xfa
+ 8001556: 009a lsls r2, r3, #2
+ 8001558: 687b ldr r3, [r7, #4]
+ 800155a: 0011 movs r1, r2
+ 800155c: 0018 movs r0, r3
+ 800155e: f7ff ffbb bl 80014d8 <LL_InitTick>
}
- 80012ba: 46c0 nop ; (mov r8, r8)
- 80012bc: 46bd mov sp, r7
- 80012be: b002 add sp, #8
- 80012c0: bd80 pop {r7, pc}
+ 8001562: 46c0 nop ; (mov r8, r8)
+ 8001564: 46bd mov sp, r7
+ 8001566: b002 add sp, #8
+ 8001568: bd80 pop {r7, pc}
-080012c2 <LL_mDelay>:
+0800156a <LL_mDelay>:
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
- 80012c2: b580 push {r7, lr}
- 80012c4: b084 sub sp, #16
- 80012c6: af00 add r7, sp, #0
- 80012c8: 6078 str r0, [r7, #4]
+ 800156a: b580 push {r7, lr}
+ 800156c: b084 sub sp, #16
+ 800156e: af00 add r7, sp, #0
+ 8001570: 6078 str r0, [r7, #4]
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- 80012ca: 4b0e ldr r3, [pc, #56] ; (8001304 <LL_mDelay+0x42>)
- 80012cc: 681b ldr r3, [r3, #0]
- 80012ce: 60fb str r3, [r7, #12]
+ 8001572: 4b0e ldr r3, [pc, #56] ; (80015ac <LL_mDelay+0x42>)
+ 8001574: 681b ldr r3, [r3, #0]
+ 8001576: 60fb str r3, [r7, #12]
/* Add this code to indicate that local variable is not used */
((void)tmp);
- 80012d0: 68fb ldr r3, [r7, #12]
+ 8001578: 68fb ldr r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
- 80012d2: 687b ldr r3, [r7, #4]
- 80012d4: 3301 adds r3, #1
- 80012d6: d00c beq.n 80012f2 <LL_mDelay+0x30>
+ 800157a: 687b ldr r3, [r7, #4]
+ 800157c: 3301 adds r3, #1
+ 800157e: d00c beq.n 800159a <LL_mDelay+0x30>
{
Delay++;
- 80012d8: 687b ldr r3, [r7, #4]
- 80012da: 3301 adds r3, #1
- 80012dc: 607b str r3, [r7, #4]
+ 8001580: 687b ldr r3, [r7, #4]
+ 8001582: 3301 adds r3, #1
+ 8001584: 607b str r3, [r7, #4]
}
while (Delay)
- 80012de: e008 b.n 80012f2 <LL_mDelay+0x30>
+ 8001586: e008 b.n 800159a <LL_mDelay+0x30>
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- 80012e0: 4b08 ldr r3, [pc, #32] ; (8001304 <LL_mDelay+0x42>)
- 80012e2: 681a ldr r2, [r3, #0]
- 80012e4: 2380 movs r3, #128 ; 0x80
- 80012e6: 025b lsls r3, r3, #9
- 80012e8: 4013 ands r3, r2
- 80012ea: d002 beq.n 80012f2 <LL_mDelay+0x30>
+ 8001588: 4b08 ldr r3, [pc, #32] ; (80015ac <LL_mDelay+0x42>)
+ 800158a: 681a ldr r2, [r3, #0]
+ 800158c: 2380 movs r3, #128 ; 0x80
+ 800158e: 025b lsls r3, r3, #9
+ 8001590: 4013 ands r3, r2
+ 8001592: d002 beq.n 800159a <LL_mDelay+0x30>
{
Delay--;
- 80012ec: 687b ldr r3, [r7, #4]
- 80012ee: 3b01 subs r3, #1
- 80012f0: 607b str r3, [r7, #4]
+ 8001594: 687b ldr r3, [r7, #4]
+ 8001596: 3b01 subs r3, #1
+ 8001598: 607b str r3, [r7, #4]
while (Delay)
- 80012f2: 687b ldr r3, [r7, #4]
- 80012f4: 2b00 cmp r3, #0
- 80012f6: d1f3 bne.n 80012e0 <LL_mDelay+0x1e>
+ 800159a: 687b ldr r3, [r7, #4]
+ 800159c: 2b00 cmp r3, #0
+ 800159e: d1f3 bne.n 8001588 <LL_mDelay+0x1e>
}
}
}
- 80012f8: 46c0 nop ; (mov r8, r8)
- 80012fa: 46c0 nop ; (mov r8, r8)
- 80012fc: 46bd mov sp, r7
- 80012fe: b004 add sp, #16
- 8001300: bd80 pop {r7, pc}
- 8001302: 46c0 nop ; (mov r8, r8)
- 8001304: e000e010 .word 0xe000e010
-
-08001308 <LL_SetSystemCoreClock>:
+ 80015a0: 46c0 nop ; (mov r8, r8)
+ 80015a2: 46c0 nop ; (mov r8, r8)
+ 80015a4: 46bd mov sp, r7
+ 80015a6: b004 add sp, #16
+ 80015a8: bd80 pop {r7, pc}
+ 80015aa: 46c0 nop ; (mov r8, r8)
+ 80015ac: e000e010 .word 0xe000e010
+
+080015b0 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
- 8001308: b580 push {r7, lr}
- 800130a: b082 sub sp, #8
- 800130c: af00 add r7, sp, #0
- 800130e: 6078 str r0, [r7, #4]
+ 80015b0: b580 push {r7, lr}
+ 80015b2: b082 sub sp, #8
+ 80015b4: af00 add r7, sp, #0
+ 80015b6: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
- 8001310: 4b03 ldr r3, [pc, #12] ; (8001320 <LL_SetSystemCoreClock+0x18>)
- 8001312: 687a ldr r2, [r7, #4]
- 8001314: 601a str r2, [r3, #0]
+ 80015b8: 4b03 ldr r3, [pc, #12] ; (80015c8 <LL_SetSystemCoreClock+0x18>)
+ 80015ba: 687a ldr r2, [r7, #4]
+ 80015bc: 601a str r2, [r3, #0]
}
- 8001316: 46c0 nop ; (mov r8, r8)
- 8001318: 46bd mov sp, r7
- 800131a: b002 add sp, #8
- 800131c: bd80 pop {r7, pc}
- 800131e: 46c0 nop ; (mov r8, r8)
- 8001320: 20000000 .word 0x20000000
-
-08001324 <LL_PLL_ConfigSystemClock_HSI>:
+ 80015be: 46c0 nop ; (mov r8, r8)
+ 80015c0: 46bd mov sp, r7
+ 80015c2: b002 add sp, #8
+ 80015c4: bd80 pop {r7, pc}
+ 80015c6: 46c0 nop ; (mov r8, r8)
+ 80015c8: 20000000 .word 0x20000000
+
+080015cc <LL_PLL_ConfigSystemClock_HSI>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 8001324: b590 push {r4, r7, lr}
- 8001326: b085 sub sp, #20
- 8001328: af00 add r7, sp, #0
- 800132a: 6078 str r0, [r7, #4]
- 800132c: 6039 str r1, [r7, #0]
+ 80015cc: b590 push {r4, r7, lr}
+ 80015ce: b085 sub sp, #20
+ 80015d0: af00 add r7, sp, #0
+ 80015d2: 6078 str r0, [r7, #4]
+ 80015d4: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 800132e: 230f movs r3, #15
- 8001330: 18fb adds r3, r7, r3
- 8001332: 2201 movs r2, #1
- 8001334: 701a strb r2, [r3, #0]
+ 80015d6: 230f movs r3, #15
+ 80015d8: 18fb adds r3, r7, r3
+ 80015da: 2201 movs r2, #1
+ 80015dc: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 8001336: 2300 movs r3, #0
- 8001338: 60bb str r3, [r7, #8]
+ 80015de: 2300 movs r3, #0
+ 80015e0: 60bb str r3, [r7, #8]
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 800133a: f000 f8d4 bl 80014e6 <UTILS_PLL_IsBusy>
- 800133e: 0003 movs r3, r0
- 8001340: 2b01 cmp r3, #1
- 8001342: d128 bne.n 8001396 <LL_PLL_ConfigSystemClock_HSI+0x72>
+ 80015e2: f000 f8d4 bl 800178e <UTILS_PLL_IsBusy>
+ 80015e6: 0003 movs r3, r0
+ 80015e8: 2b01 cmp r3, #1
+ 80015ea: d128 bne.n 800163e <LL_PLL_ConfigSystemClock_HSI+0x72>
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
- 8001344: 687b ldr r3, [r7, #4]
- 8001346: 2201 movs r2, #1
- 8001348: 605a str r2, [r3, #4]
+ 80015ec: 687b ldr r3, [r7, #4]
+ 80015ee: 2201 movs r2, #1
+ 80015f0: 605a str r2, [r3, #4]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
- 800134a: 687b ldr r3, [r7, #4]
- 800134c: 4a17 ldr r2, [pc, #92] ; (80013ac <LL_PLL_ConfigSystemClock_HSI+0x88>)
- 800134e: 0019 movs r1, r3
- 8001350: 0010 movs r0, r2
- 8001352: f000 f8ab bl 80014ac <UTILS_GetPLLOutputFrequency>
- 8001356: 0003 movs r3, r0
- 8001358: 60bb str r3, [r7, #8]
+ 80015f2: 687b ldr r3, [r7, #4]
+ 80015f4: 4a17 ldr r2, [pc, #92] ; (8001654 <LL_PLL_ConfigSystemClock_HSI+0x88>)
+ 80015f6: 0019 movs r1, r3
+ 80015f8: 0010 movs r0, r2
+ 80015fa: f000 f8ab bl 8001754 <UTILS_GetPLLOutputFrequency>
+ 80015fe: 0003 movs r3, r0
+ 8001600: 60bb str r3, [r7, #8]
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
- 800135a: f7ff fec7 bl 80010ec <LL_RCC_HSI_IsReady>
- 800135e: 0003 movs r3, r0
- 8001360: 2b01 cmp r3, #1
- 8001362: d007 beq.n 8001374 <LL_PLL_ConfigSystemClock_HSI+0x50>
+ 8001602: f7ff fec7 bl 8001394 <LL_RCC_HSI_IsReady>
+ 8001606: 0003 movs r3, r0
+ 8001608: 2b01 cmp r3, #1
+ 800160a: d007 beq.n 800161c <LL_PLL_ConfigSystemClock_HSI+0x50>
{
LL_RCC_HSI_Enable();
- 8001364: f7ff feb4 bl 80010d0 <LL_RCC_HSI_Enable>
+ 800160c: f7ff feb4 bl 8001378 <LL_RCC_HSI_Enable>
while (LL_RCC_HSI_IsReady() != 1U)
- 8001368: 46c0 nop ; (mov r8, r8)
- 800136a: f7ff febf bl 80010ec <LL_RCC_HSI_IsReady>
- 800136e: 0003 movs r3, r0
- 8001370: 2b01 cmp r3, #1
- 8001372: d1fa bne.n 800136a <LL_PLL_ConfigSystemClock_HSI+0x46>
+ 8001610: 46c0 nop ; (mov r8, r8)
+ 8001612: f7ff febf bl 8001394 <LL_RCC_HSI_IsReady>
+ 8001616: 0003 movs r3, r0
+ 8001618: 2b01 cmp r3, #1
+ 800161a: d1fa bne.n 8001612 <LL_PLL_ConfigSystemClock_HSI+0x46>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
- 8001374: 687b ldr r3, [r7, #4]
- 8001376: 681b ldr r3, [r3, #0]
- 8001378: 0019 movs r1, r3
- 800137a: 2000 movs r0, #0
- 800137c: f7ff ff32 bl 80011e4 <LL_RCC_PLL_ConfigDomain_SYS>
+ 800161c: 687b ldr r3, [r7, #4]
+ 800161e: 681b ldr r3, [r3, #0]
+ 8001620: 0019 movs r1, r3
+ 8001622: 2000 movs r0, #0
+ 8001624: f7ff ff32 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 8001380: 230f movs r3, #15
- 8001382: 18fc adds r4, r7, r3
- 8001384: 683a ldr r2, [r7, #0]
- 8001386: 68bb ldr r3, [r7, #8]
- 8001388: 0011 movs r1, r2
- 800138a: 0018 movs r0, r3
- 800138c: f000 f8be bl 800150c <UTILS_EnablePLLAndSwitchSystem>
- 8001390: 0003 movs r3, r0
- 8001392: 7023 strb r3, [r4, #0]
- 8001394: e003 b.n 800139e <LL_PLL_ConfigSystemClock_HSI+0x7a>
+ 8001628: 230f movs r3, #15
+ 800162a: 18fc adds r4, r7, r3
+ 800162c: 683a ldr r2, [r7, #0]
+ 800162e: 68bb ldr r3, [r7, #8]
+ 8001630: 0011 movs r1, r2
+ 8001632: 0018 movs r0, r3
+ 8001634: f000 f8be bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
+ 8001638: 0003 movs r3, r0
+ 800163a: 7023 strb r3, [r4, #0]
+ 800163c: e003 b.n 8001646 <LL_PLL_ConfigSystemClock_HSI+0x7a>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 8001396: 230f movs r3, #15
- 8001398: 18fb adds r3, r7, r3
- 800139a: 2200 movs r2, #0
- 800139c: 701a strb r2, [r3, #0]
+ 800163e: 230f movs r3, #15
+ 8001640: 18fb adds r3, r7, r3
+ 8001642: 2200 movs r2, #0
+ 8001644: 701a strb r2, [r3, #0]
}
return status;
- 800139e: 230f movs r3, #15
- 80013a0: 18fb adds r3, r7, r3
- 80013a2: 781b ldrb r3, [r3, #0]
+ 8001646: 230f movs r3, #15
+ 8001648: 18fb adds r3, r7, r3
+ 800164a: 781b ldrb r3, [r3, #0]
}
- 80013a4: 0018 movs r0, r3
- 80013a6: 46bd mov sp, r7
- 80013a8: b005 add sp, #20
- 80013aa: bd90 pop {r4, r7, pc}
- 80013ac: 007a1200 .word 0x007a1200
+ 800164c: 0018 movs r0, r3
+ 800164e: 46bd mov sp, r7
+ 8001650: b005 add sp, #20
+ 8001652: bd90 pop {r4, r7, pc}
+ 8001654: 007a1200 .word 0x007a1200
-080013b0 <LL_PLL_ConfigSystemClock_HSE>:
+08001658 <LL_PLL_ConfigSystemClock_HSE>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 80013b0: b590 push {r4, r7, lr}
- 80013b2: b087 sub sp, #28
- 80013b4: af00 add r7, sp, #0
- 80013b6: 60f8 str r0, [r7, #12]
- 80013b8: 60b9 str r1, [r7, #8]
- 80013ba: 607a str r2, [r7, #4]
- 80013bc: 603b str r3, [r7, #0]
+ 8001658: b590 push {r4, r7, lr}
+ 800165a: b087 sub sp, #28
+ 800165c: af00 add r7, sp, #0
+ 800165e: 60f8 str r0, [r7, #12]
+ 8001660: 60b9 str r1, [r7, #8]
+ 8001662: 607a str r2, [r7, #4]
+ 8001664: 603b str r3, [r7, #0]
ErrorStatus status = SUCCESS;
- 80013be: 2317 movs r3, #23
- 80013c0: 18fb adds r3, r7, r3
- 80013c2: 2201 movs r2, #1
- 80013c4: 701a strb r2, [r3, #0]
+ 8001666: 2317 movs r3, #23
+ 8001668: 18fb adds r3, r7, r3
+ 800166a: 2201 movs r2, #1
+ 800166c: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 80013c6: 2300 movs r3, #0
- 80013c8: 613b str r3, [r7, #16]
+ 800166e: 2300 movs r3, #0
+ 8001670: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 80013ca: f000 f88c bl 80014e6 <UTILS_PLL_IsBusy>
- 80013ce: 0003 movs r3, r0
- 80013d0: 2b01 cmp r3, #1
- 80013d2: d132 bne.n 800143a <LL_PLL_ConfigSystemClock_HSE+0x8a>
+ 8001672: f000 f88c bl 800178e <UTILS_PLL_IsBusy>
+ 8001676: 0003 movs r3, r0
+ 8001678: 2b01 cmp r3, #1
+ 800167a: d132 bne.n 80016e2 <LL_PLL_ConfigSystemClock_HSE+0x8a>
#else
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
- 80013d4: 687a ldr r2, [r7, #4]
- 80013d6: 68fb ldr r3, [r7, #12]
- 80013d8: 0011 movs r1, r2
- 80013da: 0018 movs r0, r3
- 80013dc: f000 f866 bl 80014ac <UTILS_GetPLLOutputFrequency>
- 80013e0: 0003 movs r3, r0
- 80013e2: 613b str r3, [r7, #16]
+ 800167c: 687a ldr r2, [r7, #4]
+ 800167e: 68fb ldr r3, [r7, #12]
+ 8001680: 0011 movs r1, r2
+ 8001682: 0018 movs r0, r3
+ 8001684: f000 f866 bl 8001754 <UTILS_GetPLLOutputFrequency>
+ 8001688: 0003 movs r3, r0
+ 800168a: 613b str r3, [r7, #16]
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
- 80013e4: f7ff fe60 bl 80010a8 <LL_RCC_HSE_IsReady>
- 80013e8: 0003 movs r3, r0
- 80013ea: 2b01 cmp r3, #1
- 80013ec: d00f beq.n 800140e <LL_PLL_ConfigSystemClock_HSE+0x5e>
+ 800168c: f7ff fe60 bl 8001350 <LL_RCC_HSE_IsReady>
+ 8001690: 0003 movs r3, r0
+ 8001692: 2b01 cmp r3, #1
+ 8001694: d00f beq.n 80016b6 <LL_PLL_ConfigSystemClock_HSE+0x5e>
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- 80013ee: 68bb ldr r3, [r7, #8]
- 80013f0: 2b01 cmp r3, #1
- 80013f2: d102 bne.n 80013fa <LL_PLL_ConfigSystemClock_HSE+0x4a>
+ 8001696: 68bb ldr r3, [r7, #8]
+ 8001698: 2b01 cmp r3, #1
+ 800169a: d102 bne.n 80016a2 <LL_PLL_ConfigSystemClock_HSE+0x4a>
{
LL_RCC_HSE_EnableBypass();
- 80013f4: f7ff fe2c bl 8001050 <LL_RCC_HSE_EnableBypass>
- 80013f8: e001 b.n 80013fe <LL_PLL_ConfigSystemClock_HSE+0x4e>
+ 800169c: f7ff fe2c bl 80012f8 <LL_RCC_HSE_EnableBypass>
+ 80016a0: e001 b.n 80016a6 <LL_PLL_ConfigSystemClock_HSE+0x4e>
}
else
{
LL_RCC_HSE_DisableBypass();
- 80013fa: f7ff fe37 bl 800106c <LL_RCC_HSE_DisableBypass>
+ 80016a2: f7ff fe37 bl 8001314 <LL_RCC_HSE_DisableBypass>
}
/* Enable HSE */
LL_RCC_HSE_Enable();
- 80013fe: f7ff fe45 bl 800108c <LL_RCC_HSE_Enable>
+ 80016a6: f7ff fe45 bl 8001334 <LL_RCC_HSE_Enable>
while (LL_RCC_HSE_IsReady() != 1U)
- 8001402: 46c0 nop ; (mov r8, r8)
- 8001404: f7ff fe50 bl 80010a8 <LL_RCC_HSE_IsReady>
- 8001408: 0003 movs r3, r0
- 800140a: 2b01 cmp r3, #1
- 800140c: d1fa bne.n 8001404 <LL_PLL_ConfigSystemClock_HSE+0x54>
+ 80016aa: 46c0 nop ; (mov r8, r8)
+ 80016ac: f7ff fe50 bl 8001350 <LL_RCC_HSE_IsReady>
+ 80016b0: 0003 movs r3, r0
+ 80016b2: 2b01 cmp r3, #1
+ 80016b4: d1fa bne.n 80016ac <LL_PLL_ConfigSystemClock_HSE+0x54>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
- 800140e: 687b ldr r3, [r7, #4]
- 8001410: 685b ldr r3, [r3, #4]
- 8001412: 2280 movs r2, #128 ; 0x80
- 8001414: 0252 lsls r2, r2, #9
- 8001416: 431a orrs r2, r3
- 8001418: 687b ldr r3, [r7, #4]
- 800141a: 681b ldr r3, [r3, #0]
- 800141c: 0019 movs r1, r3
- 800141e: 0010 movs r0, r2
- 8001420: f7ff fee0 bl 80011e4 <LL_RCC_PLL_ConfigDomain_SYS>
+ 80016b6: 687b ldr r3, [r7, #4]
+ 80016b8: 685b ldr r3, [r3, #4]
+ 80016ba: 2280 movs r2, #128 ; 0x80
+ 80016bc: 0252 lsls r2, r2, #9
+ 80016be: 431a orrs r2, r3
+ 80016c0: 687b ldr r3, [r7, #4]
+ 80016c2: 681b ldr r3, [r3, #0]
+ 80016c4: 0019 movs r1, r3
+ 80016c6: 0010 movs r0, r2
+ 80016c8: f7ff fee0 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 8001424: 2317 movs r3, #23
- 8001426: 18fc adds r4, r7, r3
- 8001428: 683a ldr r2, [r7, #0]
- 800142a: 693b ldr r3, [r7, #16]
- 800142c: 0011 movs r1, r2
- 800142e: 0018 movs r0, r3
- 8001430: f000 f86c bl 800150c <UTILS_EnablePLLAndSwitchSystem>
- 8001434: 0003 movs r3, r0
- 8001436: 7023 strb r3, [r4, #0]
- 8001438: e003 b.n 8001442 <LL_PLL_ConfigSystemClock_HSE+0x92>
+ 80016cc: 2317 movs r3, #23
+ 80016ce: 18fc adds r4, r7, r3
+ 80016d0: 683a ldr r2, [r7, #0]
+ 80016d2: 693b ldr r3, [r7, #16]
+ 80016d4: 0011 movs r1, r2
+ 80016d6: 0018 movs r0, r3
+ 80016d8: f000 f86c bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
+ 80016dc: 0003 movs r3, r0
+ 80016de: 7023 strb r3, [r4, #0]
+ 80016e0: e003 b.n 80016ea <LL_PLL_ConfigSystemClock_HSE+0x92>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 800143a: 2317 movs r3, #23
- 800143c: 18fb adds r3, r7, r3
- 800143e: 2200 movs r2, #0
- 8001440: 701a strb r2, [r3, #0]
+ 80016e2: 2317 movs r3, #23
+ 80016e4: 18fb adds r3, r7, r3
+ 80016e6: 2200 movs r2, #0
+ 80016e8: 701a strb r2, [r3, #0]
}
return status;
- 8001442: 2317 movs r3, #23
- 8001444: 18fb adds r3, r7, r3
- 8001446: 781b ldrb r3, [r3, #0]
+ 80016ea: 2317 movs r3, #23
+ 80016ec: 18fb adds r3, r7, r3
+ 80016ee: 781b ldrb r3, [r3, #0]
}
- 8001448: 0018 movs r0, r3
- 800144a: 46bd mov sp, r7
- 800144c: b007 add sp, #28
- 800144e: bd90 pop {r4, r7, pc}
+ 80016f0: 0018 movs r0, r3
+ 80016f2: 46bd mov sp, r7
+ 80016f4: b007 add sp, #28
+ 80016f6: bd90 pop {r4, r7, pc}
-08001450 <UTILS_SetFlashLatency>:
+080016f8 <UTILS_SetFlashLatency>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
- 8001450: b580 push {r7, lr}
- 8001452: b084 sub sp, #16
- 8001454: af00 add r7, sp, #0
- 8001456: 6078 str r0, [r7, #4]
+ 80016f8: b580 push {r7, lr}
+ 80016fa: b084 sub sp, #16
+ 80016fc: af00 add r7, sp, #0
+ 80016fe: 6078 str r0, [r7, #4]
ErrorStatus status = SUCCESS;
- 8001458: 210f movs r1, #15
- 800145a: 187b adds r3, r7, r1
- 800145c: 2201 movs r2, #1
- 800145e: 701a strb r2, [r3, #0]
+ 8001700: 210f movs r1, #15
+ 8001702: 187b adds r3, r7, r1
+ 8001704: 2201 movs r2, #1
+ 8001706: 701a strb r2, [r3, #0]
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
- 8001460: 2300 movs r3, #0
- 8001462: 60bb str r3, [r7, #8]
+ 8001708: 2300 movs r3, #0
+ 800170a: 60bb str r3, [r7, #8]
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
- 8001464: 687b ldr r3, [r7, #4]
- 8001466: 2b00 cmp r3, #0
- 8001468: d103 bne.n 8001472 <UTILS_SetFlashLatency+0x22>
+ 800170c: 687b ldr r3, [r7, #4]
+ 800170e: 2b00 cmp r3, #0
+ 8001710: d103 bne.n 800171a <UTILS_SetFlashLatency+0x22>
{
status = ERROR;
- 800146a: 187b adds r3, r7, r1
- 800146c: 2200 movs r2, #0
- 800146e: 701a strb r2, [r3, #0]
- 8001470: e013 b.n 800149a <UTILS_SetFlashLatency+0x4a>
+ 8001712: 187b adds r3, r7, r1
+ 8001714: 2200 movs r2, #0
+ 8001716: 701a strb r2, [r3, #0]
+ 8001718: e013 b.n 8001742 <UTILS_SetFlashLatency+0x4a>
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
- 8001472: 687b ldr r3, [r7, #4]
- 8001474: 4a0c ldr r2, [pc, #48] ; (80014a8 <UTILS_SetFlashLatency+0x58>)
- 8001476: 4293 cmp r3, r2
- 8001478: d901 bls.n 800147e <UTILS_SetFlashLatency+0x2e>
+ 800171a: 687b ldr r3, [r7, #4]
+ 800171c: 4a0c ldr r2, [pc, #48] ; (8001750 <UTILS_SetFlashLatency+0x58>)
+ 800171e: 4293 cmp r3, r2
+ 8001720: d901 bls.n 8001726 <UTILS_SetFlashLatency+0x2e>
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
- 800147a: 2301 movs r3, #1
- 800147c: 60bb str r3, [r7, #8]
+ 8001722: 2301 movs r3, #1
+ 8001724: 60bb str r3, [r7, #8]
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
LL_FLASH_SetLatency(latency);
- 800147e: 68bb ldr r3, [r7, #8]
- 8001480: 0018 movs r0, r3
- 8001482: f7ff feef bl 8001264 <LL_FLASH_SetLatency>
+ 8001726: 68bb ldr r3, [r7, #8]
+ 8001728: 0018 movs r0, r3
+ 800172a: f7ff feef bl 800150c <LL_FLASH_SetLatency>
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
- 8001486: f7ff ff01 bl 800128c <LL_FLASH_GetLatency>
- 800148a: 0002 movs r2, r0
- 800148c: 68bb ldr r3, [r7, #8]
- 800148e: 4293 cmp r3, r2
- 8001490: d003 beq.n 800149a <UTILS_SetFlashLatency+0x4a>
+ 800172e: f7ff ff01 bl 8001534 <LL_FLASH_GetLatency>
+ 8001732: 0002 movs r2, r0
+ 8001734: 68bb ldr r3, [r7, #8]
+ 8001736: 4293 cmp r3, r2
+ 8001738: d003 beq.n 8001742 <UTILS_SetFlashLatency+0x4a>
{
status = ERROR;
- 8001492: 230f movs r3, #15
- 8001494: 18fb adds r3, r7, r3
- 8001496: 2200 movs r2, #0
- 8001498: 701a strb r2, [r3, #0]
+ 800173a: 230f movs r3, #15
+ 800173c: 18fb adds r3, r7, r3
+ 800173e: 2200 movs r2, #0
+ 8001740: 701a strb r2, [r3, #0]
}
}
return status;
- 800149a: 230f movs r3, #15
- 800149c: 18fb adds r3, r7, r3
- 800149e: 781b ldrb r3, [r3, #0]
+ 8001742: 230f movs r3, #15
+ 8001744: 18fb adds r3, r7, r3
+ 8001746: 781b ldrb r3, [r3, #0]
}
- 80014a0: 0018 movs r0, r3
- 80014a2: 46bd mov sp, r7
- 80014a4: b004 add sp, #16
- 80014a6: bd80 pop {r7, pc}
- 80014a8: 016e3600 .word 0x016e3600
+ 8001748: 0018 movs r0, r3
+ 800174a: 46bd mov sp, r7
+ 800174c: b004 add sp, #16
+ 800174e: bd80 pop {r7, pc}
+ 8001750: 016e3600 .word 0x016e3600
-080014ac <UTILS_GetPLLOutputFrequency>:
+08001754 <UTILS_GetPLLOutputFrequency>:
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
- 80014ac: b580 push {r7, lr}
- 80014ae: b084 sub sp, #16
- 80014b0: af00 add r7, sp, #0
- 80014b2: 6078 str r0, [r7, #4]
- 80014b4: 6039 str r1, [r7, #0]
+ 8001754: b580 push {r7, lr}
+ 8001756: b084 sub sp, #16
+ 8001758: af00 add r7, sp, #0
+ 800175a: 6078 str r0, [r7, #4]
+ 800175c: 6039 str r1, [r7, #0]
uint32_t pllfreq = 0U;
- 80014b6: 2300 movs r3, #0
- 80014b8: 60fb str r3, [r7, #12]
+ 800175e: 2300 movs r3, #0
+ 8001760: 60fb str r3, [r7, #12]
/* The application software must set correctly the PLL multiplication factor to
be in the range 16-48MHz */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
- 80014ba: 683b ldr r3, [r7, #0]
- 80014bc: 685b ldr r3, [r3, #4]
- 80014be: 3301 adds r3, #1
- 80014c0: 0019 movs r1, r3
- 80014c2: 6878 ldr r0, [r7, #4]
- 80014c4: f000 f8d0 bl 8001668 <__udivsi3>
- 80014c8: 0003 movs r3, r0
- 80014ca: 0019 movs r1, r3
- 80014cc: 683b ldr r3, [r7, #0]
- 80014ce: 681b ldr r3, [r3, #0]
- 80014d0: 0c9b lsrs r3, r3, #18
- 80014d2: 220f movs r2, #15
- 80014d4: 4013 ands r3, r2
- 80014d6: 3302 adds r3, #2
- 80014d8: 434b muls r3, r1
- 80014da: 60fb str r3, [r7, #12]
+ 8001762: 683b ldr r3, [r7, #0]
+ 8001764: 685b ldr r3, [r3, #4]
+ 8001766: 3301 adds r3, #1
+ 8001768: 0019 movs r1, r3
+ 800176a: 6878 ldr r0, [r7, #4]
+ 800176c: f000 f8d0 bl 8001910 <__udivsi3>
+ 8001770: 0003 movs r3, r0
+ 8001772: 0019 movs r1, r3
+ 8001774: 683b ldr r3, [r7, #0]
+ 8001776: 681b ldr r3, [r3, #0]
+ 8001778: 0c9b lsrs r3, r3, #18
+ 800177a: 220f movs r2, #15
+ 800177c: 4013 ands r3, r2
+ 800177e: 3302 adds r3, #2
+ 8001780: 434b muls r3, r1
+ 8001782: 60fb str r3, [r7, #12]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
- 80014dc: 68fb ldr r3, [r7, #12]
+ 8001784: 68fb ldr r3, [r7, #12]
}
- 80014de: 0018 movs r0, r3
- 80014e0: 46bd mov sp, r7
- 80014e2: b004 add sp, #16
- 80014e4: bd80 pop {r7, pc}
+ 8001786: 0018 movs r0, r3
+ 8001788: 46bd mov sp, r7
+ 800178a: b004 add sp, #16
+ 800178c: bd80 pop {r7, pc}
-080014e6 <UTILS_PLL_IsBusy>:
+0800178e <UTILS_PLL_IsBusy>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
- 80014e6: b580 push {r7, lr}
- 80014e8: b082 sub sp, #8
- 80014ea: af00 add r7, sp, #0
+ 800178e: b580 push {r7, lr}
+ 8001790: b082 sub sp, #8
+ 8001792: af00 add r7, sp, #0
ErrorStatus status = SUCCESS;
- 80014ec: 1dfb adds r3, r7, #7
- 80014ee: 2201 movs r2, #1
- 80014f0: 701a strb r2, [r3, #0]
+ 8001794: 1dfb adds r3, r7, #7
+ 8001796: 2201 movs r2, #1
+ 8001798: 701a strb r2, [r3, #0]
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
- 80014f2: f7ff fe63 bl 80011bc <LL_RCC_PLL_IsReady>
- 80014f6: 1e03 subs r3, r0, #0
- 80014f8: d002 beq.n 8001500 <UTILS_PLL_IsBusy+0x1a>
+ 800179a: f7ff fe63 bl 8001464 <LL_RCC_PLL_IsReady>
+ 800179e: 1e03 subs r3, r0, #0
+ 80017a0: d002 beq.n 80017a8 <UTILS_PLL_IsBusy+0x1a>
{
/* PLL configuration cannot be modified */
status = ERROR;
- 80014fa: 1dfb adds r3, r7, #7
- 80014fc: 2200 movs r2, #0
- 80014fe: 701a strb r2, [r3, #0]
+ 80017a2: 1dfb adds r3, r7, #7
+ 80017a4: 2200 movs r2, #0
+ 80017a6: 701a strb r2, [r3, #0]
}
return status;
- 8001500: 1dfb adds r3, r7, #7
- 8001502: 781b ldrb r3, [r3, #0]
+ 80017a8: 1dfb adds r3, r7, #7
+ 80017aa: 781b ldrb r3, [r3, #0]
}
- 8001504: 0018 movs r0, r3
- 8001506: 46bd mov sp, r7
- 8001508: b002 add sp, #8
- 800150a: bd80 pop {r7, pc}
+ 80017ac: 0018 movs r0, r3
+ 80017ae: 46bd mov sp, r7
+ 80017b0: b002 add sp, #8
+ 80017b2: bd80 pop {r7, pc}
-0800150c <UTILS_EnablePLLAndSwitchSystem>:
+080017b4 <UTILS_EnablePLLAndSwitchSystem>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 800150c: b590 push {r4, r7, lr}
- 800150e: b085 sub sp, #20
- 8001510: af00 add r7, sp, #0
- 8001512: 6078 str r0, [r7, #4]
- 8001514: 6039 str r1, [r7, #0]
+ 80017b4: b590 push {r4, r7, lr}
+ 80017b6: b085 sub sp, #20
+ 80017b8: af00 add r7, sp, #0
+ 80017ba: 6078 str r0, [r7, #4]
+ 80017bc: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 8001516: 200f movs r0, #15
- 8001518: 183b adds r3, r7, r0
- 800151a: 2201 movs r2, #1
- 800151c: 701a strb r2, [r3, #0]
+ 80017be: 200f movs r0, #15
+ 80017c0: 183b adds r3, r7, r0
+ 80017c2: 2201 movs r2, #1
+ 80017c4: 701a strb r2, [r3, #0]
uint32_t sysclk_frequency_current = 0U;
- 800151e: 2300 movs r3, #0
- 8001520: 60bb str r3, [r7, #8]
+ 80017c6: 2300 movs r3, #0
+ 80017c8: 60bb str r3, [r7, #8]
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
- 8001522: 4b2e ldr r3, [pc, #184] ; (80015dc <UTILS_EnablePLLAndSwitchSystem+0xd0>)
- 8001524: 681a ldr r2, [r3, #0]
- 8001526: 683b ldr r3, [r7, #0]
- 8001528: 681b ldr r3, [r3, #0]
- 800152a: 091b lsrs r3, r3, #4
- 800152c: 210f movs r1, #15
- 800152e: 400b ands r3, r1
- 8001530: 492b ldr r1, [pc, #172] ; (80015e0 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 8001532: 5ccb ldrb r3, [r1, r3]
- 8001534: 409a lsls r2, r3
- 8001536: 0013 movs r3, r2
- 8001538: 60bb str r3, [r7, #8]
+ 80017ca: 4b2e ldr r3, [pc, #184] ; (8001884 <UTILS_EnablePLLAndSwitchSystem+0xd0>)
+ 80017cc: 681a ldr r2, [r3, #0]
+ 80017ce: 683b ldr r3, [r7, #0]
+ 80017d0: 681b ldr r3, [r3, #0]
+ 80017d2: 091b lsrs r3, r3, #4
+ 80017d4: 210f movs r1, #15
+ 80017d6: 400b ands r3, r1
+ 80017d8: 492b ldr r1, [pc, #172] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 80017da: 5ccb ldrb r3, [r1, r3]
+ 80017dc: 409a lsls r2, r3
+ 80017de: 0013 movs r3, r2
+ 80017e0: 60bb str r3, [r7, #8]
/* Increasing the number of wait states because of higher CPU frequency */
if (sysclk_frequency_current < SYSCLK_Frequency)
- 800153a: 68ba ldr r2, [r7, #8]
- 800153c: 687b ldr r3, [r7, #4]
- 800153e: 429a cmp r2, r3
- 8001540: d206 bcs.n 8001550 <UTILS_EnablePLLAndSwitchSystem+0x44>
+ 80017e2: 68ba ldr r2, [r7, #8]
+ 80017e4: 687b ldr r3, [r7, #4]
+ 80017e6: 429a cmp r2, r3
+ 80017e8: d206 bcs.n 80017f8 <UTILS_EnablePLLAndSwitchSystem+0x44>
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 8001542: 183c adds r4, r7, r0
- 8001544: 687b ldr r3, [r7, #4]
- 8001546: 0018 movs r0, r3
- 8001548: f7ff ff82 bl 8001450 <UTILS_SetFlashLatency>
- 800154c: 0003 movs r3, r0
- 800154e: 7023 strb r3, [r4, #0]
+ 80017ea: 183c adds r4, r7, r0
+ 80017ec: 687b ldr r3, [r7, #4]
+ 80017ee: 0018 movs r0, r3
+ 80017f0: f7ff ff82 bl 80016f8 <UTILS_SetFlashLatency>
+ 80017f4: 0003 movs r3, r0
+ 80017f6: 7023 strb r3, [r4, #0]
}
/* Update system clock configuration */
if (status == SUCCESS)
- 8001550: 230f movs r3, #15
- 8001552: 18fb adds r3, r7, r3
- 8001554: 781b ldrb r3, [r3, #0]
- 8001556: 2b01 cmp r3, #1
- 8001558: d11a bne.n 8001590 <UTILS_EnablePLLAndSwitchSystem+0x84>
+ 80017f8: 230f movs r3, #15
+ 80017fa: 18fb adds r3, r7, r3
+ 80017fc: 781b ldrb r3, [r3, #0]
+ 80017fe: 2b01 cmp r3, #1
+ 8001800: d11a bne.n 8001838 <UTILS_EnablePLLAndSwitchSystem+0x84>
{
/* Enable PLL */
LL_RCC_PLL_Enable();
- 800155a: f7ff fe21 bl 80011a0 <LL_RCC_PLL_Enable>
+ 8001802: f7ff fe21 bl 8001448 <LL_RCC_PLL_Enable>
while (LL_RCC_PLL_IsReady() != 1U)
- 800155e: 46c0 nop ; (mov r8, r8)
- 8001560: f7ff fe2c bl 80011bc <LL_RCC_PLL_IsReady>
- 8001564: 0003 movs r3, r0
- 8001566: 2b01 cmp r3, #1
- 8001568: d1fa bne.n 8001560 <UTILS_EnablePLLAndSwitchSystem+0x54>
+ 8001806: 46c0 nop ; (mov r8, r8)
+ 8001808: f7ff fe2c bl 8001464 <LL_RCC_PLL_IsReady>
+ 800180c: 0003 movs r3, r0
+ 800180e: 2b01 cmp r3, #1
+ 8001810: d1fa bne.n 8001808 <UTILS_EnablePLLAndSwitchSystem+0x54>
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- 800156a: 683b ldr r3, [r7, #0]
- 800156c: 681b ldr r3, [r3, #0]
- 800156e: 0018 movs r0, r3
- 8001570: f7ff fdec bl 800114c <LL_RCC_SetAHBPrescaler>
+ 8001812: 683b ldr r3, [r7, #0]
+ 8001814: 681b ldr r3, [r3, #0]
+ 8001816: 0018 movs r0, r3
+ 8001818: f7ff fdec bl 80013f4 <LL_RCC_SetAHBPrescaler>
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 8001574: 2002 movs r0, #2
- 8001576: f7ff fdc9 bl 800110c <LL_RCC_SetSysClkSource>
+ 800181c: 2002 movs r0, #2
+ 800181e: f7ff fdc9 bl 80013b4 <LL_RCC_SetSysClkSource>
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 800157a: 46c0 nop ; (mov r8, r8)
- 800157c: f7ff fdda bl 8001134 <LL_RCC_GetSysClkSource>
- 8001580: 0003 movs r3, r0
- 8001582: 2b08 cmp r3, #8
- 8001584: d1fa bne.n 800157c <UTILS_EnablePLLAndSwitchSystem+0x70>
+ 8001822: 46c0 nop ; (mov r8, r8)
+ 8001824: f7ff fdda bl 80013dc <LL_RCC_GetSysClkSource>
+ 8001828: 0003 movs r3, r0
+ 800182a: 2b08 cmp r3, #8
+ 800182c: d1fa bne.n 8001824 <UTILS_EnablePLLAndSwitchSystem+0x70>
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- 8001586: 683b ldr r3, [r7, #0]
- 8001588: 685b ldr r3, [r3, #4]
- 800158a: 0018 movs r0, r3
- 800158c: f7ff fdf2 bl 8001174 <LL_RCC_SetAPB1Prescaler>
+ 800182e: 683b ldr r3, [r7, #0]
+ 8001830: 685b ldr r3, [r3, #4]
+ 8001832: 0018 movs r0, r3
+ 8001834: f7ff fdf2 bl 800141c <LL_RCC_SetAPB1Prescaler>
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (sysclk_frequency_current > SYSCLK_Frequency)
- 8001590: 68ba ldr r2, [r7, #8]
- 8001592: 687b ldr r3, [r7, #4]
- 8001594: 429a cmp r2, r3
- 8001596: d907 bls.n 80015a8 <UTILS_EnablePLLAndSwitchSystem+0x9c>
+ 8001838: 68ba ldr r2, [r7, #8]
+ 800183a: 687b ldr r3, [r7, #4]
+ 800183c: 429a cmp r2, r3
+ 800183e: d907 bls.n 8001850 <UTILS_EnablePLLAndSwitchSystem+0x9c>
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 8001598: 230f movs r3, #15
- 800159a: 18fc adds r4, r7, r3
- 800159c: 687b ldr r3, [r7, #4]
- 800159e: 0018 movs r0, r3
- 80015a0: f7ff ff56 bl 8001450 <UTILS_SetFlashLatency>
- 80015a4: 0003 movs r3, r0
- 80015a6: 7023 strb r3, [r4, #0]
+ 8001840: 230f movs r3, #15
+ 8001842: 18fc adds r4, r7, r3
+ 8001844: 687b ldr r3, [r7, #4]
+ 8001846: 0018 movs r0, r3
+ 8001848: f7ff ff56 bl 80016f8 <UTILS_SetFlashLatency>
+ 800184c: 0003 movs r3, r0
+ 800184e: 7023 strb r3, [r4, #0]
}
/* Update SystemCoreClock variable */
if (status == SUCCESS)
- 80015a8: 230f movs r3, #15
- 80015aa: 18fb adds r3, r7, r3
- 80015ac: 781b ldrb r3, [r3, #0]
- 80015ae: 2b01 cmp r3, #1
- 80015b0: d10c bne.n 80015cc <UTILS_EnablePLLAndSwitchSystem+0xc0>
+ 8001850: 230f movs r3, #15
+ 8001852: 18fb adds r3, r7, r3
+ 8001854: 781b ldrb r3, [r3, #0]
+ 8001856: 2b01 cmp r3, #1
+ 8001858: d10c bne.n 8001874 <UTILS_EnablePLLAndSwitchSystem+0xc0>
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- 80015b2: 683b ldr r3, [r7, #0]
- 80015b4: 681b ldr r3, [r3, #0]
- 80015b6: 091b lsrs r3, r3, #4
- 80015b8: 220f movs r2, #15
- 80015ba: 4013 ands r3, r2
- 80015bc: 4a08 ldr r2, [pc, #32] ; (80015e0 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 80015be: 5cd3 ldrb r3, [r2, r3]
- 80015c0: 001a movs r2, r3
- 80015c2: 687b ldr r3, [r7, #4]
- 80015c4: 40d3 lsrs r3, r2
- 80015c6: 0018 movs r0, r3
- 80015c8: f7ff fe9e bl 8001308 <LL_SetSystemCoreClock>
+ 800185a: 683b ldr r3, [r7, #0]
+ 800185c: 681b ldr r3, [r3, #0]
+ 800185e: 091b lsrs r3, r3, #4
+ 8001860: 220f movs r2, #15
+ 8001862: 4013 ands r3, r2
+ 8001864: 4a08 ldr r2, [pc, #32] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 8001866: 5cd3 ldrb r3, [r2, r3]
+ 8001868: 001a movs r2, r3
+ 800186a: 687b ldr r3, [r7, #4]
+ 800186c: 40d3 lsrs r3, r2
+ 800186e: 0018 movs r0, r3
+ 8001870: f7ff fe9e bl 80015b0 <LL_SetSystemCoreClock>
}
return status;
- 80015cc: 230f movs r3, #15
- 80015ce: 18fb adds r3, r7, r3
- 80015d0: 781b ldrb r3, [r3, #0]
+ 8001874: 230f movs r3, #15
+ 8001876: 18fb adds r3, r7, r3
+ 8001878: 781b ldrb r3, [r3, #0]
}
- 80015d2: 0018 movs r0, r3
- 80015d4: 46bd mov sp, r7
- 80015d6: b005 add sp, #20
- 80015d8: bd90 pop {r4, r7, pc}
- 80015da: 46c0 nop ; (mov r8, r8)
- 80015dc: 20000000 .word 0x20000000
- 80015e0: 080019a4 .word 0x080019a4
-
-080015e4 <__sinit>:
+ 800187a: 0018 movs r0, r3
+ 800187c: 46bd mov sp, r7
+ 800187e: b005 add sp, #20
+ 8001880: bd90 pop {r4, r7, pc}
+ 8001882: 46c0 nop ; (mov r8, r8)
+ 8001884: 20000000 .word 0x20000000
+ 8001888: 08001c4c .word 0x08001c4c
+
+0800188c <__sinit>:
#include <stdbool.h>
int __errno = 0;
void *_impure_ptr = NULL;
void __sinit(void) {
- 80015e4: b580 push {r7, lr}
- 80015e6: af00 add r7, sp, #0
+ 800188c: b580 push {r7, lr}
+ 800188e: af00 add r7, sp, #0
}
- 80015e8: 46c0 nop ; (mov r8, r8)
- 80015ea: 46bd mov sp, r7
- 80015ec: bd80 pop {r7, pc}
+ 8001890: 46c0 nop ; (mov r8, r8)
+ 8001892: 46bd mov sp, r7
+ 8001894: bd80 pop {r7, pc}
-080015ee <memset>:
+08001896 <memset>:
void *memset(void *s, int c, size_t n) {
- 80015ee: b580 push {r7, lr}
- 80015f0: b086 sub sp, #24
- 80015f2: af00 add r7, sp, #0
- 80015f4: 60f8 str r0, [r7, #12]
- 80015f6: 60b9 str r1, [r7, #8]
- 80015f8: 607a str r2, [r7, #4]
+ 8001896: b580 push {r7, lr}
+ 8001898: b086 sub sp, #24
+ 800189a: af00 add r7, sp, #0
+ 800189c: 60f8 str r0, [r7, #12]
+ 800189e: 60b9 str r1, [r7, #8]
+ 80018a0: 607a str r2, [r7, #4]
char *end = (char *)s + n;
- 80015fa: 68fa ldr r2, [r7, #12]
- 80015fc: 687b ldr r3, [r7, #4]
- 80015fe: 18d3 adds r3, r2, r3
- 8001600: 613b str r3, [r7, #16]
+ 80018a2: 68fa ldr r2, [r7, #12]
+ 80018a4: 687b ldr r3, [r7, #4]
+ 80018a6: 18d3 adds r3, r2, r3
+ 80018a8: 613b str r3, [r7, #16]
for (char *p = (char *)s; p < end; p++)
- 8001602: 68fb ldr r3, [r7, #12]
- 8001604: 617b str r3, [r7, #20]
- 8001606: e006 b.n 8001616 <memset+0x28>
+ 80018aa: 68fb ldr r3, [r7, #12]
+ 80018ac: 617b str r3, [r7, #20]
+ 80018ae: e006 b.n 80018be <memset+0x28>
*p = (char)c;
- 8001608: 68bb ldr r3, [r7, #8]
- 800160a: b2da uxtb r2, r3
- 800160c: 697b ldr r3, [r7, #20]
- 800160e: 701a strb r2, [r3, #0]
+ 80018b0: 68bb ldr r3, [r7, #8]
+ 80018b2: b2da uxtb r2, r3
+ 80018b4: 697b ldr r3, [r7, #20]
+ 80018b6: 701a strb r2, [r3, #0]
for (char *p = (char *)s; p < end; p++)
- 8001610: 697b ldr r3, [r7, #20]
- 8001612: 3301 adds r3, #1
- 8001614: 617b str r3, [r7, #20]
- 8001616: 697a ldr r2, [r7, #20]
- 8001618: 693b ldr r3, [r7, #16]
- 800161a: 429a cmp r2, r3
- 800161c: d3f4 bcc.n 8001608 <memset+0x1a>
+ 80018b8: 697b ldr r3, [r7, #20]
+ 80018ba: 3301 adds r3, #1
+ 80018bc: 617b str r3, [r7, #20]
+ 80018be: 697a ldr r2, [r7, #20]
+ 80018c0: 693b ldr r3, [r7, #16]
+ 80018c2: 429a cmp r2, r3
+ 80018c4: d3f4 bcc.n 80018b0 <memset+0x1a>
return s;
- 800161e: 68fb ldr r3, [r7, #12]
+ 80018c6: 68fb ldr r3, [r7, #12]
}
- 8001620: 0018 movs r0, r3
- 8001622: 46bd mov sp, r7
- 8001624: b006 add sp, #24
- 8001626: bd80 pop {r7, pc}
+ 80018c8: 0018 movs r0, r3
+ 80018ca: 46bd mov sp, r7
+ 80018cc: b006 add sp, #24
+ 80018ce: bd80 pop {r7, pc}
-08001628 <strlen>:
+080018d0 <strlen>:
size_t strlen(const char *s) {
- 8001628: b580 push {r7, lr}
- 800162a: b084 sub sp, #16
- 800162c: af00 add r7, sp, #0
- 800162e: 6078 str r0, [r7, #4]
+ 80018d0: b580 push {r7, lr}
+ 80018d2: b084 sub sp, #16
+ 80018d4: af00 add r7, sp, #0
+ 80018d6: 6078 str r0, [r7, #4]
const char *start = s;
- 8001630: 687b ldr r3, [r7, #4]
- 8001632: 60fb str r3, [r7, #12]
+ 80018d8: 687b ldr r3, [r7, #4]
+ 80018da: 60fb str r3, [r7, #12]
while (*s++);
- 8001634: 46c0 nop ; (mov r8, r8)
- 8001636: 687b ldr r3, [r7, #4]
- 8001638: 1c5a adds r2, r3, #1
- 800163a: 607a str r2, [r7, #4]
- 800163c: 781b ldrb r3, [r3, #0]
- 800163e: 2b00 cmp r3, #0
- 8001640: d1f9 bne.n 8001636 <strlen+0xe>
+ 80018dc: 46c0 nop ; (mov r8, r8)
+ 80018de: 687b ldr r3, [r7, #4]
+ 80018e0: 1c5a adds r2, r3, #1
+ 80018e2: 607a str r2, [r7, #4]
+ 80018e4: 781b ldrb r3, [r3, #0]
+ 80018e6: 2b00 cmp r3, #0
+ 80018e8: d1f9 bne.n 80018de <strlen+0xe>
return s - start - 1;
- 8001642: 687a ldr r2, [r7, #4]
- 8001644: 68fb ldr r3, [r7, #12]
- 8001646: 1ad3 subs r3, r2, r3
- 8001648: 3b01 subs r3, #1
+ 80018ea: 687a ldr r2, [r7, #4]
+ 80018ec: 68fb ldr r3, [r7, #12]
+ 80018ee: 1ad3 subs r3, r2, r3
+ 80018f0: 3b01 subs r3, #1
}
- 800164a: 0018 movs r0, r3
- 800164c: 46bd mov sp, r7
- 800164e: b004 add sp, #16
- 8001650: bd80 pop {r7, pc}
+ 80018f2: 0018 movs r0, r3
+ 80018f4: 46bd mov sp, r7
+ 80018f6: b004 add sp, #16
+ 80018f8: bd80 pop {r7, pc}
-08001652 <__assert_func>:
+080018fa <__assert_func>:
void __assert_func(bool value) {
- 8001652: b580 push {r7, lr}
- 8001654: b082 sub sp, #8
- 8001656: af00 add r7, sp, #0
- 8001658: 0002 movs r2, r0
- 800165a: 1dfb adds r3, r7, #7
- 800165c: 701a strb r2, [r3, #0]
+ 80018fa: b580 push {r7, lr}
+ 80018fc: b082 sub sp, #8
+ 80018fe: af00 add r7, sp, #0
+ 8001900: 0002 movs r2, r0
+ 8001902: 1dfb adds r3, r7, #7
+ 8001904: 701a strb r2, [r3, #0]
}
- 800165e: 46c0 nop ; (mov r8, r8)
- 8001660: 46bd mov sp, r7
- 8001662: b002 add sp, #8
- 8001664: bd80 pop {r7, pc}
+ 8001906: 46c0 nop ; (mov r8, r8)
+ 8001908: 46bd mov sp, r7
+ 800190a: b002 add sp, #8
+ 800190c: bd80 pop {r7, pc}
...
-08001668 <__udivsi3>:
- 8001668: 2200 movs r2, #0
- 800166a: 0843 lsrs r3, r0, #1
- 800166c: 428b cmp r3, r1
- 800166e: d374 bcc.n 800175a <__udivsi3+0xf2>
- 8001670: 0903 lsrs r3, r0, #4
- 8001672: 428b cmp r3, r1
- 8001674: d35f bcc.n 8001736 <__udivsi3+0xce>
- 8001676: 0a03 lsrs r3, r0, #8
- 8001678: 428b cmp r3, r1
- 800167a: d344 bcc.n 8001706 <__udivsi3+0x9e>
- 800167c: 0b03 lsrs r3, r0, #12
- 800167e: 428b cmp r3, r1
- 8001680: d328 bcc.n 80016d4 <__udivsi3+0x6c>
- 8001682: 0c03 lsrs r3, r0, #16
- 8001684: 428b cmp r3, r1
- 8001686: d30d bcc.n 80016a4 <__udivsi3+0x3c>
- 8001688: 22ff movs r2, #255 ; 0xff
- 800168a: 0209 lsls r1, r1, #8
- 800168c: ba12 rev r2, r2
- 800168e: 0c03 lsrs r3, r0, #16
- 8001690: 428b cmp r3, r1
- 8001692: d302 bcc.n 800169a <__udivsi3+0x32>
- 8001694: 1212 asrs r2, r2, #8
- 8001696: 0209 lsls r1, r1, #8
- 8001698: d065 beq.n 8001766 <__udivsi3+0xfe>
- 800169a: 0b03 lsrs r3, r0, #12
- 800169c: 428b cmp r3, r1
- 800169e: d319 bcc.n 80016d4 <__udivsi3+0x6c>
- 80016a0: e000 b.n 80016a4 <__udivsi3+0x3c>
- 80016a2: 0a09 lsrs r1, r1, #8
- 80016a4: 0bc3 lsrs r3, r0, #15
- 80016a6: 428b cmp r3, r1
- 80016a8: d301 bcc.n 80016ae <__udivsi3+0x46>
- 80016aa: 03cb lsls r3, r1, #15
- 80016ac: 1ac0 subs r0, r0, r3
- 80016ae: 4152 adcs r2, r2
- 80016b0: 0b83 lsrs r3, r0, #14
- 80016b2: 428b cmp r3, r1
- 80016b4: d301 bcc.n 80016ba <__udivsi3+0x52>
- 80016b6: 038b lsls r3, r1, #14
- 80016b8: 1ac0 subs r0, r0, r3
- 80016ba: 4152 adcs r2, r2
- 80016bc: 0b43 lsrs r3, r0, #13
- 80016be: 428b cmp r3, r1
- 80016c0: d301 bcc.n 80016c6 <__udivsi3+0x5e>
- 80016c2: 034b lsls r3, r1, #13
- 80016c4: 1ac0 subs r0, r0, r3
- 80016c6: 4152 adcs r2, r2
- 80016c8: 0b03 lsrs r3, r0, #12
- 80016ca: 428b cmp r3, r1
- 80016cc: d301 bcc.n 80016d2 <__udivsi3+0x6a>
- 80016ce: 030b lsls r3, r1, #12
- 80016d0: 1ac0 subs r0, r0, r3
- 80016d2: 4152 adcs r2, r2
- 80016d4: 0ac3 lsrs r3, r0, #11
- 80016d6: 428b cmp r3, r1
- 80016d8: d301 bcc.n 80016de <__udivsi3+0x76>
- 80016da: 02cb lsls r3, r1, #11
- 80016dc: 1ac0 subs r0, r0, r3
- 80016de: 4152 adcs r2, r2
- 80016e0: 0a83 lsrs r3, r0, #10
- 80016e2: 428b cmp r3, r1
- 80016e4: d301 bcc.n 80016ea <__udivsi3+0x82>
- 80016e6: 028b lsls r3, r1, #10
- 80016e8: 1ac0 subs r0, r0, r3
- 80016ea: 4152 adcs r2, r2
- 80016ec: 0a43 lsrs r3, r0, #9
- 80016ee: 428b cmp r3, r1
- 80016f0: d301 bcc.n 80016f6 <__udivsi3+0x8e>
- 80016f2: 024b lsls r3, r1, #9
- 80016f4: 1ac0 subs r0, r0, r3
- 80016f6: 4152 adcs r2, r2
- 80016f8: 0a03 lsrs r3, r0, #8
- 80016fa: 428b cmp r3, r1
- 80016fc: d301 bcc.n 8001702 <__udivsi3+0x9a>
- 80016fe: 020b lsls r3, r1, #8
- 8001700: 1ac0 subs r0, r0, r3
- 8001702: 4152 adcs r2, r2
- 8001704: d2cd bcs.n 80016a2 <__udivsi3+0x3a>
- 8001706: 09c3 lsrs r3, r0, #7
- 8001708: 428b cmp r3, r1
- 800170a: d301 bcc.n 8001710 <__udivsi3+0xa8>
- 800170c: 01cb lsls r3, r1, #7
- 800170e: 1ac0 subs r0, r0, r3
- 8001710: 4152 adcs r2, r2
- 8001712: 0983 lsrs r3, r0, #6
- 8001714: 428b cmp r3, r1
- 8001716: d301 bcc.n 800171c <__udivsi3+0xb4>
- 8001718: 018b lsls r3, r1, #6
- 800171a: 1ac0 subs r0, r0, r3
- 800171c: 4152 adcs r2, r2
- 800171e: 0943 lsrs r3, r0, #5
- 8001720: 428b cmp r3, r1
- 8001722: d301 bcc.n 8001728 <__udivsi3+0xc0>
- 8001724: 014b lsls r3, r1, #5
- 8001726: 1ac0 subs r0, r0, r3
- 8001728: 4152 adcs r2, r2
- 800172a: 0903 lsrs r3, r0, #4
- 800172c: 428b cmp r3, r1
- 800172e: d301 bcc.n 8001734 <__udivsi3+0xcc>
- 8001730: 010b lsls r3, r1, #4
- 8001732: 1ac0 subs r0, r0, r3
- 8001734: 4152 adcs r2, r2
- 8001736: 08c3 lsrs r3, r0, #3
- 8001738: 428b cmp r3, r1
- 800173a: d301 bcc.n 8001740 <__udivsi3+0xd8>
- 800173c: 00cb lsls r3, r1, #3
- 800173e: 1ac0 subs r0, r0, r3
- 8001740: 4152 adcs r2, r2
- 8001742: 0883 lsrs r3, r0, #2
- 8001744: 428b cmp r3, r1
- 8001746: d301 bcc.n 800174c <__udivsi3+0xe4>
- 8001748: 008b lsls r3, r1, #2
- 800174a: 1ac0 subs r0, r0, r3
- 800174c: 4152 adcs r2, r2
- 800174e: 0843 lsrs r3, r0, #1
- 8001750: 428b cmp r3, r1
- 8001752: d301 bcc.n 8001758 <__udivsi3+0xf0>
- 8001754: 004b lsls r3, r1, #1
- 8001756: 1ac0 subs r0, r0, r3
- 8001758: 4152 adcs r2, r2
- 800175a: 1a41 subs r1, r0, r1
- 800175c: d200 bcs.n 8001760 <__udivsi3+0xf8>
- 800175e: 4601 mov r1, r0
- 8001760: 4152 adcs r2, r2
- 8001762: 4610 mov r0, r2
- 8001764: 4770 bx lr
- 8001766: e7ff b.n 8001768 <__udivsi3+0x100>
- 8001768: b501 push {r0, lr}
- 800176a: 2000 movs r0, #0
- 800176c: f000 f8f0 bl 8001950 <__aeabi_idiv0>
- 8001770: bd02 pop {r1, pc}
- 8001772: 46c0 nop ; (mov r8, r8)
-
-08001774 <__aeabi_uidivmod>:
- 8001774: 2900 cmp r1, #0
- 8001776: d0f7 beq.n 8001768 <__udivsi3+0x100>
- 8001778: e776 b.n 8001668 <__udivsi3>
- 800177a: 4770 bx lr
-
-0800177c <__divsi3>:
- 800177c: 4603 mov r3, r0
- 800177e: 430b orrs r3, r1
- 8001780: d47f bmi.n 8001882 <__divsi3+0x106>
- 8001782: 2200 movs r2, #0
- 8001784: 0843 lsrs r3, r0, #1
- 8001786: 428b cmp r3, r1
- 8001788: d374 bcc.n 8001874 <__divsi3+0xf8>
- 800178a: 0903 lsrs r3, r0, #4
- 800178c: 428b cmp r3, r1
- 800178e: d35f bcc.n 8001850 <__divsi3+0xd4>
- 8001790: 0a03 lsrs r3, r0, #8
- 8001792: 428b cmp r3, r1
- 8001794: d344 bcc.n 8001820 <__divsi3+0xa4>
- 8001796: 0b03 lsrs r3, r0, #12
- 8001798: 428b cmp r3, r1
- 800179a: d328 bcc.n 80017ee <__divsi3+0x72>
- 800179c: 0c03 lsrs r3, r0, #16
- 800179e: 428b cmp r3, r1
- 80017a0: d30d bcc.n 80017be <__divsi3+0x42>
- 80017a2: 22ff movs r2, #255 ; 0xff
- 80017a4: 0209 lsls r1, r1, #8
- 80017a6: ba12 rev r2, r2
- 80017a8: 0c03 lsrs r3, r0, #16
- 80017aa: 428b cmp r3, r1
- 80017ac: d302 bcc.n 80017b4 <__divsi3+0x38>
- 80017ae: 1212 asrs r2, r2, #8
- 80017b0: 0209 lsls r1, r1, #8
- 80017b2: d065 beq.n 8001880 <__divsi3+0x104>
- 80017b4: 0b03 lsrs r3, r0, #12
- 80017b6: 428b cmp r3, r1
- 80017b8: d319 bcc.n 80017ee <__divsi3+0x72>
- 80017ba: e000 b.n 80017be <__divsi3+0x42>
- 80017bc: 0a09 lsrs r1, r1, #8
- 80017be: 0bc3 lsrs r3, r0, #15
- 80017c0: 428b cmp r3, r1
- 80017c2: d301 bcc.n 80017c8 <__divsi3+0x4c>
- 80017c4: 03cb lsls r3, r1, #15
- 80017c6: 1ac0 subs r0, r0, r3
- 80017c8: 4152 adcs r2, r2
- 80017ca: 0b83 lsrs r3, r0, #14
- 80017cc: 428b cmp r3, r1
- 80017ce: d301 bcc.n 80017d4 <__divsi3+0x58>
- 80017d0: 038b lsls r3, r1, #14
- 80017d2: 1ac0 subs r0, r0, r3
- 80017d4: 4152 adcs r2, r2
- 80017d6: 0b43 lsrs r3, r0, #13
- 80017d8: 428b cmp r3, r1
- 80017da: d301 bcc.n 80017e0 <__divsi3+0x64>
- 80017dc: 034b lsls r3, r1, #13
- 80017de: 1ac0 subs r0, r0, r3
- 80017e0: 4152 adcs r2, r2
- 80017e2: 0b03 lsrs r3, r0, #12
- 80017e4: 428b cmp r3, r1
- 80017e6: d301 bcc.n 80017ec <__divsi3+0x70>
- 80017e8: 030b lsls r3, r1, #12
- 80017ea: 1ac0 subs r0, r0, r3
- 80017ec: 4152 adcs r2, r2
- 80017ee: 0ac3 lsrs r3, r0, #11
- 80017f0: 428b cmp r3, r1
- 80017f2: d301 bcc.n 80017f8 <__divsi3+0x7c>
- 80017f4: 02cb lsls r3, r1, #11
- 80017f6: 1ac0 subs r0, r0, r3
- 80017f8: 4152 adcs r2, r2
- 80017fa: 0a83 lsrs r3, r0, #10
- 80017fc: 428b cmp r3, r1
- 80017fe: d301 bcc.n 8001804 <__divsi3+0x88>
- 8001800: 028b lsls r3, r1, #10
- 8001802: 1ac0 subs r0, r0, r3
- 8001804: 4152 adcs r2, r2
- 8001806: 0a43 lsrs r3, r0, #9
- 8001808: 428b cmp r3, r1
- 800180a: d301 bcc.n 8001810 <__divsi3+0x94>
- 800180c: 024b lsls r3, r1, #9
- 800180e: 1ac0 subs r0, r0, r3
- 8001810: 4152 adcs r2, r2
- 8001812: 0a03 lsrs r3, r0, #8
- 8001814: 428b cmp r3, r1
- 8001816: d301 bcc.n 800181c <__divsi3+0xa0>
- 8001818: 020b lsls r3, r1, #8
- 800181a: 1ac0 subs r0, r0, r3
- 800181c: 4152 adcs r2, r2
- 800181e: d2cd bcs.n 80017bc <__divsi3+0x40>
- 8001820: 09c3 lsrs r3, r0, #7
- 8001822: 428b cmp r3, r1
- 8001824: d301 bcc.n 800182a <__divsi3+0xae>
- 8001826: 01cb lsls r3, r1, #7
- 8001828: 1ac0 subs r0, r0, r3
- 800182a: 4152 adcs r2, r2
- 800182c: 0983 lsrs r3, r0, #6
- 800182e: 428b cmp r3, r1
- 8001830: d301 bcc.n 8001836 <__divsi3+0xba>
- 8001832: 018b lsls r3, r1, #6
- 8001834: 1ac0 subs r0, r0, r3
- 8001836: 4152 adcs r2, r2
- 8001838: 0943 lsrs r3, r0, #5
- 800183a: 428b cmp r3, r1
- 800183c: d301 bcc.n 8001842 <__divsi3+0xc6>
- 800183e: 014b lsls r3, r1, #5
- 8001840: 1ac0 subs r0, r0, r3
- 8001842: 4152 adcs r2, r2
- 8001844: 0903 lsrs r3, r0, #4
- 8001846: 428b cmp r3, r1
- 8001848: d301 bcc.n 800184e <__divsi3+0xd2>
- 800184a: 010b lsls r3, r1, #4
- 800184c: 1ac0 subs r0, r0, r3
- 800184e: 4152 adcs r2, r2
- 8001850: 08c3 lsrs r3, r0, #3
- 8001852: 428b cmp r3, r1
- 8001854: d301 bcc.n 800185a <__divsi3+0xde>
- 8001856: 00cb lsls r3, r1, #3
- 8001858: 1ac0 subs r0, r0, r3
- 800185a: 4152 adcs r2, r2
- 800185c: 0883 lsrs r3, r0, #2
- 800185e: 428b cmp r3, r1
- 8001860: d301 bcc.n 8001866 <__divsi3+0xea>
- 8001862: 008b lsls r3, r1, #2
- 8001864: 1ac0 subs r0, r0, r3
- 8001866: 4152 adcs r2, r2
- 8001868: 0843 lsrs r3, r0, #1
- 800186a: 428b cmp r3, r1
- 800186c: d301 bcc.n 8001872 <__divsi3+0xf6>
- 800186e: 004b lsls r3, r1, #1
- 8001870: 1ac0 subs r0, r0, r3
- 8001872: 4152 adcs r2, r2
- 8001874: 1a41 subs r1, r0, r1
- 8001876: d200 bcs.n 800187a <__divsi3+0xfe>
- 8001878: 4601 mov r1, r0
- 800187a: 4152 adcs r2, r2
- 800187c: 4610 mov r0, r2
- 800187e: 4770 bx lr
- 8001880: e05d b.n 800193e <__divsi3+0x1c2>
- 8001882: 0fca lsrs r2, r1, #31
- 8001884: d000 beq.n 8001888 <__divsi3+0x10c>
- 8001886: 4249 negs r1, r1
- 8001888: 1003 asrs r3, r0, #32
- 800188a: d300 bcc.n 800188e <__divsi3+0x112>
- 800188c: 4240 negs r0, r0
- 800188e: 4053 eors r3, r2
- 8001890: 2200 movs r2, #0
- 8001892: 469c mov ip, r3
- 8001894: 0903 lsrs r3, r0, #4
- 8001896: 428b cmp r3, r1
- 8001898: d32d bcc.n 80018f6 <__divsi3+0x17a>
- 800189a: 0a03 lsrs r3, r0, #8
- 800189c: 428b cmp r3, r1
- 800189e: d312 bcc.n 80018c6 <__divsi3+0x14a>
- 80018a0: 22fc movs r2, #252 ; 0xfc
- 80018a2: 0189 lsls r1, r1, #6
- 80018a4: ba12 rev r2, r2
- 80018a6: 0a03 lsrs r3, r0, #8
- 80018a8: 428b cmp r3, r1
- 80018aa: d30c bcc.n 80018c6 <__divsi3+0x14a>
- 80018ac: 0189 lsls r1, r1, #6
- 80018ae: 1192 asrs r2, r2, #6
- 80018b0: 428b cmp r3, r1
- 80018b2: d308 bcc.n 80018c6 <__divsi3+0x14a>
- 80018b4: 0189 lsls r1, r1, #6
- 80018b6: 1192 asrs r2, r2, #6
- 80018b8: 428b cmp r3, r1
- 80018ba: d304 bcc.n 80018c6 <__divsi3+0x14a>
- 80018bc: 0189 lsls r1, r1, #6
- 80018be: d03a beq.n 8001936 <__divsi3+0x1ba>
- 80018c0: 1192 asrs r2, r2, #6
- 80018c2: e000 b.n 80018c6 <__divsi3+0x14a>
- 80018c4: 0989 lsrs r1, r1, #6
- 80018c6: 09c3 lsrs r3, r0, #7
- 80018c8: 428b cmp r3, r1
- 80018ca: d301 bcc.n 80018d0 <__divsi3+0x154>
- 80018cc: 01cb lsls r3, r1, #7
- 80018ce: 1ac0 subs r0, r0, r3
- 80018d0: 4152 adcs r2, r2
- 80018d2: 0983 lsrs r3, r0, #6
- 80018d4: 428b cmp r3, r1
- 80018d6: d301 bcc.n 80018dc <__divsi3+0x160>
- 80018d8: 018b lsls r3, r1, #6
- 80018da: 1ac0 subs r0, r0, r3
- 80018dc: 4152 adcs r2, r2
- 80018de: 0943 lsrs r3, r0, #5
- 80018e0: 428b cmp r3, r1
- 80018e2: d301 bcc.n 80018e8 <__divsi3+0x16c>
- 80018e4: 014b lsls r3, r1, #5
- 80018e6: 1ac0 subs r0, r0, r3
- 80018e8: 4152 adcs r2, r2
- 80018ea: 0903 lsrs r3, r0, #4
- 80018ec: 428b cmp r3, r1
- 80018ee: d301 bcc.n 80018f4 <__divsi3+0x178>
- 80018f0: 010b lsls r3, r1, #4
- 80018f2: 1ac0 subs r0, r0, r3
- 80018f4: 4152 adcs r2, r2
- 80018f6: 08c3 lsrs r3, r0, #3
- 80018f8: 428b cmp r3, r1
- 80018fa: d301 bcc.n 8001900 <__divsi3+0x184>
- 80018fc: 00cb lsls r3, r1, #3
- 80018fe: 1ac0 subs r0, r0, r3
- 8001900: 4152 adcs r2, r2
- 8001902: 0883 lsrs r3, r0, #2
- 8001904: 428b cmp r3, r1
- 8001906: d301 bcc.n 800190c <__divsi3+0x190>
- 8001908: 008b lsls r3, r1, #2
- 800190a: 1ac0 subs r0, r0, r3
- 800190c: 4152 adcs r2, r2
- 800190e: d2d9 bcs.n 80018c4 <__divsi3+0x148>
- 8001910: 0843 lsrs r3, r0, #1
- 8001912: 428b cmp r3, r1
- 8001914: d301 bcc.n 800191a <__divsi3+0x19e>
- 8001916: 004b lsls r3, r1, #1
- 8001918: 1ac0 subs r0, r0, r3
- 800191a: 4152 adcs r2, r2
- 800191c: 1a41 subs r1, r0, r1
- 800191e: d200 bcs.n 8001922 <__divsi3+0x1a6>
- 8001920: 4601 mov r1, r0
- 8001922: 4663 mov r3, ip
- 8001924: 4152 adcs r2, r2
- 8001926: 105b asrs r3, r3, #1
- 8001928: 4610 mov r0, r2
- 800192a: d301 bcc.n 8001930 <__divsi3+0x1b4>
- 800192c: 4240 negs r0, r0
- 800192e: 2b00 cmp r3, #0
- 8001930: d500 bpl.n 8001934 <__divsi3+0x1b8>
- 8001932: 4249 negs r1, r1
- 8001934: 4770 bx lr
- 8001936: 4663 mov r3, ip
- 8001938: 105b asrs r3, r3, #1
- 800193a: d300 bcc.n 800193e <__divsi3+0x1c2>
- 800193c: 4240 negs r0, r0
- 800193e: b501 push {r0, lr}
- 8001940: 2000 movs r0, #0
- 8001942: f000 f805 bl 8001950 <__aeabi_idiv0>
- 8001946: bd02 pop {r1, pc}
-
-08001948 <__aeabi_idivmod>:
- 8001948: 2900 cmp r1, #0
- 800194a: d0f8 beq.n 800193e <__divsi3+0x1c2>
- 800194c: e716 b.n 800177c <__divsi3>
- 800194e: 4770 bx lr
-
-08001950 <__aeabi_idiv0>:
- 8001950: 4770 bx lr
- 8001952: 46c0 nop ; (mov r8, r8)
-
-08001954 <Reset_Handler>:
+08001910 <__udivsi3>:
+ 8001910: 2200 movs r2, #0
+ 8001912: 0843 lsrs r3, r0, #1
+ 8001914: 428b cmp r3, r1
+ 8001916: d374 bcc.n 8001a02 <__udivsi3+0xf2>
+ 8001918: 0903 lsrs r3, r0, #4
+ 800191a: 428b cmp r3, r1
+ 800191c: d35f bcc.n 80019de <__udivsi3+0xce>
+ 800191e: 0a03 lsrs r3, r0, #8
+ 8001920: 428b cmp r3, r1
+ 8001922: d344 bcc.n 80019ae <__udivsi3+0x9e>
+ 8001924: 0b03 lsrs r3, r0, #12
+ 8001926: 428b cmp r3, r1
+ 8001928: d328 bcc.n 800197c <__udivsi3+0x6c>
+ 800192a: 0c03 lsrs r3, r0, #16
+ 800192c: 428b cmp r3, r1
+ 800192e: d30d bcc.n 800194c <__udivsi3+0x3c>
+ 8001930: 22ff movs r2, #255 ; 0xff
+ 8001932: 0209 lsls r1, r1, #8
+ 8001934: ba12 rev r2, r2
+ 8001936: 0c03 lsrs r3, r0, #16
+ 8001938: 428b cmp r3, r1
+ 800193a: d302 bcc.n 8001942 <__udivsi3+0x32>
+ 800193c: 1212 asrs r2, r2, #8
+ 800193e: 0209 lsls r1, r1, #8
+ 8001940: d065 beq.n 8001a0e <__udivsi3+0xfe>
+ 8001942: 0b03 lsrs r3, r0, #12
+ 8001944: 428b cmp r3, r1
+ 8001946: d319 bcc.n 800197c <__udivsi3+0x6c>
+ 8001948: e000 b.n 800194c <__udivsi3+0x3c>
+ 800194a: 0a09 lsrs r1, r1, #8
+ 800194c: 0bc3 lsrs r3, r0, #15
+ 800194e: 428b cmp r3, r1
+ 8001950: d301 bcc.n 8001956 <__udivsi3+0x46>
+ 8001952: 03cb lsls r3, r1, #15
+ 8001954: 1ac0 subs r0, r0, r3
+ 8001956: 4152 adcs r2, r2
+ 8001958: 0b83 lsrs r3, r0, #14
+ 800195a: 428b cmp r3, r1
+ 800195c: d301 bcc.n 8001962 <__udivsi3+0x52>
+ 800195e: 038b lsls r3, r1, #14
+ 8001960: 1ac0 subs r0, r0, r3
+ 8001962: 4152 adcs r2, r2
+ 8001964: 0b43 lsrs r3, r0, #13
+ 8001966: 428b cmp r3, r1
+ 8001968: d301 bcc.n 800196e <__udivsi3+0x5e>
+ 800196a: 034b lsls r3, r1, #13
+ 800196c: 1ac0 subs r0, r0, r3
+ 800196e: 4152 adcs r2, r2
+ 8001970: 0b03 lsrs r3, r0, #12
+ 8001972: 428b cmp r3, r1
+ 8001974: d301 bcc.n 800197a <__udivsi3+0x6a>
+ 8001976: 030b lsls r3, r1, #12
+ 8001978: 1ac0 subs r0, r0, r3
+ 800197a: 4152 adcs r2, r2
+ 800197c: 0ac3 lsrs r3, r0, #11
+ 800197e: 428b cmp r3, r1
+ 8001980: d301 bcc.n 8001986 <__udivsi3+0x76>
+ 8001982: 02cb lsls r3, r1, #11
+ 8001984: 1ac0 subs r0, r0, r3
+ 8001986: 4152 adcs r2, r2
+ 8001988: 0a83 lsrs r3, r0, #10
+ 800198a: 428b cmp r3, r1
+ 800198c: d301 bcc.n 8001992 <__udivsi3+0x82>
+ 800198e: 028b lsls r3, r1, #10
+ 8001990: 1ac0 subs r0, r0, r3
+ 8001992: 4152 adcs r2, r2
+ 8001994: 0a43 lsrs r3, r0, #9
+ 8001996: 428b cmp r3, r1
+ 8001998: d301 bcc.n 800199e <__udivsi3+0x8e>
+ 800199a: 024b lsls r3, r1, #9
+ 800199c: 1ac0 subs r0, r0, r3
+ 800199e: 4152 adcs r2, r2
+ 80019a0: 0a03 lsrs r3, r0, #8
+ 80019a2: 428b cmp r3, r1
+ 80019a4: d301 bcc.n 80019aa <__udivsi3+0x9a>
+ 80019a6: 020b lsls r3, r1, #8
+ 80019a8: 1ac0 subs r0, r0, r3
+ 80019aa: 4152 adcs r2, r2
+ 80019ac: d2cd bcs.n 800194a <__udivsi3+0x3a>
+ 80019ae: 09c3 lsrs r3, r0, #7
+ 80019b0: 428b cmp r3, r1
+ 80019b2: d301 bcc.n 80019b8 <__udivsi3+0xa8>
+ 80019b4: 01cb lsls r3, r1, #7
+ 80019b6: 1ac0 subs r0, r0, r3
+ 80019b8: 4152 adcs r2, r2
+ 80019ba: 0983 lsrs r3, r0, #6
+ 80019bc: 428b cmp r3, r1
+ 80019be: d301 bcc.n 80019c4 <__udivsi3+0xb4>
+ 80019c0: 018b lsls r3, r1, #6
+ 80019c2: 1ac0 subs r0, r0, r3
+ 80019c4: 4152 adcs r2, r2
+ 80019c6: 0943 lsrs r3, r0, #5
+ 80019c8: 428b cmp r3, r1
+ 80019ca: d301 bcc.n 80019d0 <__udivsi3+0xc0>
+ 80019cc: 014b lsls r3, r1, #5
+ 80019ce: 1ac0 subs r0, r0, r3
+ 80019d0: 4152 adcs r2, r2
+ 80019d2: 0903 lsrs r3, r0, #4
+ 80019d4: 428b cmp r3, r1
+ 80019d6: d301 bcc.n 80019dc <__udivsi3+0xcc>
+ 80019d8: 010b lsls r3, r1, #4
+ 80019da: 1ac0 subs r0, r0, r3
+ 80019dc: 4152 adcs r2, r2
+ 80019de: 08c3 lsrs r3, r0, #3
+ 80019e0: 428b cmp r3, r1
+ 80019e2: d301 bcc.n 80019e8 <__udivsi3+0xd8>
+ 80019e4: 00cb lsls r3, r1, #3
+ 80019e6: 1ac0 subs r0, r0, r3
+ 80019e8: 4152 adcs r2, r2
+ 80019ea: 0883 lsrs r3, r0, #2
+ 80019ec: 428b cmp r3, r1
+ 80019ee: d301 bcc.n 80019f4 <__udivsi3+0xe4>
+ 80019f0: 008b lsls r3, r1, #2
+ 80019f2: 1ac0 subs r0, r0, r3
+ 80019f4: 4152 adcs r2, r2
+ 80019f6: 0843 lsrs r3, r0, #1
+ 80019f8: 428b cmp r3, r1
+ 80019fa: d301 bcc.n 8001a00 <__udivsi3+0xf0>
+ 80019fc: 004b lsls r3, r1, #1
+ 80019fe: 1ac0 subs r0, r0, r3
+ 8001a00: 4152 adcs r2, r2
+ 8001a02: 1a41 subs r1, r0, r1
+ 8001a04: d200 bcs.n 8001a08 <__udivsi3+0xf8>
+ 8001a06: 4601 mov r1, r0
+ 8001a08: 4152 adcs r2, r2
+ 8001a0a: 4610 mov r0, r2
+ 8001a0c: 4770 bx lr
+ 8001a0e: e7ff b.n 8001a10 <__udivsi3+0x100>
+ 8001a10: b501 push {r0, lr}
+ 8001a12: 2000 movs r0, #0
+ 8001a14: f000 f8f0 bl 8001bf8 <__aeabi_idiv0>
+ 8001a18: bd02 pop {r1, pc}
+ 8001a1a: 46c0 nop ; (mov r8, r8)
+
+08001a1c <__aeabi_uidivmod>:
+ 8001a1c: 2900 cmp r1, #0
+ 8001a1e: d0f7 beq.n 8001a10 <__udivsi3+0x100>
+ 8001a20: e776 b.n 8001910 <__udivsi3>
+ 8001a22: 4770 bx lr
+
+08001a24 <__divsi3>:
+ 8001a24: 4603 mov r3, r0
+ 8001a26: 430b orrs r3, r1
+ 8001a28: d47f bmi.n 8001b2a <__divsi3+0x106>
+ 8001a2a: 2200 movs r2, #0
+ 8001a2c: 0843 lsrs r3, r0, #1
+ 8001a2e: 428b cmp r3, r1
+ 8001a30: d374 bcc.n 8001b1c <__divsi3+0xf8>
+ 8001a32: 0903 lsrs r3, r0, #4
+ 8001a34: 428b cmp r3, r1
+ 8001a36: d35f bcc.n 8001af8 <__divsi3+0xd4>
+ 8001a38: 0a03 lsrs r3, r0, #8
+ 8001a3a: 428b cmp r3, r1
+ 8001a3c: d344 bcc.n 8001ac8 <__divsi3+0xa4>
+ 8001a3e: 0b03 lsrs r3, r0, #12
+ 8001a40: 428b cmp r3, r1
+ 8001a42: d328 bcc.n 8001a96 <__divsi3+0x72>
+ 8001a44: 0c03 lsrs r3, r0, #16
+ 8001a46: 428b cmp r3, r1
+ 8001a48: d30d bcc.n 8001a66 <__divsi3+0x42>
+ 8001a4a: 22ff movs r2, #255 ; 0xff
+ 8001a4c: 0209 lsls r1, r1, #8
+ 8001a4e: ba12 rev r2, r2
+ 8001a50: 0c03 lsrs r3, r0, #16
+ 8001a52: 428b cmp r3, r1
+ 8001a54: d302 bcc.n 8001a5c <__divsi3+0x38>
+ 8001a56: 1212 asrs r2, r2, #8
+ 8001a58: 0209 lsls r1, r1, #8
+ 8001a5a: d065 beq.n 8001b28 <__divsi3+0x104>
+ 8001a5c: 0b03 lsrs r3, r0, #12
+ 8001a5e: 428b cmp r3, r1
+ 8001a60: d319 bcc.n 8001a96 <__divsi3+0x72>
+ 8001a62: e000 b.n 8001a66 <__divsi3+0x42>
+ 8001a64: 0a09 lsrs r1, r1, #8
+ 8001a66: 0bc3 lsrs r3, r0, #15
+ 8001a68: 428b cmp r3, r1
+ 8001a6a: d301 bcc.n 8001a70 <__divsi3+0x4c>
+ 8001a6c: 03cb lsls r3, r1, #15
+ 8001a6e: 1ac0 subs r0, r0, r3
+ 8001a70: 4152 adcs r2, r2
+ 8001a72: 0b83 lsrs r3, r0, #14
+ 8001a74: 428b cmp r3, r1
+ 8001a76: d301 bcc.n 8001a7c <__divsi3+0x58>
+ 8001a78: 038b lsls r3, r1, #14
+ 8001a7a: 1ac0 subs r0, r0, r3
+ 8001a7c: 4152 adcs r2, r2
+ 8001a7e: 0b43 lsrs r3, r0, #13
+ 8001a80: 428b cmp r3, r1
+ 8001a82: d301 bcc.n 8001a88 <__divsi3+0x64>
+ 8001a84: 034b lsls r3, r1, #13
+ 8001a86: 1ac0 subs r0, r0, r3
+ 8001a88: 4152 adcs r2, r2
+ 8001a8a: 0b03 lsrs r3, r0, #12
+ 8001a8c: 428b cmp r3, r1
+ 8001a8e: d301 bcc.n 8001a94 <__divsi3+0x70>
+ 8001a90: 030b lsls r3, r1, #12
+ 8001a92: 1ac0 subs r0, r0, r3
+ 8001a94: 4152 adcs r2, r2
+ 8001a96: 0ac3 lsrs r3, r0, #11
+ 8001a98: 428b cmp r3, r1
+ 8001a9a: d301 bcc.n 8001aa0 <__divsi3+0x7c>
+ 8001a9c: 02cb lsls r3, r1, #11
+ 8001a9e: 1ac0 subs r0, r0, r3
+ 8001aa0: 4152 adcs r2, r2
+ 8001aa2: 0a83 lsrs r3, r0, #10
+ 8001aa4: 428b cmp r3, r1
+ 8001aa6: d301 bcc.n 8001aac <__divsi3+0x88>
+ 8001aa8: 028b lsls r3, r1, #10
+ 8001aaa: 1ac0 subs r0, r0, r3
+ 8001aac: 4152 adcs r2, r2
+ 8001aae: 0a43 lsrs r3, r0, #9
+ 8001ab0: 428b cmp r3, r1
+ 8001ab2: d301 bcc.n 8001ab8 <__divsi3+0x94>
+ 8001ab4: 024b lsls r3, r1, #9
+ 8001ab6: 1ac0 subs r0, r0, r3
+ 8001ab8: 4152 adcs r2, r2
+ 8001aba: 0a03 lsrs r3, r0, #8
+ 8001abc: 428b cmp r3, r1
+ 8001abe: d301 bcc.n 8001ac4 <__divsi3+0xa0>
+ 8001ac0: 020b lsls r3, r1, #8
+ 8001ac2: 1ac0 subs r0, r0, r3
+ 8001ac4: 4152 adcs r2, r2
+ 8001ac6: d2cd bcs.n 8001a64 <__divsi3+0x40>
+ 8001ac8: 09c3 lsrs r3, r0, #7
+ 8001aca: 428b cmp r3, r1
+ 8001acc: d301 bcc.n 8001ad2 <__divsi3+0xae>
+ 8001ace: 01cb lsls r3, r1, #7
+ 8001ad0: 1ac0 subs r0, r0, r3
+ 8001ad2: 4152 adcs r2, r2
+ 8001ad4: 0983 lsrs r3, r0, #6
+ 8001ad6: 428b cmp r3, r1
+ 8001ad8: d301 bcc.n 8001ade <__divsi3+0xba>
+ 8001ada: 018b lsls r3, r1, #6
+ 8001adc: 1ac0 subs r0, r0, r3
+ 8001ade: 4152 adcs r2, r2
+ 8001ae0: 0943 lsrs r3, r0, #5
+ 8001ae2: 428b cmp r3, r1
+ 8001ae4: d301 bcc.n 8001aea <__divsi3+0xc6>
+ 8001ae6: 014b lsls r3, r1, #5
+ 8001ae8: 1ac0 subs r0, r0, r3
+ 8001aea: 4152 adcs r2, r2
+ 8001aec: 0903 lsrs r3, r0, #4
+ 8001aee: 428b cmp r3, r1
+ 8001af0: d301 bcc.n 8001af6 <__divsi3+0xd2>
+ 8001af2: 010b lsls r3, r1, #4
+ 8001af4: 1ac0 subs r0, r0, r3
+ 8001af6: 4152 adcs r2, r2
+ 8001af8: 08c3 lsrs r3, r0, #3
+ 8001afa: 428b cmp r3, r1
+ 8001afc: d301 bcc.n 8001b02 <__divsi3+0xde>
+ 8001afe: 00cb lsls r3, r1, #3
+ 8001b00: 1ac0 subs r0, r0, r3
+ 8001b02: 4152 adcs r2, r2
+ 8001b04: 0883 lsrs r3, r0, #2
+ 8001b06: 428b cmp r3, r1
+ 8001b08: d301 bcc.n 8001b0e <__divsi3+0xea>
+ 8001b0a: 008b lsls r3, r1, #2
+ 8001b0c: 1ac0 subs r0, r0, r3
+ 8001b0e: 4152 adcs r2, r2
+ 8001b10: 0843 lsrs r3, r0, #1
+ 8001b12: 428b cmp r3, r1
+ 8001b14: d301 bcc.n 8001b1a <__divsi3+0xf6>
+ 8001b16: 004b lsls r3, r1, #1
+ 8001b18: 1ac0 subs r0, r0, r3
+ 8001b1a: 4152 adcs r2, r2
+ 8001b1c: 1a41 subs r1, r0, r1
+ 8001b1e: d200 bcs.n 8001b22 <__divsi3+0xfe>
+ 8001b20: 4601 mov r1, r0
+ 8001b22: 4152 adcs r2, r2
+ 8001b24: 4610 mov r0, r2
+ 8001b26: 4770 bx lr
+ 8001b28: e05d b.n 8001be6 <__divsi3+0x1c2>
+ 8001b2a: 0fca lsrs r2, r1, #31
+ 8001b2c: d000 beq.n 8001b30 <__divsi3+0x10c>
+ 8001b2e: 4249 negs r1, r1
+ 8001b30: 1003 asrs r3, r0, #32
+ 8001b32: d300 bcc.n 8001b36 <__divsi3+0x112>
+ 8001b34: 4240 negs r0, r0
+ 8001b36: 4053 eors r3, r2
+ 8001b38: 2200 movs r2, #0
+ 8001b3a: 469c mov ip, r3
+ 8001b3c: 0903 lsrs r3, r0, #4
+ 8001b3e: 428b cmp r3, r1
+ 8001b40: d32d bcc.n 8001b9e <__divsi3+0x17a>
+ 8001b42: 0a03 lsrs r3, r0, #8
+ 8001b44: 428b cmp r3, r1
+ 8001b46: d312 bcc.n 8001b6e <__divsi3+0x14a>
+ 8001b48: 22fc movs r2, #252 ; 0xfc
+ 8001b4a: 0189 lsls r1, r1, #6
+ 8001b4c: ba12 rev r2, r2
+ 8001b4e: 0a03 lsrs r3, r0, #8
+ 8001b50: 428b cmp r3, r1
+ 8001b52: d30c bcc.n 8001b6e <__divsi3+0x14a>
+ 8001b54: 0189 lsls r1, r1, #6
+ 8001b56: 1192 asrs r2, r2, #6
+ 8001b58: 428b cmp r3, r1
+ 8001b5a: d308 bcc.n 8001b6e <__divsi3+0x14a>
+ 8001b5c: 0189 lsls r1, r1, #6
+ 8001b5e: 1192 asrs r2, r2, #6
+ 8001b60: 428b cmp r3, r1
+ 8001b62: d304 bcc.n 8001b6e <__divsi3+0x14a>
+ 8001b64: 0189 lsls r1, r1, #6
+ 8001b66: d03a beq.n 8001bde <__divsi3+0x1ba>
+ 8001b68: 1192 asrs r2, r2, #6
+ 8001b6a: e000 b.n 8001b6e <__divsi3+0x14a>
+ 8001b6c: 0989 lsrs r1, r1, #6
+ 8001b6e: 09c3 lsrs r3, r0, #7
+ 8001b70: 428b cmp r3, r1
+ 8001b72: d301 bcc.n 8001b78 <__divsi3+0x154>
+ 8001b74: 01cb lsls r3, r1, #7
+ 8001b76: 1ac0 subs r0, r0, r3
+ 8001b78: 4152 adcs r2, r2
+ 8001b7a: 0983 lsrs r3, r0, #6
+ 8001b7c: 428b cmp r3, r1
+ 8001b7e: d301 bcc.n 8001b84 <__divsi3+0x160>
+ 8001b80: 018b lsls r3, r1, #6
+ 8001b82: 1ac0 subs r0, r0, r3
+ 8001b84: 4152 adcs r2, r2
+ 8001b86: 0943 lsrs r3, r0, #5
+ 8001b88: 428b cmp r3, r1
+ 8001b8a: d301 bcc.n 8001b90 <__divsi3+0x16c>
+ 8001b8c: 014b lsls r3, r1, #5
+ 8001b8e: 1ac0 subs r0, r0, r3
+ 8001b90: 4152 adcs r2, r2
+ 8001b92: 0903 lsrs r3, r0, #4
+ 8001b94: 428b cmp r3, r1
+ 8001b96: d301 bcc.n 8001b9c <__divsi3+0x178>
+ 8001b98: 010b lsls r3, r1, #4
+ 8001b9a: 1ac0 subs r0, r0, r3
+ 8001b9c: 4152 adcs r2, r2
+ 8001b9e: 08c3 lsrs r3, r0, #3
+ 8001ba0: 428b cmp r3, r1
+ 8001ba2: d301 bcc.n 8001ba8 <__divsi3+0x184>
+ 8001ba4: 00cb lsls r3, r1, #3
+ 8001ba6: 1ac0 subs r0, r0, r3
+ 8001ba8: 4152 adcs r2, r2
+ 8001baa: 0883 lsrs r3, r0, #2
+ 8001bac: 428b cmp r3, r1
+ 8001bae: d301 bcc.n 8001bb4 <__divsi3+0x190>
+ 8001bb0: 008b lsls r3, r1, #2
+ 8001bb2: 1ac0 subs r0, r0, r3
+ 8001bb4: 4152 adcs r2, r2
+ 8001bb6: d2d9 bcs.n 8001b6c <__divsi3+0x148>
+ 8001bb8: 0843 lsrs r3, r0, #1
+ 8001bba: 428b cmp r3, r1
+ 8001bbc: d301 bcc.n 8001bc2 <__divsi3+0x19e>
+ 8001bbe: 004b lsls r3, r1, #1
+ 8001bc0: 1ac0 subs r0, r0, r3
+ 8001bc2: 4152 adcs r2, r2
+ 8001bc4: 1a41 subs r1, r0, r1
+ 8001bc6: d200 bcs.n 8001bca <__divsi3+0x1a6>
+ 8001bc8: 4601 mov r1, r0
+ 8001bca: 4663 mov r3, ip
+ 8001bcc: 4152 adcs r2, r2
+ 8001bce: 105b asrs r3, r3, #1
+ 8001bd0: 4610 mov r0, r2
+ 8001bd2: d301 bcc.n 8001bd8 <__divsi3+0x1b4>
+ 8001bd4: 4240 negs r0, r0
+ 8001bd6: 2b00 cmp r3, #0
+ 8001bd8: d500 bpl.n 8001bdc <__divsi3+0x1b8>
+ 8001bda: 4249 negs r1, r1
+ 8001bdc: 4770 bx lr
+ 8001bde: 4663 mov r3, ip
+ 8001be0: 105b asrs r3, r3, #1
+ 8001be2: d300 bcc.n 8001be6 <__divsi3+0x1c2>
+ 8001be4: 4240 negs r0, r0
+ 8001be6: b501 push {r0, lr}
+ 8001be8: 2000 movs r0, #0
+ 8001bea: f000 f805 bl 8001bf8 <__aeabi_idiv0>
+ 8001bee: bd02 pop {r1, pc}
+
+08001bf0 <__aeabi_idivmod>:
+ 8001bf0: 2900 cmp r1, #0
+ 8001bf2: d0f8 beq.n 8001be6 <__divsi3+0x1c2>
+ 8001bf4: e716 b.n 8001a24 <__divsi3>
+ 8001bf6: 4770 bx lr
+
+08001bf8 <__aeabi_idiv0>:
+ 8001bf8: 4770 bx lr
+ 8001bfa: 46c0 nop ; (mov r8, r8)
+
+08001bfc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
- 8001954: 480c ldr r0, [pc, #48] ; (8001988 <LoopForever+0x2>)
+ 8001bfc: 480c ldr r0, [pc, #48] ; (8001c30 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
- 8001956: 4685 mov sp, r0
+ 8001bfe: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 8001958: 2100 movs r1, #0
+ 8001c00: 2100 movs r1, #0
b LoopCopyDataInit
- 800195a: e003 b.n 8001964 <LoopCopyDataInit>
+ 8001c02: e003 b.n 8001c0c <LoopCopyDataInit>
-0800195c <CopyDataInit>:
+08001c04 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 800195c: 4b0b ldr r3, [pc, #44] ; (800198c <LoopForever+0x6>)
+ 8001c04: 4b0b ldr r3, [pc, #44] ; (8001c34 <LoopForever+0x6>)
ldr r3, [r3, r1]
- 800195e: 585b ldr r3, [r3, r1]
+ 8001c06: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 8001960: 5043 str r3, [r0, r1]
+ 8001c08: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 8001962: 3104 adds r1, #4
+ 8001c0a: 3104 adds r1, #4
-08001964 <LoopCopyDataInit>:
+08001c0c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 8001964: 480a ldr r0, [pc, #40] ; (8001990 <LoopForever+0xa>)
+ 8001c0c: 480a ldr r0, [pc, #40] ; (8001c38 <LoopForever+0xa>)
ldr r3, =_edata
- 8001966: 4b0b ldr r3, [pc, #44] ; (8001994 <LoopForever+0xe>)
+ 8001c0e: 4b0b ldr r3, [pc, #44] ; (8001c3c <LoopForever+0xe>)
adds r2, r0, r1
- 8001968: 1842 adds r2, r0, r1
+ 8001c10: 1842 adds r2, r0, r1
cmp r2, r3
- 800196a: 429a cmp r2, r3
+ 8001c12: 429a cmp r2, r3
bcc CopyDataInit
- 800196c: d3f6 bcc.n 800195c <CopyDataInit>
+ 8001c14: d3f6 bcc.n 8001c04 <CopyDataInit>
ldr r2, =_sbss
- 800196e: 4a0a ldr r2, [pc, #40] ; (8001998 <LoopForever+0x12>)
+ 8001c16: 4a0a ldr r2, [pc, #40] ; (8001c40 <LoopForever+0x12>)
b LoopFillZerobss
- 8001970: e002 b.n 8001978 <LoopFillZerobss>
+ 8001c18: e002 b.n 8001c20 <LoopFillZerobss>
-08001972 <FillZerobss>:
+08001c1a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 8001972: 2300 movs r3, #0
+ 8001c1a: 2300 movs r3, #0
str r3, [r2]
- 8001974: 6013 str r3, [r2, #0]
+ 8001c1c: 6013 str r3, [r2, #0]
adds r2, r2, #4
- 8001976: 3204 adds r2, #4
+ 8001c1e: 3204 adds r2, #4
-08001978 <LoopFillZerobss>:
+08001c20 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 8001978: 4b08 ldr r3, [pc, #32] ; (800199c <LoopForever+0x16>)
+ 8001c20: 4b08 ldr r3, [pc, #32] ; (8001c44 <LoopForever+0x16>)
cmp r2, r3
- 800197a: 429a cmp r2, r3
+ 8001c22: 429a cmp r2, r3
bcc FillZerobss
- 800197c: d3f9 bcc.n 8001972 <FillZerobss>
+ 8001c24: d3f9 bcc.n 8001c1a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
- 800197e: f7ff faad bl 8000edc <SystemInit>
+ 8001c26: f7ff faad bl 8001184 <SystemInit>
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/
bl main
- 8001982: f7fe fc4a bl 800021a <main>
+ 8001c2a: f7fe faf6 bl 800021a <main>
-08001986 <LoopForever>:
+08001c2e <LoopForever>:
LoopForever:
b LoopForever
- 8001986: e7fe b.n 8001986 <LoopForever>
+ 8001c2e: e7fe b.n 8001c2e <LoopForever>
ldr r0, =_estack
- 8001988: 20001000 .word 0x20001000
+ 8001c30: 20001000 .word 0x20001000
ldr r3, =_sidata
- 800198c: 080019bc .word 0x080019bc
+ 8001c34: 08001c64 .word 0x08001c64
ldr r0, =_sdata
- 8001990: 20000000 .word 0x20000000
+ 8001c38: 20000000 .word 0x20000000
ldr r3, =_edata
- 8001994: 20000094 .word 0x20000094
+ 8001c3c: 20000094 .word 0x20000094
ldr r2, =_sbss
- 8001998: 20000094 .word 0x20000094
+ 8001c40: 20000094 .word 0x20000094
ldr r3, = _ebss
- 800199c: 2000051c .word 0x2000051c
+ 8001c44: 200003b8 .word 0x200003b8
-080019a0 <ADC1_IRQHandler>:
+08001c48 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 80019a0: e7fe b.n 80019a0 <ADC1_IRQHandler>
+ 8001c48: e7fe b.n 8001c48 <ADC1_IRQHandler>
...
-080019a4 <AHBPrescTable>:
+08001c4c <AHBPrescTable>:
...
- 80019ac: 0201 0403 0706 0908 ........
+ 8001c54: 0201 0403 0706 0908 ........
-080019b4 <APBPrescTable>:
- 80019b4: 0000 0000 0201 0403 ........
+08001c5c <APBPrescTable>:
+ 8001c5c: 0000 0000 0201 0403 ........
diff --git a/gm_platform/fw/main.map b/gm_platform/fw/main.map
index 0baea99..3260f49 100644
--- a/gm_platform/fw/main.map
+++ b/gm_platform/fw/main.map
@@ -1,18 +1,17 @@
Archive member included to satisfy reference by file (symbol)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- /tmp/ccxtvPlT.o (__aeabi_uidiv)
+ /tmp/ccy8OCeb.o (__aeabi_uidiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- /tmp/ccrrpgrR.o (__aeabi_idiv)
+ /tmp/cc6Un0Q5.o (__aeabi_idiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
Allocating common symbols
Common symbol size file
-usart_tx_buf 0x40c /tmp/ccXNIrIP.o
-leds 0x20 /tmp/ccxtvPlT.o
-adc_buf 0x40 /tmp/ccrrpgrR.o
+usart_tx_buf 0x220 /tmp/ccRRCPG0.o
+leds 0x20 /tmp/ccy8OCeb.o
Memory Configuration
@@ -25,29 +24,29 @@ RAM 0x0000000020000000 0x0000000000001000 xrw
Linker script and memory map
LOAD /home/user/resource/STM32CubeF0/Drivers/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
-LOAD /tmp/ccxtvPlT.o
-LOAD /tmp/ccrrpgrR.o
-LOAD /tmp/ccXNIrIP.o
-LOAD /tmp/ccy0xC7N.o
-LOAD /tmp/ccr2qryM.o
-LOAD /tmp/ccJ50X5K.o
-LOAD /tmp/ccFUXyQJ.o
-LOAD /tmp/cc8rJnLI.o
-LOAD /tmp/ccDd2fMH.o
+LOAD /tmp/ccy8OCeb.o
+LOAD /tmp/cc6Un0Q5.o
+LOAD /tmp/ccRRCPG0.o
+LOAD /tmp/ccWI4kHV.o
+LOAD /tmp/ccjaIjJQ.o
+LOAD /tmp/cceYjaVL.o
+LOAD /tmp/ccsXJViH.o
+LOAD /tmp/ccGz0VMC.o
+LOAD /tmp/ccy5lZmy.o
LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020001000 _estack = 0x20001000
.isr_vector 0x0000000008000000 0xc0
0x0000000008000000 . = ALIGN (0x4)
*(.isr_vector)
- .isr_vector 0x0000000008000000 0xc0 /tmp/ccr2qryM.o
+ .isr_vector 0x0000000008000000 0xc0 /tmp/ccjaIjJQ.o
0x0000000008000000 g_pfnVectors
0x00000000080000c0 . = ALIGN (0x4)
-.text 0x00000000080000c0 0x18fc
+.text 0x00000000080000c0 0x1ba4
0x00000000080000c0 . = ALIGN (0x4)
*(.text)
- .text 0x00000000080000c0 0x428 /tmp/ccxtvPlT.o
+ .text 0x00000000080000c0 0x428 /tmp/ccy8OCeb.o
0x0000000008000210 update_leds
0x000000000800021a main
0x000000000800039c SPI1_IRQHandler
@@ -57,119 +56,118 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000008000494 SVC_Handler
0x00000000080004a0 PendSV_Handler
0x00000000080004ac SysTick_Handler
- .text 0x00000000080004e8 0x2e4 /tmp/ccrrpgrR.o
+ .text 0x00000000080004e8 0x334 /tmp/cc6Un0Q5.o
0x00000000080005f0 adc_configure_scope_mode
- 0x0000000008000762 DMA1_Channel1_IRQHandler
- .text 0x00000000080007cc 0x3a4 /tmp/ccXNIrIP.o
- 0x0000000008000904 usart_dma_init
- 0x00000000080009f8 usart_dma_fifo_push
- 0x0000000008000a50 usart_putc
- 0x0000000008000a80 usart_putc_nonblocking
- 0x0000000008000aa8 DMA1_Channel2_3_IRQHandler
- 0x0000000008000ae8 usart_send_packet
- 0x0000000008000b1c usart_send_packet_nonblocking
- .text 0x0000000008000b70 0x358 /tmp/ccy0xC7N.o
- 0x0000000008000b70 cobs_encode
- 0x0000000008000c36 cobs_encode_usart
- 0x0000000008000cf4 cobs_decode
- 0x0000000008000dca cobs_decode_incremental_initialize
- 0x0000000008000de6 cobs_decode_incremental
- .text 0x0000000008000ec8 0x14 /tmp/ccr2qryM.o
- .text 0x0000000008000edc 0x174 /tmp/ccJ50X5K.o
- 0x0000000008000edc SystemInit
- 0x0000000008000f64 SystemCoreClockUpdate
- .text 0x0000000008001050 0x594 /tmp/ccFUXyQJ.o
- 0x00000000080012a4 LL_Init1msTick
- 0x00000000080012c2 LL_mDelay
- 0x0000000008001308 LL_SetSystemCoreClock
- 0x0000000008001324 LL_PLL_ConfigSystemClock_HSI
- 0x00000000080013b0 LL_PLL_ConfigSystemClock_HSE
- .text 0x00000000080015e4 0x82 /tmp/cc8rJnLI.o
- 0x00000000080015e4 __sinit
- 0x00000000080015ee memset
- 0x0000000008001628 strlen
- 0x0000000008001652 __assert_func
- .text 0x0000000008001666 0x0 /tmp/ccDd2fMH.o
- *fill* 0x0000000008001666 0x2
- .text 0x0000000008001668 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- 0x0000000008001668 __udivsi3
- 0x0000000008001668 __aeabi_uidiv
- 0x0000000008001774 __aeabi_uidivmod
- .text 0x000000000800177c 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- 0x000000000800177c __aeabi_idiv
- 0x000000000800177c __divsi3
- 0x0000000008001948 __aeabi_idivmod
- .text 0x0000000008001950 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
- 0x0000000008001950 __aeabi_ldiv0
- 0x0000000008001950 __aeabi_idiv0
+ 0x000000000800079a DMA1_Channel1_IRQHandler
+ .text 0x000000000800081c 0x6c0 /tmp/ccRRCPG0.o
+ 0x0000000008000954 usart_dma_init
+ 0x0000000008000a28 USART1_IRQHandler
+ 0x0000000008000bc4 usart_ack_packet
+ 0x0000000008000c00 usart_dma_fifo_push
+ 0x0000000008000c78 usart_putc
+ 0x0000000008000cd0 DMA1_Channel2_3_IRQHandler
+ 0x0000000008000dbc usart_send_packet_nonblocking
+ .text 0x0000000008000edc 0x292 /tmp/ccWI4kHV.o
+ 0x0000000008000edc cobs_encode_usart
+ 0x0000000008000f9a cobs_decode
+ 0x0000000008001070 cobs_decode_incremental_initialize
+ 0x000000000800108c cobs_decode_incremental
+ .text 0x000000000800116e 0x14 /tmp/ccjaIjJQ.o
+ *fill* 0x0000000008001182 0x2
+ .text 0x0000000008001184 0x174 /tmp/cceYjaVL.o
+ 0x0000000008001184 SystemInit
+ 0x000000000800120c SystemCoreClockUpdate
+ .text 0x00000000080012f8 0x594 /tmp/ccsXJViH.o
+ 0x000000000800154c LL_Init1msTick
+ 0x000000000800156a LL_mDelay
+ 0x00000000080015b0 LL_SetSystemCoreClock
+ 0x00000000080015cc LL_PLL_ConfigSystemClock_HSI
+ 0x0000000008001658 LL_PLL_ConfigSystemClock_HSE
+ .text 0x000000000800188c 0x82 /tmp/ccGz0VMC.o
+ 0x000000000800188c __sinit
+ 0x0000000008001896 memset
+ 0x00000000080018d0 strlen
+ 0x00000000080018fa __assert_func
+ .text 0x000000000800190e 0x0 /tmp/ccy5lZmy.o
+ *fill* 0x000000000800190e 0x2
+ .text 0x0000000008001910 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ 0x0000000008001910 __udivsi3
+ 0x0000000008001910 __aeabi_uidiv
+ 0x0000000008001a1c __aeabi_uidivmod
+ .text 0x0000000008001a24 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ 0x0000000008001a24 __aeabi_idiv
+ 0x0000000008001a24 __divsi3
+ 0x0000000008001bf0 __aeabi_idivmod
+ .text 0x0000000008001bf8 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ 0x0000000008001bf8 __aeabi_ldiv0
+ 0x0000000008001bf8 __aeabi_idiv0
*(.text.*)
.text.Reset_Handler
- 0x0000000008001954 0x4c /tmp/ccr2qryM.o
- 0x0000000008001954 Reset_Handler
+ 0x0000000008001bfc 0x4c /tmp/ccjaIjJQ.o
+ 0x0000000008001bfc Reset_Handler
.text.Default_Handler
- 0x00000000080019a0 0x2 /tmp/ccr2qryM.o
- 0x00000000080019a0 TIM1_CC_IRQHandler
- 0x00000000080019a0 I2C1_IRQHandler
- 0x00000000080019a0 EXTI2_3_IRQHandler
- 0x00000000080019a0 ADC1_IRQHandler
- 0x00000000080019a0 TIM17_IRQHandler
- 0x00000000080019a0 RTC_IRQHandler
- 0x00000000080019a0 TIM3_IRQHandler
- 0x00000000080019a0 EXTI4_15_IRQHandler
- 0x00000000080019a0 RCC_IRQHandler
- 0x00000000080019a0 Default_Handler
- 0x00000000080019a0 TIM14_IRQHandler
- 0x00000000080019a0 DMA1_Channel4_5_IRQHandler
- 0x00000000080019a0 EXTI0_1_IRQHandler
- 0x00000000080019a0 WWDG_IRQHandler
- 0x00000000080019a0 FLASH_IRQHandler
- 0x00000000080019a0 USART1_IRQHandler
- 0x00000000080019a0 TIM1_BRK_UP_TRG_COM_IRQHandler
+ 0x0000000008001c48 0x2 /tmp/ccjaIjJQ.o
+ 0x0000000008001c48 TIM1_CC_IRQHandler
+ 0x0000000008001c48 I2C1_IRQHandler
+ 0x0000000008001c48 EXTI2_3_IRQHandler
+ 0x0000000008001c48 ADC1_IRQHandler
+ 0x0000000008001c48 TIM17_IRQHandler
+ 0x0000000008001c48 RTC_IRQHandler
+ 0x0000000008001c48 TIM3_IRQHandler
+ 0x0000000008001c48 EXTI4_15_IRQHandler
+ 0x0000000008001c48 RCC_IRQHandler
+ 0x0000000008001c48 Default_Handler
+ 0x0000000008001c48 TIM14_IRQHandler
+ 0x0000000008001c48 DMA1_Channel4_5_IRQHandler
+ 0x0000000008001c48 EXTI0_1_IRQHandler
+ 0x0000000008001c48 WWDG_IRQHandler
+ 0x0000000008001c48 FLASH_IRQHandler
+ 0x0000000008001c48 TIM1_BRK_UP_TRG_COM_IRQHandler
*(.rodata)
- *fill* 0x00000000080019a2 0x2
- .rodata 0x00000000080019a4 0x18 /tmp/ccJ50X5K.o
- 0x00000000080019a4 AHBPrescTable
- 0x00000000080019b4 APBPrescTable
+ *fill* 0x0000000008001c4a 0x2
+ .rodata 0x0000000008001c4c 0x18 /tmp/cceYjaVL.o
+ 0x0000000008001c4c AHBPrescTable
+ 0x0000000008001c5c APBPrescTable
*(.rodata*)
*(.glue_7)
- .glue_7 0x00000000080019bc 0x0 linker stubs
+ .glue_7 0x0000000008001c64 0x0 linker stubs
*(.glue_7t)
- .glue_7t 0x00000000080019bc 0x0 linker stubs
+ .glue_7t 0x0000000008001c64 0x0 linker stubs
*(.source_tarball)
*(.init)
*(.fini)
*(.source_tarball)
- 0x00000000080019bc . = ALIGN (0x4)
- 0x00000000080019bc _etext = .
- 0x00000000080019bc _sidata = _etext
+ 0x0000000008001c64 . = ALIGN (0x4)
+ 0x0000000008001c64 _etext = .
+ 0x0000000008001c64 _sidata = _etext
-.vfp11_veneer 0x00000000080019bc 0x0
- .vfp11_veneer 0x00000000080019bc 0x0 linker stubs
+.vfp11_veneer 0x0000000008001c64 0x0
+ .vfp11_veneer 0x0000000008001c64 0x0 linker stubs
-.v4_bx 0x00000000080019bc 0x0
- .v4_bx 0x00000000080019bc 0x0 linker stubs
+.v4_bx 0x0000000008001c64 0x0
+ .v4_bx 0x0000000008001c64 0x0 linker stubs
-.iplt 0x00000000080019bc 0x0
- .iplt 0x00000000080019bc 0x0 /tmp/ccxtvPlT.o
+.iplt 0x0000000008001c64 0x0
+ .iplt 0x0000000008001c64 0x0 /tmp/ccy8OCeb.o
-.rel.dyn 0x00000000080019bc 0x0
- .rel.iplt 0x00000000080019bc 0x0 /tmp/ccxtvPlT.o
+.rel.dyn 0x0000000008001c64 0x0
+ .rel.iplt 0x0000000008001c64 0x0 /tmp/ccy8OCeb.o
-.data 0x0000000020000000 0x94 load address 0x00000000080019bc
+.data 0x0000000020000000 0x94 load address 0x0000000008001c64
0x0000000020000000 . = ALIGN (0x4)
0x0000000020000000 _sdata = .
0x0000000020000000 _data = .
*(.data)
- .data 0x0000000020000000 0x0 /tmp/ccxtvPlT.o
- .data 0x0000000020000000 0x0 /tmp/ccrrpgrR.o
- .data 0x0000000020000000 0x0 /tmp/ccXNIrIP.o
- .data 0x0000000020000000 0x0 /tmp/ccy0xC7N.o
- .data 0x0000000020000000 0x0 /tmp/ccr2qryM.o
- .data 0x0000000020000000 0x4 /tmp/ccJ50X5K.o
+ .data 0x0000000020000000 0x0 /tmp/ccy8OCeb.o
+ .data 0x0000000020000000 0x0 /tmp/cc6Un0Q5.o
+ .data 0x0000000020000000 0x0 /tmp/ccRRCPG0.o
+ .data 0x0000000020000000 0x0 /tmp/ccWI4kHV.o
+ .data 0x0000000020000000 0x0 /tmp/ccjaIjJQ.o
+ .data 0x0000000020000000 0x4 /tmp/cceYjaVL.o
0x0000000020000000 SystemCoreClock
- .data 0x0000000020000004 0x0 /tmp/ccFUXyQJ.o
- .data 0x0000000020000004 0x0 /tmp/cc8rJnLI.o
- .data 0x0000000020000004 0x90 /tmp/ccDd2fMH.o
+ .data 0x0000000020000004 0x0 /tmp/ccsXJViH.o
+ .data 0x0000000020000004 0x0 /tmp/ccGz0VMC.o
+ .data 0x0000000020000004 0x90 /tmp/ccy5lZmy.o
0x0000000020000004 tim3
0x0000000020000008 tim14
0x000000002000000c rtc
@@ -214,45 +212,41 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _edata = .
-.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001a50
- .igot.plt 0x0000000020000094 0x0 /tmp/ccxtvPlT.o
+.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001cf8
+ .igot.plt 0x0000000020000094 0x0 /tmp/ccy8OCeb.o
-.bss 0x0000000020000094 0x488 load address 0x0000000008001a50
+.bss 0x0000000020000094 0x324 load address 0x0000000008001cf8
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _sbss = .
0x0000000020000094 _bss = .
*(.bss)
- .bss 0x0000000020000094 0xc /tmp/ccxtvPlT.o
+ .bss 0x0000000020000094 0xc /tmp/ccy8OCeb.o
0x0000000020000094 sys_time_seconds
- .bss 0x00000000200000a0 0x4 /tmp/ccrrpgrR.o
- 0x00000000200000a0 usart_overruns
- .bss 0x00000000200000a4 0x1 /tmp/ccXNIrIP.o
- .bss 0x00000000200000a5 0x0 /tmp/ccy0xC7N.o
- .bss 0x00000000200000a5 0x0 /tmp/ccr2qryM.o
- .bss 0x00000000200000a5 0x0 /tmp/ccJ50X5K.o
- .bss 0x00000000200000a5 0x0 /tmp/ccFUXyQJ.o
- *fill* 0x00000000200000a5 0x3
- .bss 0x00000000200000a8 0x8 /tmp/cc8rJnLI.o
- 0x00000000200000a8 __errno
- 0x00000000200000ac _impure_ptr
- .bss 0x00000000200000b0 0x0 /tmp/ccDd2fMH.o
- .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .bss 0x00000000200000a0 0x98 /tmp/cc6Un0Q5.o
+ .bss 0x0000000020000138 0x38 /tmp/ccRRCPG0.o
+ .bss 0x0000000020000170 0x0 /tmp/ccWI4kHV.o
+ .bss 0x0000000020000170 0x0 /tmp/ccjaIjJQ.o
+ .bss 0x0000000020000170 0x0 /tmp/cceYjaVL.o
+ .bss 0x0000000020000170 0x0 /tmp/ccsXJViH.o
+ .bss 0x0000000020000170 0x8 /tmp/ccGz0VMC.o
+ 0x0000000020000170 __errno
+ 0x0000000020000174 _impure_ptr
+ .bss 0x0000000020000178 0x0 /tmp/ccy5lZmy.o
+ .bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
*(.bss.*)
*(COMMON)
- COMMON 0x00000000200000b0 0x20 /tmp/ccxtvPlT.o
- 0x00000000200000b0 leds
- COMMON 0x00000000200000d0 0x40 /tmp/ccrrpgrR.o
- 0x00000000200000d0 adc_buf
- COMMON 0x0000000020000110 0x40c /tmp/ccXNIrIP.o
- 0x0000000020000110 usart_tx_buf
- 0x000000002000051c . = ALIGN (0x4)
- 0x000000002000051c _ebss = .
+ COMMON 0x0000000020000178 0x20 /tmp/ccy8OCeb.o
+ 0x0000000020000178 leds
+ COMMON 0x0000000020000198 0x220 /tmp/ccRRCPG0.o
+ 0x0000000020000198 usart_tx_buf
+ 0x00000000200003b8 . = ALIGN (0x4)
+ 0x00000000200003b8 _ebss = .
[!provide] PROVIDE (end = _ebss)
[!provide] PROVIDE (_end = _ebss)
- 0x000000002000051c __exidx_start = .
- 0x000000002000051c __exidx_end = .
+ 0x00000000200003b8 __exidx_start = .
+ 0x00000000200003b8 __exidx_end = .
.stab
*(.stab)
@@ -274,36 +268,36 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.comment 0x0000000000000000 0x21
*(.comment)
- .comment 0x0000000000000000 0x21 /tmp/ccxtvPlT.o
+ .comment 0x0000000000000000 0x21 /tmp/ccy8OCeb.o
0x22 (size before relaxing)
- .comment 0x0000000000000021 0x22 /tmp/ccrrpgrR.o
- .comment 0x0000000000000021 0x22 /tmp/ccXNIrIP.o
- .comment 0x0000000000000021 0x22 /tmp/ccy0xC7N.o
- .comment 0x0000000000000021 0x22 /tmp/ccJ50X5K.o
- .comment 0x0000000000000021 0x22 /tmp/ccFUXyQJ.o
- .comment 0x0000000000000021 0x22 /tmp/cc8rJnLI.o
- .comment 0x0000000000000021 0x22 /tmp/ccDd2fMH.o
+ .comment 0x0000000000000021 0x22 /tmp/cc6Un0Q5.o
+ .comment 0x0000000000000021 0x22 /tmp/ccRRCPG0.o
+ .comment 0x0000000000000021 0x22 /tmp/ccWI4kHV.o
+ .comment 0x0000000000000021 0x22 /tmp/cceYjaVL.o
+ .comment 0x0000000000000021 0x22 /tmp/ccsXJViH.o
+ .comment 0x0000000000000021 0x22 /tmp/ccGz0VMC.o
+ .comment 0x0000000000000021 0x22 /tmp/ccy5lZmy.o
.ARM.attributes
0x0000000000000000 0x2f
.ARM.attributes
- 0x0000000000000000 0x2b /tmp/ccxtvPlT.o
+ 0x0000000000000000 0x2b /tmp/ccy8OCeb.o
.ARM.attributes
- 0x000000000000002b 0x2b /tmp/ccrrpgrR.o
+ 0x000000000000002b 0x2b /tmp/cc6Un0Q5.o
.ARM.attributes
- 0x0000000000000056 0x2b /tmp/ccXNIrIP.o
+ 0x0000000000000056 0x2b /tmp/ccRRCPG0.o
.ARM.attributes
- 0x0000000000000081 0x2b /tmp/ccy0xC7N.o
+ 0x0000000000000081 0x2b /tmp/ccWI4kHV.o
.ARM.attributes
- 0x00000000000000ac 0x21 /tmp/ccr2qryM.o
+ 0x00000000000000ac 0x21 /tmp/ccjaIjJQ.o
.ARM.attributes
- 0x00000000000000cd 0x2b /tmp/ccJ50X5K.o
+ 0x00000000000000cd 0x2b /tmp/cceYjaVL.o
.ARM.attributes
- 0x00000000000000f8 0x2b /tmp/ccFUXyQJ.o
+ 0x00000000000000f8 0x2b /tmp/ccsXJViH.o
.ARM.attributes
- 0x0000000000000123 0x2b /tmp/cc8rJnLI.o
+ 0x0000000000000123 0x2b /tmp/ccGz0VMC.o
.ARM.attributes
- 0x000000000000014e 0x31 /tmp/ccDd2fMH.o
+ 0x000000000000014e 0x31 /tmp/ccy5lZmy.o
.ARM.attributes
0x000000000000017f 0x1e /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.ARM.attributes
@@ -326,23 +320,23 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_aranges 0x0000000000000000 0x180
*(.debug_aranges)
.debug_aranges
- 0x0000000000000000 0x20 /tmp/ccxtvPlT.o
+ 0x0000000000000000 0x20 /tmp/ccy8OCeb.o
.debug_aranges
- 0x0000000000000020 0x20 /tmp/ccrrpgrR.o
+ 0x0000000000000020 0x20 /tmp/cc6Un0Q5.o
.debug_aranges
- 0x0000000000000040 0x20 /tmp/ccXNIrIP.o
+ 0x0000000000000040 0x20 /tmp/ccRRCPG0.o
.debug_aranges
- 0x0000000000000060 0x20 /tmp/ccy0xC7N.o
+ 0x0000000000000060 0x20 /tmp/ccWI4kHV.o
.debug_aranges
- 0x0000000000000080 0x28 /tmp/ccr2qryM.o
+ 0x0000000000000080 0x28 /tmp/ccjaIjJQ.o
.debug_aranges
- 0x00000000000000a8 0x20 /tmp/ccJ50X5K.o
+ 0x00000000000000a8 0x20 /tmp/cceYjaVL.o
.debug_aranges
- 0x00000000000000c8 0x20 /tmp/ccFUXyQJ.o
+ 0x00000000000000c8 0x20 /tmp/ccsXJViH.o
.debug_aranges
- 0x00000000000000e8 0x20 /tmp/cc8rJnLI.o
+ 0x00000000000000e8 0x20 /tmp/ccGz0VMC.o
.debug_aranges
- 0x0000000000000108 0x18 /tmp/ccDd2fMH.o
+ 0x0000000000000108 0x18 /tmp/ccy5lZmy.o
.debug_aranges
0x0000000000000120 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.debug_aranges
@@ -353,87 +347,87 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_pubnames
*(.debug_pubnames)
-.debug_info 0x0000000000000000 0x5eaf
+.debug_info 0x0000000000000000 0x62e5
*(.debug_info .gnu.linkonce.wi.*)
- .debug_info 0x0000000000000000 0x12f8 /tmp/ccxtvPlT.o
- .debug_info 0x00000000000012f8 0x1129 /tmp/ccrrpgrR.o
- .debug_info 0x0000000000002421 0x10a6 /tmp/ccXNIrIP.o
- .debug_info 0x00000000000034c7 0xcf2 /tmp/ccy0xC7N.o
- .debug_info 0x00000000000041b9 0x22 /tmp/ccr2qryM.o
- .debug_info 0x00000000000041db 0x263 /tmp/ccJ50X5K.o
- .debug_info 0x000000000000443e 0x795 /tmp/ccFUXyQJ.o
- .debug_info 0x0000000000004bd3 0x1e9 /tmp/cc8rJnLI.o
- .debug_info 0x0000000000004dbc 0x1081 /tmp/ccDd2fMH.o
- .debug_info 0x0000000000005e3d 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_info 0x0000000000005e63 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_info 0x0000000000005e89 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_abbrev 0x0000000000000000 0x1221
+ .debug_info 0x0000000000000000 0x132d /tmp/ccy8OCeb.o
+ .debug_info 0x000000000000132d 0x11f5 /tmp/cc6Un0Q5.o
+ .debug_info 0x0000000000002522 0x13c6 /tmp/ccRRCPG0.o
+ .debug_info 0x00000000000038e8 0xd07 /tmp/ccWI4kHV.o
+ .debug_info 0x00000000000045ef 0x22 /tmp/ccjaIjJQ.o
+ .debug_info 0x0000000000004611 0x263 /tmp/cceYjaVL.o
+ .debug_info 0x0000000000004874 0x795 /tmp/ccsXJViH.o
+ .debug_info 0x0000000000005009 0x1e9 /tmp/ccGz0VMC.o
+ .debug_info 0x00000000000051f2 0x1081 /tmp/ccy5lZmy.o
+ .debug_info 0x0000000000006273 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_info 0x0000000000006299 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_info 0x00000000000062bf 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_abbrev 0x0000000000000000 0x12ad
*(.debug_abbrev)
- .debug_abbrev 0x0000000000000000 0x355 /tmp/ccxtvPlT.o
- .debug_abbrev 0x0000000000000355 0x322 /tmp/ccrrpgrR.o
- .debug_abbrev 0x0000000000000677 0x32d /tmp/ccXNIrIP.o
- .debug_abbrev 0x00000000000009a4 0x290 /tmp/ccy0xC7N.o
- .debug_abbrev 0x0000000000000c34 0x12 /tmp/ccr2qryM.o
- .debug_abbrev 0x0000000000000c46 0x113 /tmp/ccJ50X5K.o
- .debug_abbrev 0x0000000000000d59 0x23c /tmp/ccFUXyQJ.o
- .debug_abbrev 0x0000000000000f95 0x117 /tmp/cc8rJnLI.o
- .debug_abbrev 0x00000000000010ac 0x139 /tmp/ccDd2fMH.o
- .debug_abbrev 0x00000000000011e5 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_abbrev 0x00000000000011f9 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_abbrev 0x000000000000120d 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_line 0x0000000000000000 0x1806
+ .debug_abbrev 0x0000000000000000 0x34c /tmp/ccy8OCeb.o
+ .debug_abbrev 0x000000000000034c 0x314 /tmp/cc6Un0Q5.o
+ .debug_abbrev 0x0000000000000660 0x3ec /tmp/ccRRCPG0.o
+ .debug_abbrev 0x0000000000000a4c 0x274 /tmp/ccWI4kHV.o
+ .debug_abbrev 0x0000000000000cc0 0x12 /tmp/ccjaIjJQ.o
+ .debug_abbrev 0x0000000000000cd2 0x113 /tmp/cceYjaVL.o
+ .debug_abbrev 0x0000000000000de5 0x23c /tmp/ccsXJViH.o
+ .debug_abbrev 0x0000000000001021 0x117 /tmp/ccGz0VMC.o
+ .debug_abbrev 0x0000000000001138 0x139 /tmp/ccy5lZmy.o
+ .debug_abbrev 0x0000000000001271 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_abbrev 0x0000000000001285 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_abbrev 0x0000000000001299 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_line 0x0000000000000000 0x198f
*(.debug_line)
- .debug_line 0x0000000000000000 0x3cb /tmp/ccxtvPlT.o
- .debug_line 0x00000000000003cb 0x363 /tmp/ccrrpgrR.o
- .debug_line 0x000000000000072e 0x3b2 /tmp/ccXNIrIP.o
- .debug_line 0x0000000000000ae0 0x305 /tmp/ccy0xC7N.o
- .debug_line 0x0000000000000de5 0x77 /tmp/ccr2qryM.o
- .debug_line 0x0000000000000e5c 0x1ab /tmp/ccJ50X5K.o
- .debug_line 0x0000000000001007 0x466 /tmp/ccFUXyQJ.o
- .debug_line 0x000000000000146d 0xf4 /tmp/cc8rJnLI.o
- .debug_line 0x0000000000001561 0x148 /tmp/ccDd2fMH.o
- .debug_line 0x00000000000016a9 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_line 0x000000000000171f 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_line 0x000000000000179c 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_frame 0x0000000000000000 0x888
+ .debug_line 0x0000000000000000 0x3d6 /tmp/ccy8OCeb.o
+ .debug_line 0x00000000000003d6 0x37f /tmp/cc6Un0Q5.o
+ .debug_line 0x0000000000000755 0x51f /tmp/ccRRCPG0.o
+ .debug_line 0x0000000000000c74 0x2fa /tmp/ccWI4kHV.o
+ .debug_line 0x0000000000000f6e 0x77 /tmp/ccjaIjJQ.o
+ .debug_line 0x0000000000000fe5 0x1ab /tmp/cceYjaVL.o
+ .debug_line 0x0000000000001190 0x466 /tmp/ccsXJViH.o
+ .debug_line 0x00000000000015f6 0xf4 /tmp/ccGz0VMC.o
+ .debug_line 0x00000000000016ea 0x148 /tmp/ccy5lZmy.o
+ .debug_line 0x0000000000001832 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_line 0x00000000000018a8 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_line 0x0000000000001925 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_frame 0x0000000000000000 0x8c4
*(.debug_frame)
- .debug_frame 0x0000000000000000 0x164 /tmp/ccxtvPlT.o
- .debug_frame 0x0000000000000164 0xec /tmp/ccrrpgrR.o
- .debug_frame 0x0000000000000250 0x168 /tmp/ccXNIrIP.o
- .debug_frame 0x00000000000003b8 0xb0 /tmp/ccy0xC7N.o
- .debug_frame 0x0000000000000468 0x4c /tmp/ccJ50X5K.o
- .debug_frame 0x00000000000004b4 0x308 /tmp/ccFUXyQJ.o
- .debug_frame 0x00000000000007bc 0x8c /tmp/cc8rJnLI.o
- .debug_frame 0x0000000000000848 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_frame 0x0000000000000868 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
-
-.debug_str 0x0000000000000000 0x12fd
+ .debug_frame 0x0000000000000000 0x164 /tmp/ccy8OCeb.o
+ .debug_frame 0x0000000000000164 0x104 /tmp/cc6Un0Q5.o
+ .debug_frame 0x0000000000000268 0x1ac /tmp/ccRRCPG0.o
+ .debug_frame 0x0000000000000414 0x90 /tmp/ccWI4kHV.o
+ .debug_frame 0x00000000000004a4 0x4c /tmp/cceYjaVL.o
+ .debug_frame 0x00000000000004f0 0x308 /tmp/ccsXJViH.o
+ .debug_frame 0x00000000000007f8 0x8c /tmp/ccGz0VMC.o
+ .debug_frame 0x0000000000000884 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame 0x00000000000008a4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+
+.debug_str 0x0000000000000000 0x1404
*(.debug_str)
- .debug_str 0x0000000000000000 0x952 /tmp/ccxtvPlT.o
- 0x9f5 (size before relaxing)
- .debug_str 0x0000000000000952 0x101 /tmp/ccrrpgrR.o
- 0x95f (size before relaxing)
- .debug_str 0x0000000000000a53 0xdc /tmp/ccXNIrIP.o
- 0x939 (size before relaxing)
- .debug_str 0x0000000000000b2f 0xa9 /tmp/ccy0xC7N.o
- 0x65f (size before relaxing)
- .debug_str 0x0000000000000bd8 0x22 /tmp/ccr2qryM.o
+ .debug_str 0x0000000000000000 0x968 /tmp/ccy8OCeb.o
+ 0xa13 (size before relaxing)
+ .debug_str 0x0000000000000968 0x125 /tmp/cc6Un0Q5.o
+ 0x9a9 (size before relaxing)
+ .debug_str 0x0000000000000a8d 0x1e1 /tmp/ccRRCPG0.o
+ 0xa79 (size before relaxing)
+ .debug_str 0x0000000000000c6e 0x82 /tmp/ccWI4kHV.o
+ 0x6ba (size before relaxing)
+ .debug_str 0x0000000000000cf0 0x22 /tmp/ccjaIjJQ.o
0x57 (size before relaxing)
- .debug_str 0x0000000000000bfa 0x53 /tmp/ccJ50X5K.o
+ .debug_str 0x0000000000000d12 0x53 /tmp/cceYjaVL.o
0x219 (size before relaxing)
- .debug_str 0x0000000000000c4d 0x3ae /tmp/ccFUXyQJ.o
+ .debug_str 0x0000000000000d65 0x3ae /tmp/ccsXJViH.o
0x5bf (size before relaxing)
- .debug_str 0x0000000000000ffb 0x39 /tmp/cc8rJnLI.o
+ .debug_str 0x0000000000001113 0x39 /tmp/ccGz0VMC.o
0x1b7 (size before relaxing)
- .debug_str 0x0000000000001034 0x227 /tmp/ccDd2fMH.o
+ .debug_str 0x000000000000114c 0x216 /tmp/ccy5lZmy.o
0x5ca (size before relaxing)
- .debug_str 0x000000000000125b 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_str 0x0000000000001362 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
0xae (size before relaxing)
- .debug_str 0x00000000000012fd 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_str 0x00000000000012fd 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .debug_str 0x0000000000001404 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_str 0x0000000000001404 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
.debug_loc
*(.debug_loc)
@@ -455,5 +449,5 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
OUTPUT(main.elf elf32-littlearm)
.debug_ranges 0x0000000000000000 0x38
- .debug_ranges 0x0000000000000000 0x18 /tmp/ccy0xC7N.o
- .debug_ranges 0x0000000000000018 0x20 /tmp/ccr2qryM.o
+ .debug_ranges 0x0000000000000000 0x18 /tmp/ccWI4kHV.o
+ .debug_ranges 0x0000000000000018 0x20 /tmp/ccjaIjJQ.o
diff --git a/gm_platform/fw/serial.c b/gm_platform/fw/serial.c
index 468c523..178d6f9 100644
--- a/gm_platform/fw/serial.c
+++ b/gm_platform/fw/serial.c
@@ -31,14 +31,27 @@
volatile struct dma_tx_buf usart_tx_buf;
+static uint32_t tx_overruns=0, rx_overruns=0;
+static uint32_t rx_framing_errors=0, rx_protocol_errors=0;
+
+static struct cobs_decode_state cobs_state;
+
+static volatile uint8_t rx_buf[32];
+
+
static void usart_schedule_dma(void);
-int usart_putc_nonblocking(char c);
-int usart_putc(char c);
+static int usart_putc_nonblocking(uint8_t c);
+static int usart_retransmit_packet(uint8_t idx);
+
void usart_dma_init() {
- usart_tx_buf.xfr_start = -1,
- usart_tx_buf.xfr_end = 0,
- usart_tx_buf.wr_pos = 0,
+ usart_tx_buf.xfr_start = -1;
+ usart_tx_buf.xfr_end = 0;
+ usart_tx_buf.wr_pos = 0;
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ usart_tx_buf.packet_start[i] = -1;
+
+ cobs_decode_incremental_initialize(&cobs_state);
/* Configure DMA 1 Channel 2 to handle uart transmission */
DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
@@ -74,7 +87,7 @@ void usart_dma_init() {
//USART1->BRR = 417;
//USART1->BRR = 48; /* 1MBd */
- USART1->BRR = 96; /* 500kBd */
+ //USART1->BRR = 96; /* 500kBd */
USART1->BRR = 192; /* 250kBd */
//USART1->BRR = 208; /* 230400 */
@@ -83,19 +96,72 @@ void usart_dma_init() {
USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
/* Enable receive interrupt */
- //NVIC_EnableIRQ(USART1_IRQn);
- //NVIC_SetPriority(USART1_IRQn, 1);
+ NVIC_EnableIRQ(USART1_IRQn);
+ NVIC_SetPriority(USART1_IRQn, 3<<5);
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
}
+void USART1_IRQHandler() {
+ uint32_t isr = USART1->ISR;
+
+ if (isr & USART_ISR_ORE) {
+ USART1->ICR = USART_ICR_ORECF;
+ rx_overruns++;
+ return;
+ }
+
+ if (isr & USART_ISR_RXNE) {
+ uint8_t c = USART1->RDR;
+
+ int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c);
+ if (rc == 0) /* packet still incomplete */
+ return;
+
+ if (rc < 0) {
+ rx_framing_errors++;
+ return;
+ }
+
+ /* A complete frame received */
+ if (rc != 2) {
+ rx_protocol_errors++;
+ return;
+ }
+
+ volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf;
+
+ switch (pkt->type) {
+ case CTRL_PKT_RESET:
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
+ usart_tx_buf.packet_start[i] = -1;
+ break;
+
+ case CTRL_PKT_ACK:
+ if (usart_ack_packet(pkt->orig_id))
+ rx_protocol_errors++;
+ break;
+
+ case CTRL_PKT_RETRANSMIT:
+ if (usart_retransmit_packet(pkt->orig_id))
+ rx_protocol_errors++;
+ break;
+
+ default:
+ rx_protocol_errors++;
+ }
+ return;
+ }
+}
+
+
void usart_schedule_dma() {
/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
- size_t xfr_len, xfr_start = buf->xfr_end;
+ ssize_t xfr_len, xfr_start = buf->xfr_end;
if (buf->wr_pos > xfr_start) /* no wraparound */
xfr_len = buf->wr_pos - xfr_start;
else /* wraparound */
@@ -110,15 +176,28 @@ void usart_schedule_dma() {
DMA1_Channel2->CCR |= DMA_CCR_EN;
}
-int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) {
+int usart_ack_packet(uint8_t idx) {
+ if (idx > ARRAY_LEN(usart_tx_buf.packet_start))
+ return -EINVAL;
+
+ usart_tx_buf.packet_start[idx] = -1;
+ return 0;
+}
+
+int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
- if (buf->wr_pos == buf->xfr_start) {
- NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- return -EBUSY;
+ /* If the write pointer hit any unacknowledged packet start position we can't advance it.
+ * Packet start positions are unordered and we have to scan here. */
+ for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
+ if (buf->wr_pos == buf->packet_start[i]) {
+ NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ return -EBUSY;
+ }
}
+ /* write byte, then increment to avoid racing the DMA ISR reading wr_pos */
buf->data[buf->wr_pos] = c;
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
@@ -126,7 +205,7 @@ int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) {
return 0;
}
-int usart_putc(char c) {
+int usart_putc(uint8_t c) {
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
/* idle */
@@ -134,7 +213,7 @@ int usart_putc(char c) {
return 0;
}
-int usart_putc_nonblocking(char c) {
+int usart_putc_nonblocking(uint8_t c) {
return usart_dma_fifo_push(&usart_tx_buf, c);
}
@@ -148,26 +227,70 @@ void DMA1_Channel2_3_IRQHandler(void) {
usart_schedule_dma();
}
-void usart_send_packet(const uint8_t *data, size_t len) {
- /* ignore return value as putf is blocking and always succeeds */
- (void)cobs_encode_usart(usart_putc, (char *)data, len);
+int usart_retransmit_packet(uint8_t idx) {
+ /* Disable ADC DMA IRQ to prevent write races */
+ NVIC_DisableIRQ(DMA1_Channel1_IRQn);
- /* If the DMA stream is idle right now, schedule a transfer */
- if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
- usart_schedule_dma();
+ ssize_t i = usart_tx_buf.packet_start[idx];
+ ssize_t start = i;
+
+ /* Copy packet */
+ uint8_t c;
+ while ((c = usart_tx_buf.data[i++])) {
+ if (usart_putc_nonblocking(c)) {
+ tx_overruns++;
+ return -EBUSY;
+ }
+ }
+
+ /* Terminating null byte */
+ if (usart_putc_nonblocking(0)) {
+ tx_overruns++;
+ return -EBUSY;
+ }
+
+ /* Update start index */
+ usart_tx_buf.packet_start[idx] = start;
+
+ NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+ return 0;
}
-int usart_send_packet_nonblocking(const uint8_t *data, size_t len) {
- /* ignore return value as putf is blocking and always succeeds */
- /* FIXME DEBUG */
- //int rc = cobs_encode_usart(usart_putc_nonblocking, (char *)data, len);
- //if (rc)
- // return rc;
- /* END */
+/* len is the packet length including headers */
+int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
+
+ ssize_t start = usart_tx_buf.wr_pos;
+ /* Find a free slot for this packet */
+ size_t packet_idx = 0;
+ do {
+ if (usart_tx_buf.packet_start[packet_idx] == -1)
+ goto success;
+ } while (++packet_idx <ARRAY_LEN(usart_tx_buf.packet_start));
+
+ tx_overruns++;
+ return -EBUSY;
+
+success:
+ pkt->pid = packet_idx;
+ pkt->_pad = 0;
+
+ /* make the value this wonky-ass CRC implementation produces match zlib etc. */
+ CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET;
+ for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
+ CRC->DR = ((uint8_t *)pkt)[i];
+
+ pkt->crc32 = ~CRC->DR;
+ int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
+ if (rc)
+ return rc;
+
+ /* Checkpoint packet start index to prevent overwriting before ack */
+ usart_tx_buf.packet_start[packet_idx] = start;
+ /* FIXME debug code
static uint8_t x = 0;
-
for (size_t i=0; i<351; i++)
usart_putc_nonblocking(x++);
+ */
/* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
diff --git a/gm_platform/fw/serial.h b/gm_platform/fw/serial.h
index c10393a..39ffd18 100644
--- a/gm_platform/fw/serial.h
+++ b/gm_platform/fw/serial.h
@@ -27,19 +27,46 @@
#include <stdarg.h>
#include <errno.h>
+#include "global.h"
+
struct dma_tx_buf {
- size_t xfr_start; /* Start index of running DMA transfer */
- size_t xfr_end; /* End index of running DMA transfer plus one */
- size_t wr_pos; /* Next index to be written */
+ /* The following fields are accessed only from DMA ISR */
+ ssize_t xfr_start; /* Start index of running DMA transfer */
+ ssize_t xfr_end; /* End index of running DMA transfer plus one */
+ uint8_t cur_packet;
+
+ /* The following fields are written only from non-interrupt code */
+ ssize_t wr_pos; /* Next index to be written */
+ ssize_t packet_start[8];
+
+ /* The following may be accessed by anything */
uint8_t data[512];
- size_t packet_starts[5];
+};
+
+struct __attribute__((__packed__)) ll_pkt {
+ uint32_t crc32;
+ /* CRC computed over entire packet starting here */
+ uint8_t pid;
+ uint8_t _pad;
+ uint8_t data[];
+};
+
+enum ctrl_pkt_type {
+ CTRL_PKT_RESET = 1,
+ CTRL_PKT_ACK = 2,
+ CTRL_PKT_RETRANSMIT = 3,
+};
+
+struct __attribute__((__packed__)) ctrl_pkt {
+ uint8_t type;
+ uint8_t orig_id;
};
extern volatile struct dma_tx_buf usart_tx_buf;
void usart_dma_init(void);
-int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c);
-void usart_send_packet(const uint8_t *data, size_t len);
-int usart_send_packet_nonblocking(const uint8_t *data, size_t len);
+int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c);
+int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len);
+int usart_ack_packet(uint8_t idx);
#endif // __SERIAL_H__
generated by cgit (git 2.34.1) at 2024-11-24 16:17:49 +0000