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authorjaseg <git@jaseg.net>2020-01-28 12:45:00 +0100
committerjaseg <git@jaseg.net>2020-01-28 12:45:00 +0100
commit00b530ab415b92be9e76984510ed175aafcb5cfe (patch)
treeb13c2000cd7dd56b1867f1c19bf94a904b982f02 /gm_platform/fw
parentf4a6ea896f711f68e898e69e21d74118a44465f2 (diff)
downloadmaster-thesis-00b530ab415b92be9e76984510ed175aafcb5cfe.tar.gz
master-thesis-00b530ab415b92be9e76984510ed175aafcb5cfe.tar.bz2
master-thesis-00b530ab415b92be9e76984510ed175aafcb5cfe.zip
wip
Diffstat (limited to 'gm_platform/fw')
-rwxr-xr-xgm_platform/fw/main.binbin7416 -> 7376 bytes
-rwxr-xr-xgm_platform/fw/main.elfbin184004 -> 183980 bytes
-rw-r--r--gm_platform/fw/main.hex653
-rw-r--r--gm_platform/fw/main.lst5023
-rw-r--r--gm_platform/fw/main.map440
-rw-r--r--gm_platform/fw/serial.c135
-rw-r--r--gm_platform/fw/serial.h7
7 files changed, 3109 insertions, 3149 deletions
diff --git a/gm_platform/fw/main.bin b/gm_platform/fw/main.bin
index 828a8bd..c7953c8 100755
--- a/gm_platform/fw/main.bin
+++ b/gm_platform/fw/main.bin
Binary files differ
diff --git a/gm_platform/fw/main.elf b/gm_platform/fw/main.elf
index b7b6067..156f38f 100755
--- a/gm_platform/fw/main.elf
+++ b/gm_platform/fw/main.elf
Binary files differ
diff --git a/gm_platform/fw/main.hex b/gm_platform/fw/main.hex
index d69bcb8..96eba06 100644
--- a/gm_platform/fw/main.hex
+++ b/gm_platform/fw/main.hex
@@ -1,15 +1,15 @@
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+:1000000000100020D51B000885040008910400089A
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+:1019400001D34B03C01A5241030B8B4201D30B034B
+:10195000C01A5241C30A8B4201D3CB02C01A524172
+:10196000830A8B4201D38B02C01A5241430A8B4235
+:1019700001D34B02C01A5241030A8B4201D30B021E
+:10198000C01A5241CDD2C3098B4201D3CB01C01A38
+:10199000524183098B4201D38B01C01A5241430942
+:1019A0008B4201D34B01C01A524103098B4201D330
+:1019B0000B01C01A5241C3088B4201D3CB00C01A9D
+:1019C000524183088B4201D38B00C01A5241430815
+:1019D0008B4201D34B00C01A5241411A00D201463A
+:1019E000524110467047FFE701B5002000F0F0F8C3
+:1019F00002BDC0460029F7D076E7704703460B4387
+:101A00007FD4002243088B4274D303098B425FD3F7
+:101A1000030A8B4244D3030B8B4228D3030C8B4223
+:101A20000DD3FF22090212BA030C8B4202D3121209
+:101A3000090265D0030B8B4219D300E0090AC30BDE
+:101A40008B4201D3CB03C01A5241830B8B4201D38B
+:101A50008B03C01A5241430B8B4201D34B03C01A74
+:101A60005241030B8B4201D30B03C01A5241C30AEC
+:101A70008B4201D3CB02C01A5241830A8B4201D35D
+:101A80008B02C01A5241430A8B4201D34B02C01A47
+:101A90005241030A8B4201D30B02C01A5241CDD2EC
+:101AA000C3098B4201D3CB01C01A524183098B4237
+:101AB00001D38B01C01A524143098B4201D34B0120
+:101AC000C01A524103098B4201D30B01C01A524183
+:101AD000C3088B4201D3CB00C01A524183088B420A
+:101AE00001D38B00C01A524143088B4201D34B00F3
+:101AF000C01A5241411A00D2014652411046704765
+:101B00005DE0CA0F00D04942031000D34042534069
+:101B100000229C4603098B422DD3030A8B4212D329
+:101B2000FC22890112BA030A8B420CD3890192115B
+:101B30008B4208D3890192118B4204D389013AD098
+:101B4000921100E08909C3098B4201D3CB01C01A6D
+:101B5000524183098B4201D38B01C01A5241430980
+:101B60008B4201D34B01C01A524103098B4201D36E
+:101B70000B01C01A5241C3088B4201D3CB00C01ADB
+:101B8000524183088B4201D38B00C01A5241D9D2F3
+:101B900043088B4201D34B00C01A5241411A00D274
+:101BA0000146634652415B10104601D34042002B70
+:101BB00000D54942704763465B1000D3404201B5EF
+:101BC000002000F005F802BD0029F8D016E77047A4
+:101BD0007047C0460C488546002103E00B4B5B581C
+:101BE000435004310A480B4B42189A42F6D30A4A32
+:101BF00002E0002313600432084B9A42F9D3FFF746
+:101C0000ADFAFEF70AFBFEE7001000203C1C0008BE
+:101C1000000000209400002094000020D403002045
+:101C2000FEE70000000000000000000001020304C5
+:0C1C300006070809000000000102030480
+:101C3C0000127A0000040040002000400028004000
+:101C4C00002C004000300040005400400070004068
+:101C5C00000001400004014000240140082701401D
+:101C6C0008270140002C01400030014000380140A1
+:101C7C00004401400048014000580140000002406F
+:101C8C00080002401C0002403000024044000240A8
+:101C9C00580002400020024000F8FF1F00100240D4
+:101CAC0000300240000000480004004800080048D2
+:101CBC00000C00480014004800ED00E010E000E0CB
+:041CCC0000E100E053
+:0400000508001BD5FF
:00000001FF
diff --git a/gm_platform/fw/main.lst b/gm_platform/fw/main.lst
index 1958b70..1fc34f4 100644
--- a/gm_platform/fw/main.lst
+++ b/gm_platform/fw/main.lst
@@ -15,19 +15,19 @@ SYMBOL TABLE:
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_ranges 00000000 .debug_ranges
-00000000 l df *ABS* 00000000 /tmp/ccjaIjJQ.o
-08001c0c l .text 00000000 LoopCopyDataInit
-08001c04 l .text 00000000 CopyDataInit
-08001c20 l .text 00000000 LoopFillZerobss
-08001c1a l .text 00000000 FillZerobss
-08001c2e l .text 00000000 LoopForever
-08001c48 l .text 00000000 Infinite_Loop
+00000000 l df *ABS* 00000000 /tmp/ccNO0bzV.o
+08001be4 l .text 00000000 LoopCopyDataInit
+08001bdc l .text 00000000 CopyDataInit
+08001bf8 l .text 00000000 LoopFillZerobss
+08001bf2 l .text 00000000 FillZerobss
+08001c06 l .text 00000000 LoopForever
+08001c20 l .text 00000000 Infinite_Loop
00000000 l df *ABS* 00000000 main.c
080000c0 l F .text 0000002c NVIC_EnableIRQ
080000ec l F .text 000000dc NVIC_SetPriority
080001c8 l F .text 00000048 SysTick_Config
-20000098 l .bss 00000004 leds_update_counter.5792
-2000009c l .bss 00000004 n.5815
+20000098 l .bss 00000004 leds_update_counter.5796
+2000009c l .bss 00000004 n.5819
00000000 l df *ABS* 00000000 adc.c
080004e8 l F .text 0000002c NVIC_EnableIRQ
08000514 l F .text 000000dc NVIC_SetPriority
@@ -48,152 +48,151 @@ SYMBOL TABLE:
20000144 l .bss 00000004 rx_protocol_errors
20000148 l .bss 00000008 cobs_state
20000150 l .bss 00000020 rx_buf
-08000d10 l F .text 000000ac usart_retransmit_packet
-08000b50 l F .text 00000074 usart_schedule_dma
-08000ca8 l F .text 00000028 usart_putc_nonblocking
+08000b68 l F .text 000000d0 usart_schedule_dma
+08000d24 l F .text 00000028 usart_putc_nonblocking
00000000 l df *ABS* 00000000 cobs.c
00000000 l df *ABS* 00000000 system_stm32f0xx.c
00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c
-080012f8 l F .text 0000001c LL_RCC_HSE_EnableBypass
-08001314 l F .text 00000020 LL_RCC_HSE_DisableBypass
-08001334 l F .text 0000001c LL_RCC_HSE_Enable
-08001350 l F .text 00000028 LL_RCC_HSE_IsReady
-08001378 l F .text 0000001c LL_RCC_HSI_Enable
-08001394 l F .text 00000020 LL_RCC_HSI_IsReady
-080013b4 l F .text 00000028 LL_RCC_SetSysClkSource
-080013dc l F .text 00000018 LL_RCC_GetSysClkSource
-080013f4 l F .text 00000028 LL_RCC_SetAHBPrescaler
-0800141c l F .text 0000002c LL_RCC_SetAPB1Prescaler
-08001448 l F .text 0000001c LL_RCC_PLL_Enable
-08001464 l F .text 00000028 LL_RCC_PLL_IsReady
-0800148c l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
-080014d8 l F .text 00000034 LL_InitTick
-0800150c l F .text 00000028 LL_FLASH_SetLatency
-08001534 l F .text 00000018 LL_FLASH_GetLatency
-0800178e l F .text 00000026 UTILS_PLL_IsBusy
-08001754 l F .text 0000003a UTILS_GetPLLOutputFrequency
-080017b4 l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
-080016f8 l F .text 0000005c UTILS_SetFlashLatency
+080012d0 l F .text 0000001c LL_RCC_HSE_EnableBypass
+080012ec l F .text 00000020 LL_RCC_HSE_DisableBypass
+0800130c l F .text 0000001c LL_RCC_HSE_Enable
+08001328 l F .text 00000028 LL_RCC_HSE_IsReady
+08001350 l F .text 0000001c LL_RCC_HSI_Enable
+0800136c l F .text 00000020 LL_RCC_HSI_IsReady
+0800138c l F .text 00000028 LL_RCC_SetSysClkSource
+080013b4 l F .text 00000018 LL_RCC_GetSysClkSource
+080013cc l F .text 00000028 LL_RCC_SetAHBPrescaler
+080013f4 l F .text 0000002c LL_RCC_SetAPB1Prescaler
+08001420 l F .text 0000001c LL_RCC_PLL_Enable
+0800143c l F .text 00000028 LL_RCC_PLL_IsReady
+08001464 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
+080014b0 l F .text 00000034 LL_InitTick
+080014e4 l F .text 00000028 LL_FLASH_SetLatency
+0800150c l F .text 00000018 LL_FLASH_GetLatency
+08001766 l F .text 00000026 UTILS_PLL_IsBusy
+0800172c l F .text 0000003a UTILS_GetPLLOutputFrequency
+0800178c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
+080016d0 l F .text 0000005c UTILS_SetFlashLatency
00000000 l df *ABS* 00000000 base.c
00000000 l df *ABS* 00000000 cmsis_exports.c
00000000 l df *ABS* 00000000 _udivsi3.o
-08001910 l .text 00000000 .udivsi3_skip_div0_test
+080018e8 l .text 00000000 .udivsi3_skip_div0_test
00000000 l df *ABS* 00000000 _divsi3.o
-08001a24 l .text 00000000 .divsi3_skip_div0_test
+080019fc l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
-08001c5c g O .text 00000008 APBPrescTable
+08001c34 g O .text 00000008 APBPrescTable
20000044 g O .data 00000004 tim17
2000007c g O .data 00000004 gpioc
20000088 g O .data 00000004 scb
-0800156a g F .text 00000046 LL_mDelay
-08001c48 w F .text 00000002 TIM1_CC_IRQHandler
-0800188c g F .text 0000000a __sinit
+08001542 g F .text 00000046 LL_mDelay
+08001c20 w F .text 00000002 TIM1_CC_IRQHandler
+08001864 g F .text 0000000a __sinit
08000490 g F .text 00000004 HardFault_Handler
2000006c g O .data 00000004 rcc
080004ac g F .text 0000003c SysTick_Handler
-08001c64 g .text 00000000 _sidata
+08001c3c g .text 00000000 _sidata
080004a0 g F .text 0000000c PendSV_Handler
20000020 g O .data 00000004 syscfg
08000484 g F .text 0000000c NMI_Handler
-200003b8 g .bss 00000000 __exidx_end
-080015cc g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
-08001c48 w F .text 00000002 I2C1_IRQHandler
-080015b0 g F .text 0000001c LL_SetSystemCoreClock
+200003d4 g .bss 00000000 __exidx_end
+080015a4 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
+08001c20 w F .text 00000002 I2C1_IRQHandler
+08001588 g F .text 0000001c LL_SetSystemCoreClock
20000170 g O .bss 00000004 __errno
20000008 g O .data 00000004 tim14
20000048 g O .data 00000004 dbgmcu
2000003c g O .data 00000004 usart1
-08001c64 g .text 00000000 _etext
+08001c3c g .text 00000000 _etext
20000094 g .bss 00000000 _sbss
-08000f9a g F .text 000000d6 cobs_decode
-20000198 g O .bss 00000220 usart_tx_buf
+08000f72 g F .text 000000d6 cobs_decode
+20000198 g O .bss 0000023c usart_tx_buf
20000094 g O .bss 00000004 sys_time_seconds
20000000 g O .data 00000004 SystemCoreClock
2000001c g O .data 00000004 pwr
-08001910 g F .text 0000010a .hidden __udivsi3
-080018fa g F .text 00000014 __assert_func
+080018e8 g F .text 0000010a .hidden __udivsi3
+080018d2 g F .text 00000014 __assert_func
20000000 g .data 00000000 _sdata
0800039c g F .text 0000002c SPI1_IRQHandler
20000060 g O .data 00000004 dma1_channel5
20000058 g O .data 00000004 dma1_channel3
-200003b8 g .bss 00000000 __exidx_start
-0800154c g F .text 0000001e LL_Init1msTick
+200003d4 g .bss 00000000 __exidx_start
+08001524 g F .text 0000001e LL_Init1msTick
20000054 g O .data 00000004 dma1_channel2
-08001c48 w F .text 00000002 EXTI2_3_IRQHandler
-08001c48 w F .text 00000002 ADC1_IRQHandler
-0800108c g F .text 000000e2 cobs_decode_incremental
+08001c20 w F .text 00000002 EXTI2_3_IRQHandler
+08001c20 w F .text 00000002 ADC1_IRQHandler
+08001064 g F .text 000000e2 cobs_decode_incremental
2000004c g O .data 00000004 dma1
-08001c48 w F .text 00000002 TIM17_IRQHandler
-08001c48 w F .text 00000002 RTC_IRQHandler
-200003b8 g .bss 00000000 _ebss
+08001c20 w F .text 00000002 TIM17_IRQHandler
+08001c20 w F .text 00000002 RTC_IRQHandler
+200003d4 g .bss 00000000 _ebss
2000002c g O .data 00000004 adc1_common
-08001bfc w F .text 00000034 Reset_Handler
+08001bd4 w F .text 00000034 Reset_Handler
20000070 g O .data 00000004 crc
20000024 g O .data 00000004 exti
08000210 g F .text 0000000a update_leds
20000028 g O .data 00000004 adc1
-08001a24 g F .text 00000000 .hidden __aeabi_idiv
+080019fc g F .text 00000000 .hidden __aeabi_idiv
20000178 g O .bss 00000020 leds
20000074 g O .data 00000004 gpioa
080003c8 g F .text 000000bc TIM16_IRQHandler
-08001c48 w F .text 00000002 TIM3_IRQHandler
-08001c48 w F .text 00000002 EXTI4_15_IRQHandler
-08001c48 w F .text 00000002 RCC_IRQHandler
-08000dbc g F .text 00000120 usart_send_packet_nonblocking
+08001c20 w F .text 00000002 TIM3_IRQHandler
+08001c20 w F .text 00000002 EXTI4_15_IRQHandler
+08001c20 w F .text 00000002 RCC_IRQHandler
+08000d90 g F .text 00000124 usart_send_packet_nonblocking
20000094 g .bss 00000000 _bss
0800079a g F .text 00000082 DMA1_Channel1_IRQHandler
-08001c48 g .text 00000002 Default_Handler
-08001c4c g O .text 00000010 AHBPrescTable
-08000edc g F .text 000000be cobs_encode_usart
+08001c20 g .text 00000002 Default_Handler
+08001c24 g O .text 00000010 AHBPrescTable
+08000eb4 g F .text 000000be cobs_encode_usart
20000010 g O .data 00000004 wwdg
-08001c48 w F .text 00000002 TIM14_IRQHandler
-08001c48 w F .text 00000002 DMA1_Channel4_5_IRQHandler
+08001c20 w F .text 00000002 TIM14_IRQHandler
+08001c20 w F .text 00000002 DMA1_Channel4_5_IRQHandler
20000030 g O .data 00000004 adc
-08000c78 g F .text 00000030 usart_putc
-08001c48 w F .text 00000002 EXTI0_1_IRQHandler
-08001bf8 w F .text 00000002 .hidden __aeabi_ldiv0
+08000cf4 g F .text 00000030 usart_putc
+08001c20 w F .text 00000002 EXTI0_1_IRQHandler
+08001bd0 w F .text 00000002 .hidden __aeabi_ldiv0
20000004 g O .data 00000004 tim3
2000000c g O .data 00000004 rtc
-08000954 g F .text 000000d4 usart_dma_init
-08001896 g F .text 0000003a memset
-08000bc4 g F .text 0000003c usart_ack_packet
+08000954 g F .text 000000ec usart_dma_init
+0800186e g F .text 0000003a memset
+08000c38 g F .text 00000060 usart_ack_packet
0800021a g F .text 00000182 main
20000064 g O .data 00000004 flash
-08001910 g F .text 00000000 .hidden __aeabi_uidiv
+080018e8 g F .text 00000000 .hidden __aeabi_uidiv
08000494 g F .text 0000000c SVC_Handler
20000018 g O .data 00000004 i2c1
20000050 g O .data 00000004 dma1_channel1
-08001a24 g F .text 000001cc .hidden __divsi3
+080019fc g F .text 000001cc .hidden __divsi3
20000090 g O .data 00000004 nvic
-08001184 g F .text 00000088 SystemInit
+0800115c g F .text 00000088 SystemInit
20000174 g O .bss 00000004 _impure_ptr
-08001c48 w F .text 00000002 WWDG_IRQHandler
+08001c20 w F .text 00000002 WWDG_IRQHandler
20000000 g .data 00000000 _data
20000084 g O .data 00000004 gpiof
-08000cd0 g F .text 00000040 DMA1_Channel2_3_IRQHandler
+08000d4c g F .text 00000044 DMA1_Channel2_3_IRQHandler
20000080 g O .data 00000004 gpiod
20001000 g *ABS* 00000000 _estack
-08001a1c g F .text 00000008 .hidden __aeabi_uidivmod
+080019f4 g F .text 00000008 .hidden __aeabi_uidivmod
20000068 g O .data 00000004 ob
20000094 g .data 00000000 _edata
20000038 g O .data 00000004 spi1
-08000c00 g F .text 00000078 usart_dma_fifo_push
+08000c98 g F .text 0000005c usart_dma_fifo_push
2000005c g O .data 00000004 dma1_channel4
08000000 g O .isr_vector 00000000 g_pfnVectors
-0800120c g F .text 000000ec SystemCoreClockUpdate
-08001658 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
-08001bf8 w F .text 00000002 .hidden __aeabi_idiv0
+080011e4 g F .text 000000ec SystemCoreClockUpdate
+08001630 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
+08001bd0 w F .text 00000002 .hidden __aeabi_idiv0
20000014 g O .data 00000004 iwdg
-08001c48 w F .text 00000002 FLASH_IRQHandler
-08001070 g F .text 0000001c cobs_decode_incremental_initialize
-08000a28 g F .text 00000128 USART1_IRQHandler
+08001c20 w F .text 00000002 FLASH_IRQHandler
+08001048 g F .text 0000001c cobs_decode_incremental_initialize
+08000a40 g F .text 00000128 USART1_IRQHandler
080005f0 g F .text 000000a0 adc_configure_scope_mode
-080018d0 g F .text 0000002a strlen
-08001c48 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
+080018a8 g F .text 0000002a strlen
+08001c20 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
20000078 g O .data 00000004 gpiob
20000034 g O .data 00000004 tim1
2000008c g O .data 00000004 systick
-08001bf0 g F .text 00000008 .hidden __aeabi_idivmod
+08001bc8 g F .text 00000008 .hidden __aeabi_idivmod
20000040 g O .data 00000004 tim16
@@ -496,13 +495,13 @@ int main(void) {
8000278: 430a orrs r2, r1
800027a: 605a str r2, [r3, #4]
SystemCoreClockUpdate();
- 800027c: f000 ffc6 bl 800120c <SystemCoreClockUpdate>
+ 800027c: f000 ffb2 bl 80011e4 <SystemCoreClockUpdate>
SysTick_Config(SystemCoreClock/10); /* 100ms interval */
8000280: 4b3c ldr r3, [pc, #240] ; (8000374 <main+0x15a>)
8000282: 681b ldr r3, [r3, #0]
8000284: 210a movs r1, #10
8000286: 0018 movs r0, r3
- 8000288: f001 fb42 bl 8001910 <__udivsi3>
+ 8000288: f001 fb2e bl 80018e8 <__udivsi3>
800028c: 0003 movs r3, r0
800028e: 0018 movs r0, r3
8000290: f7ff ff9a bl 80001c8 <SysTick_Config>
@@ -1134,7 +1133,7 @@ void adc_configure_scope_mode(int sampling_interval_ns) {
800064e: 687b ldr r3, [r7, #4]
8000650: 21fa movs r1, #250 ; 0xfa
8000652: 0018 movs r0, r3
- 8000654: f001 f9e6 bl 8001a24 <__divsi3>
+ 8000654: f001 f9d2 bl 80019fc <__divsi3>
8000658: 0003 movs r3, r0
800065a: e000 b.n 800065e <adc_configure_scope_mode+0x6e>
800065c: 2306 movs r3, #6
@@ -1398,7 +1397,7 @@ void DMA1_Channel1_IRQHandler(void) {
80007f8: 189b adds r3, r3, r2
80007fa: 2148 movs r1, #72 ; 0x48
80007fc: 0018 movs r0, r3
- 80007fe: f000 fadd bl 8000dbc <usart_send_packet_nonblocking>
+ 80007fe: f000 fac7 bl 8000d90 <usart_send_packet_nonblocking>
adc_buf[i] = -255;
}
}
@@ -1590,9 +1589,9 @@ void DMA1_Channel1_IRQHandler(void) {
8000950: e000e100 .word 0xe000e100
08000954 <usart_dma_init>:
+
static void usart_schedule_dma(void);
static int usart_putc_nonblocking(uint8_t c);
-static int usart_retransmit_packet(uint8_t idx);
void usart_dma_init() {
@@ -1600,1892 +1599,1893 @@ void usart_dma_init() {
8000956: b082 sub sp, #8
8000958: af00 add r7, sp, #0
usart_tx_buf.xfr_start = -1;
- 800095a: 4b2a ldr r3, [pc, #168] ; (8000a04 <usart_dma_init+0xb0>)
+ 800095a: 4b30 ldr r3, [pc, #192] ; (8000a1c <usart_dma_init+0xc8>)
800095c: 2201 movs r2, #1
800095e: 4252 negs r2, r2
8000960: 601a str r2, [r3, #0]
usart_tx_buf.xfr_end = 0;
- 8000962: 4b28 ldr r3, [pc, #160] ; (8000a04 <usart_dma_init+0xb0>)
+ 8000962: 4b2e ldr r3, [pc, #184] ; (8000a1c <usart_dma_init+0xc8>)
8000964: 2200 movs r2, #0
8000966: 605a str r2, [r3, #4]
usart_tx_buf.wr_pos = 0;
- 8000968: 4b26 ldr r3, [pc, #152] ; (8000a04 <usart_dma_init+0xb0>)
+ 8000968: 4b2c ldr r3, [pc, #176] ; (8000a1c <usart_dma_init+0xc8>)
800096a: 2200 movs r2, #0
- 800096c: 609a str r2, [r3, #8]
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- 800096e: 2300 movs r3, #0
- 8000970: 607b str r3, [r7, #4]
- 8000972: e00b b.n 800098c <usart_dma_init+0x38>
- usart_tx_buf.packet_start[i] = -1;
- 8000974: 4a23 ldr r2, [pc, #140] ; (8000a04 <usart_dma_init+0xb0>)
- 8000976: 687b ldr r3, [r7, #4]
- 8000978: 3302 adds r3, #2
- 800097a: 009b lsls r3, r3, #2
- 800097c: 18d3 adds r3, r2, r3
- 800097e: 3304 adds r3, #4
- 8000980: 2201 movs r2, #1
- 8000982: 4252 negs r2, r2
- 8000984: 601a str r2, [r3, #0]
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- 8000986: 687b ldr r3, [r7, #4]
- 8000988: 3301 adds r3, #1
+ 800096c: 615a str r2, [r3, #20]
+ usart_tx_buf.wr_idx = 0;
+ 800096e: 4b2b ldr r3, [pc, #172] ; (8000a1c <usart_dma_init+0xc8>)
+ 8000970: 2200 movs r2, #0
+ 8000972: 619a str r2, [r3, #24]
+ usart_tx_buf.cur_packet = -1;
+ 8000974: 4b29 ldr r3, [pc, #164] ; (8000a1c <usart_dma_init+0xc8>)
+ 8000976: 2201 movs r2, #1
+ 8000978: 4252 negs r2, r2
+ 800097a: 609a str r2, [r3, #8]
+ usart_tx_buf.retransmit_rq = 0;
+ 800097c: 4b27 ldr r3, [pc, #156] ; (8000a1c <usart_dma_init+0xc8>)
+ 800097e: 2200 movs r2, #0
+ 8000980: 60da str r2, [r3, #12]
+ usart_tx_buf.wraparound = 0;
+ 8000982: 4b26 ldr r3, [pc, #152] ; (8000a1c <usart_dma_init+0xc8>)
+ 8000984: 2200 movs r2, #0
+ 8000986: 611a str r2, [r3, #16]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ 8000988: 2300 movs r3, #0
800098a: 607b str r3, [r7, #4]
- 800098c: 687b ldr r3, [r7, #4]
- 800098e: 2b04 cmp r3, #4
- 8000990: d9f0 bls.n 8000974 <usart_dma_init+0x20>
+ 800098c: e00b b.n 80009a6 <usart_dma_init+0x52>
+ usart_tx_buf.packet_end[i] = -1;
+ 800098e: 4a23 ldr r2, [pc, #140] ; (8000a1c <usart_dma_init+0xc8>)
+ 8000990: 687b ldr r3, [r7, #4]
+ 8000992: 3306 adds r3, #6
+ 8000994: 009b lsls r3, r3, #2
+ 8000996: 18d3 adds r3, r2, r3
+ 8000998: 3304 adds r3, #4
+ 800099a: 2201 movs r2, #1
+ 800099c: 4252 negs r2, r2
+ 800099e: 601a str r2, [r3, #0]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ 80009a0: 687b ldr r3, [r7, #4]
+ 80009a2: 3301 adds r3, #1
+ 80009a4: 607b str r3, [r7, #4]
+ 80009a6: 687b ldr r3, [r7, #4]
+ 80009a8: 2b07 cmp r3, #7
+ 80009aa: d9f0 bls.n 800098e <usart_dma_init+0x3a>
cobs_decode_incremental_initialize(&cobs_state);
- 8000992: 4b1d ldr r3, [pc, #116] ; (8000a08 <usart_dma_init+0xb4>)
- 8000994: 0018 movs r0, r3
- 8000996: f000 fb6b bl 8001070 <cobs_decode_incremental_initialize>
+ 80009ac: 4b1c ldr r3, [pc, #112] ; (8000a20 <usart_dma_init+0xcc>)
+ 80009ae: 0018 movs r0, r3
+ 80009b0: f000 fb4a bl 8001048 <cobs_decode_incremental_initialize>
/* Configure DMA 1 Channel 2 to handle uart transmission */
DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
- 800099a: 4b1c ldr r3, [pc, #112] ; (8000a0c <usart_dma_init+0xb8>)
- 800099c: 4a1c ldr r2, [pc, #112] ; (8000a10 <usart_dma_init+0xbc>)
- 800099e: 609a str r2, [r3, #8]
+ 80009b4: 4b1b ldr r3, [pc, #108] ; (8000a24 <usart_dma_init+0xd0>)
+ 80009b6: 4a1c ldr r2, [pc, #112] ; (8000a28 <usart_dma_init+0xd4>)
+ 80009b8: 609a str r2, [r3, #8]
DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
- 80009a0: 4b1a ldr r3, [pc, #104] ; (8000a0c <usart_dma_init+0xb8>)
- 80009a2: 2292 movs r2, #146 ; 0x92
- 80009a4: 601a str r2, [r3, #0]
+ 80009ba: 4b1a ldr r3, [pc, #104] ; (8000a24 <usart_dma_init+0xd0>)
+ 80009bc: 2292 movs r2, #146 ; 0x92
+ 80009be: 601a str r2, [r3, #0]
| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR);
- 80009a6: 4b1b ldr r3, [pc, #108] ; (8000a14 <usart_dma_init+0xc0>)
- 80009a8: 4a1b ldr r2, [pc, #108] ; (8000a18 <usart_dma_init+0xc4>)
- 80009aa: 60da str r2, [r3, #12]
+ 80009c0: 4b1a ldr r3, [pc, #104] ; (8000a2c <usart_dma_init+0xd8>)
+ 80009c2: 4a1b ldr r2, [pc, #108] ; (8000a30 <usart_dma_init+0xdc>)
+ 80009c4: 60da str r2, [r3, #12]
DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos)
- 80009ac: 4b19 ldr r3, [pc, #100] ; (8000a14 <usart_dma_init+0xc0>)
- 80009ae: 4a1b ldr r2, [pc, #108] ; (8000a1c <usart_dma_init+0xc8>)
- 80009b0: 601a str r2, [r3, #0]
+ 80009c6: 4b19 ldr r3, [pc, #100] ; (8000a2c <usart_dma_init+0xd8>)
+ 80009c8: 4a1a ldr r2, [pc, #104] ; (8000a34 <usart_dma_init+0xe0>)
+ 80009ca: 601a str r2, [r3, #0]
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_PINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on transfer completion. We use this to process the ADC data */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 80009b2: 200a movs r0, #10
- 80009b4: f7ff ff32 bl 800081c <NVIC_EnableIRQ>
+ 80009cc: 200a movs r0, #10
+ 80009ce: f7ff ff25 bl 800081c <NVIC_EnableIRQ>
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
- 80009b8: 2120 movs r1, #32
- 80009ba: 200a movs r0, #10
- 80009bc: f7ff ff5c bl 8000878 <NVIC_SetPriority>
+ 80009d2: 2120 movs r1, #32
+ 80009d4: 200a movs r0, #10
+ 80009d6: f7ff ff4f bl 8000878 <NVIC_SetPriority>
USART1->CR1 = /* 8-bit -> M1, M0 clear */
- 80009c0: 4b17 ldr r3, [pc, #92] ; (8000a20 <usart_dma_init+0xcc>)
- 80009c2: 4a18 ldr r2, [pc, #96] ; (8000a24 <usart_dma_init+0xd0>)
- 80009c4: 601a str r2, [r3, #0]
+ 80009da: 4b17 ldr r3, [pc, #92] ; (8000a38 <usart_dma_init+0xe4>)
+ 80009dc: 4a17 ldr r2, [pc, #92] ; (8000a3c <usart_dma_init+0xe8>)
+ 80009de: 601a str r2, [r3, #0]
/* Set divider for 115.2kBd @48MHz system clock. */
//USART1->BRR = 417;
//USART1->BRR = 48; /* 1MBd */
//USART1->BRR = 96; /* 500kBd */
USART1->BRR = 192; /* 250kBd */
- 80009c6: 4b16 ldr r3, [pc, #88] ; (8000a20 <usart_dma_init+0xcc>)
- 80009c8: 22c0 movs r2, #192 ; 0xc0
- 80009ca: 60da str r2, [r3, #12]
+ 80009e0: 4b15 ldr r3, [pc, #84] ; (8000a38 <usart_dma_init+0xe4>)
+ 80009e2: 22c0 movs r2, #192 ; 0xc0
+ 80009e4: 60da str r2, [r3, #12]
//USART1->BRR = 208; /* 230400 */
USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
- 80009cc: 4b14 ldr r3, [pc, #80] ; (8000a20 <usart_dma_init+0xcc>)
- 80009ce: 22c0 movs r2, #192 ; 0xc0
- 80009d0: 0292 lsls r2, r2, #10
- 80009d2: 605a str r2, [r3, #4]
+ 80009e6: 4b14 ldr r3, [pc, #80] ; (8000a38 <usart_dma_init+0xe4>)
+ 80009e8: 22c0 movs r2, #192 ; 0xc0
+ 80009ea: 0292 lsls r2, r2, #10
+ 80009ec: 605a str r2, [r3, #4]
USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
- 80009d4: 4b12 ldr r3, [pc, #72] ; (8000a20 <usart_dma_init+0xcc>)
- 80009d6: 689a ldr r2, [r3, #8]
- 80009d8: 4b11 ldr r3, [pc, #68] ; (8000a20 <usart_dma_init+0xcc>)
- 80009da: 2180 movs r1, #128 ; 0x80
- 80009dc: 430a orrs r2, r1
- 80009de: 609a str r2, [r3, #8]
+ 80009ee: 4b12 ldr r3, [pc, #72] ; (8000a38 <usart_dma_init+0xe4>)
+ 80009f0: 689a ldr r2, [r3, #8]
+ 80009f2: 4b11 ldr r3, [pc, #68] ; (8000a38 <usart_dma_init+0xe4>)
+ 80009f4: 2180 movs r1, #128 ; 0x80
+ 80009f6: 430a orrs r2, r1
+ 80009f8: 609a str r2, [r3, #8]
/* Enable receive interrupt */
NVIC_EnableIRQ(USART1_IRQn);
- 80009e0: 201b movs r0, #27
- 80009e2: f7ff ff1b bl 800081c <NVIC_EnableIRQ>
+ 80009fa: 201b movs r0, #27
+ 80009fc: f7ff ff0e bl 800081c <NVIC_EnableIRQ>
NVIC_SetPriority(USART1_IRQn, 3<<5);
- 80009e6: 2160 movs r1, #96 ; 0x60
- 80009e8: 201b movs r0, #27
- 80009ea: f7ff ff45 bl 8000878 <NVIC_SetPriority>
+ 8000a00: 2160 movs r1, #96 ; 0x60
+ 8000a02: 201b movs r0, #27
+ 8000a04: f7ff ff38 bl 8000878 <NVIC_SetPriority>
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
- 80009ee: 4b0c ldr r3, [pc, #48] ; (8000a20 <usart_dma_init+0xcc>)
- 80009f0: 681a ldr r2, [r3, #0]
- 80009f2: 4b0b ldr r3, [pc, #44] ; (8000a20 <usart_dma_init+0xcc>)
- 80009f4: 2101 movs r1, #1
- 80009f6: 430a orrs r2, r1
- 80009f8: 601a str r2, [r3, #0]
+ 8000a08: 4b0b ldr r3, [pc, #44] ; (8000a38 <usart_dma_init+0xe4>)
+ 8000a0a: 681a ldr r2, [r3, #0]
+ 8000a0c: 4b0a ldr r3, [pc, #40] ; (8000a38 <usart_dma_init+0xe4>)
+ 8000a0e: 2101 movs r1, #1
+ 8000a10: 430a orrs r2, r1
+ 8000a12: 601a str r2, [r3, #0]
}
- 80009fa: 46c0 nop ; (mov r8, r8)
- 80009fc: 46bd mov sp, r7
- 80009fe: b002 add sp, #8
- 8000a00: bd80 pop {r7, pc}
- 8000a02: 46c0 nop ; (mov r8, r8)
- 8000a04: 20000198 .word 0x20000198
- 8000a08: 20000148 .word 0x20000148
- 8000a0c: 4002001c .word 0x4002001c
- 8000a10: 40013828 .word 0x40013828
- 8000a14: 40020030 .word 0x40020030
- 8000a18: 40023000 .word 0x40023000
- 8000a1c: 00001042 .word 0x00001042
- 8000a20: 40013800 .word 0x40013800
- 8000a24: 0000202c .word 0x0000202c
-
-08000a28 <USART1_IRQHandler>:
+ 8000a14: 46c0 nop ; (mov r8, r8)
+ 8000a16: 46bd mov sp, r7
+ 8000a18: b002 add sp, #8
+ 8000a1a: bd80 pop {r7, pc}
+ 8000a1c: 20000198 .word 0x20000198
+ 8000a20: 20000148 .word 0x20000148
+ 8000a24: 4002001c .word 0x4002001c
+ 8000a28: 40013828 .word 0x40013828
+ 8000a2c: 40020030 .word 0x40020030
+ 8000a30: 40023000 .word 0x40023000
+ 8000a34: 00001042 .word 0x00001042
+ 8000a38: 40013800 .word 0x40013800
+ 8000a3c: 0000202c .word 0x0000202c
+
+08000a40 <USART1_IRQHandler>:
void USART1_IRQHandler() {
- 8000a28: b580 push {r7, lr}
- 8000a2a: b086 sub sp, #24
- 8000a2c: af00 add r7, sp, #0
+ 8000a40: b580 push {r7, lr}
+ 8000a42: b086 sub sp, #24
+ 8000a44: af00 add r7, sp, #0
uint32_t isr = USART1->ISR;
- 8000a2e: 4b41 ldr r3, [pc, #260] ; (8000b34 <USART1_IRQHandler+0x10c>)
- 8000a30: 69db ldr r3, [r3, #28]
- 8000a32: 613b str r3, [r7, #16]
+ 8000a46: 4b40 ldr r3, [pc, #256] ; (8000b48 <USART1_IRQHandler+0x108>)
+ 8000a48: 69db ldr r3, [r3, #28]
+ 8000a4a: 613b str r3, [r7, #16]
if (isr & USART_ISR_ORE) {
- 8000a34: 693b ldr r3, [r7, #16]
- 8000a36: 2208 movs r2, #8
- 8000a38: 4013 ands r3, r2
- 8000a3a: d008 beq.n 8000a4e <USART1_IRQHandler+0x26>
+ 8000a4c: 693b ldr r3, [r7, #16]
+ 8000a4e: 2208 movs r2, #8
+ 8000a50: 4013 ands r3, r2
+ 8000a52: d008 beq.n 8000a66 <USART1_IRQHandler+0x26>
USART1->ICR = USART_ICR_ORECF;
- 8000a3c: 4b3d ldr r3, [pc, #244] ; (8000b34 <USART1_IRQHandler+0x10c>)
- 8000a3e: 2208 movs r2, #8
- 8000a40: 621a str r2, [r3, #32]
+ 8000a54: 4b3c ldr r3, [pc, #240] ; (8000b48 <USART1_IRQHandler+0x108>)
+ 8000a56: 2208 movs r2, #8
+ 8000a58: 621a str r2, [r3, #32]
rx_overruns++;
- 8000a42: 4b3d ldr r3, [pc, #244] ; (8000b38 <USART1_IRQHandler+0x110>)
- 8000a44: 681b ldr r3, [r3, #0]
- 8000a46: 1c5a adds r2, r3, #1
- 8000a48: 4b3b ldr r3, [pc, #236] ; (8000b38 <USART1_IRQHandler+0x110>)
- 8000a4a: 601a str r2, [r3, #0]
+ 8000a5a: 4b3c ldr r3, [pc, #240] ; (8000b4c <USART1_IRQHandler+0x10c>)
+ 8000a5c: 681b ldr r3, [r3, #0]
+ 8000a5e: 1c5a adds r2, r3, #1
+ 8000a60: 4b3a ldr r3, [pc, #232] ; (8000b4c <USART1_IRQHandler+0x10c>)
+ 8000a62: 601a str r2, [r3, #0]
return;
- 8000a4c: e06f b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000a64: e06c b.n 8000b40 <USART1_IRQHandler+0x100>
}
if (isr & USART_ISR_RXNE) {
- 8000a4e: 693b ldr r3, [r7, #16]
- 8000a50: 2220 movs r2, #32
- 8000a52: 4013 ands r3, r2
- 8000a54: d100 bne.n 8000a58 <USART1_IRQHandler+0x30>
- 8000a56: e06a b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000a66: 693b ldr r3, [r7, #16]
+ 8000a68: 2220 movs r2, #32
+ 8000a6a: 4013 ands r3, r2
+ 8000a6c: d100 bne.n 8000a70 <USART1_IRQHandler+0x30>
+ 8000a6e: e067 b.n 8000b40 <USART1_IRQHandler+0x100>
uint8_t c = USART1->RDR;
- 8000a58: 4b36 ldr r3, [pc, #216] ; (8000b34 <USART1_IRQHandler+0x10c>)
- 8000a5a: 8c9b ldrh r3, [r3, #36] ; 0x24
- 8000a5c: b29a uxth r2, r3
- 8000a5e: 210f movs r1, #15
- 8000a60: 187b adds r3, r7, r1
- 8000a62: 701a strb r2, [r3, #0]
+ 8000a70: 4b35 ldr r3, [pc, #212] ; (8000b48 <USART1_IRQHandler+0x108>)
+ 8000a72: 8c9b ldrh r3, [r3, #36] ; 0x24
+ 8000a74: b29a uxth r2, r3
+ 8000a76: 210f movs r1, #15
+ 8000a78: 187b adds r3, r7, r1
+ 8000a7a: 701a strb r2, [r3, #0]
int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c);
- 8000a64: 187b adds r3, r7, r1
- 8000a66: 781b ldrb r3, [r3, #0]
- 8000a68: 4934 ldr r1, [pc, #208] ; (8000b3c <USART1_IRQHandler+0x114>)
- 8000a6a: 4835 ldr r0, [pc, #212] ; (8000b40 <USART1_IRQHandler+0x118>)
- 8000a6c: 2220 movs r2, #32
- 8000a6e: f000 fb0d bl 800108c <cobs_decode_incremental>
- 8000a72: 0003 movs r3, r0
- 8000a74: 60bb str r3, [r7, #8]
+ 8000a7c: 187b adds r3, r7, r1
+ 8000a7e: 781b ldrb r3, [r3, #0]
+ 8000a80: 4933 ldr r1, [pc, #204] ; (8000b50 <USART1_IRQHandler+0x110>)
+ 8000a82: 4834 ldr r0, [pc, #208] ; (8000b54 <USART1_IRQHandler+0x114>)
+ 8000a84: 2220 movs r2, #32
+ 8000a86: f000 faed bl 8001064 <cobs_decode_incremental>
+ 8000a8a: 0003 movs r3, r0
+ 8000a8c: 60bb str r3, [r7, #8]
if (rc == 0) /* packet still incomplete */
- 8000a76: 68bb ldr r3, [r7, #8]
- 8000a78: 2b00 cmp r3, #0
- 8000a7a: d057 beq.n 8000b2c <USART1_IRQHandler+0x104>
+ 8000a8e: 68bb ldr r3, [r7, #8]
+ 8000a90: 2b00 cmp r3, #0
+ 8000a92: d054 beq.n 8000b3e <USART1_IRQHandler+0xfe>
return;
if (rc < 0) {
- 8000a7c: 68bb ldr r3, [r7, #8]
- 8000a7e: 2b00 cmp r3, #0
- 8000a80: da05 bge.n 8000a8e <USART1_IRQHandler+0x66>
+ 8000a94: 68bb ldr r3, [r7, #8]
+ 8000a96: 2b00 cmp r3, #0
+ 8000a98: da05 bge.n 8000aa6 <USART1_IRQHandler+0x66>
rx_framing_errors++;
- 8000a82: 4b30 ldr r3, [pc, #192] ; (8000b44 <USART1_IRQHandler+0x11c>)
- 8000a84: 681b ldr r3, [r3, #0]
- 8000a86: 1c5a adds r2, r3, #1
- 8000a88: 4b2e ldr r3, [pc, #184] ; (8000b44 <USART1_IRQHandler+0x11c>)
- 8000a8a: 601a str r2, [r3, #0]
+ 8000a9a: 4b2f ldr r3, [pc, #188] ; (8000b58 <USART1_IRQHandler+0x118>)
+ 8000a9c: 681b ldr r3, [r3, #0]
+ 8000a9e: 1c5a adds r2, r3, #1
+ 8000aa0: 4b2d ldr r3, [pc, #180] ; (8000b58 <USART1_IRQHandler+0x118>)
+ 8000aa2: 601a str r2, [r3, #0]
return;
- 8000a8c: e04f b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000aa4: e04c b.n 8000b40 <USART1_IRQHandler+0x100>
}
/* A complete frame received */
if (rc != 2) {
- 8000a8e: 68bb ldr r3, [r7, #8]
- 8000a90: 2b02 cmp r3, #2
- 8000a92: d005 beq.n 8000aa0 <USART1_IRQHandler+0x78>
+ 8000aa6: 68bb ldr r3, [r7, #8]
+ 8000aa8: 2b02 cmp r3, #2
+ 8000aaa: d005 beq.n 8000ab8 <USART1_IRQHandler+0x78>
rx_protocol_errors++;
- 8000a94: 4b2c ldr r3, [pc, #176] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000a96: 681b ldr r3, [r3, #0]
- 8000a98: 1c5a adds r2, r3, #1
- 8000a9a: 4b2b ldr r3, [pc, #172] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000a9c: 601a str r2, [r3, #0]
+ 8000aac: 4b2b ldr r3, [pc, #172] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000aae: 681b ldr r3, [r3, #0]
+ 8000ab0: 1c5a adds r2, r3, #1
+ 8000ab2: 4b2a ldr r3, [pc, #168] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000ab4: 601a str r2, [r3, #0]
return;
- 8000a9e: e046 b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000ab6: e043 b.n 8000b40 <USART1_IRQHandler+0x100>
}
volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf;
- 8000aa0: 4b26 ldr r3, [pc, #152] ; (8000b3c <USART1_IRQHandler+0x114>)
- 8000aa2: 607b str r3, [r7, #4]
+ 8000ab8: 4b25 ldr r3, [pc, #148] ; (8000b50 <USART1_IRQHandler+0x110>)
+ 8000aba: 607b str r3, [r7, #4]
switch (pkt->type) {
- 8000aa4: 687b ldr r3, [r7, #4]
- 8000aa6: 781b ldrb r3, [r3, #0]
- 8000aa8: b2db uxtb r3, r3
- 8000aaa: 2b03 cmp r3, #3
- 8000aac: d026 beq.n 8000afc <USART1_IRQHandler+0xd4>
- 8000aae: dc33 bgt.n 8000b18 <USART1_IRQHandler+0xf0>
- 8000ab0: 2b01 cmp r3, #1
- 8000ab2: d002 beq.n 8000aba <USART1_IRQHandler+0x92>
- 8000ab4: 2b02 cmp r3, #2
- 8000ab6: d013 beq.n 8000ae0 <USART1_IRQHandler+0xb8>
- 8000ab8: e02e b.n 8000b18 <USART1_IRQHandler+0xf0>
+ 8000abc: 687b ldr r3, [r7, #4]
+ 8000abe: 781b ldrb r3, [r3, #0]
+ 8000ac0: b2db uxtb r3, r3
+ 8000ac2: 2b03 cmp r3, #3
+ 8000ac4: d026 beq.n 8000b14 <USART1_IRQHandler+0xd4>
+ 8000ac6: dc30 bgt.n 8000b2a <USART1_IRQHandler+0xea>
+ 8000ac8: 2b01 cmp r3, #1
+ 8000aca: d002 beq.n 8000ad2 <USART1_IRQHandler+0x92>
+ 8000acc: 2b02 cmp r3, #2
+ 8000ace: d013 beq.n 8000af8 <USART1_IRQHandler+0xb8>
+ 8000ad0: e02b b.n 8000b2a <USART1_IRQHandler+0xea>
case CTRL_PKT_RESET:
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- 8000aba: 2300 movs r3, #0
- 8000abc: 617b str r3, [r7, #20]
- 8000abe: e00b b.n 8000ad8 <USART1_IRQHandler+0xb0>
- usart_tx_buf.packet_start[i] = -1;
- 8000ac0: 4a22 ldr r2, [pc, #136] ; (8000b4c <USART1_IRQHandler+0x124>)
- 8000ac2: 697b ldr r3, [r7, #20]
- 8000ac4: 3302 adds r3, #2
- 8000ac6: 009b lsls r3, r3, #2
- 8000ac8: 18d3 adds r3, r2, r3
- 8000aca: 3304 adds r3, #4
- 8000acc: 2201 movs r2, #1
- 8000ace: 4252 negs r2, r2
- 8000ad0: 601a str r2, [r3, #0]
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- 8000ad2: 697b ldr r3, [r7, #20]
- 8000ad4: 3301 adds r3, #1
- 8000ad6: 617b str r3, [r7, #20]
- 8000ad8: 697b ldr r3, [r7, #20]
- 8000ada: 2b04 cmp r3, #4
- 8000adc: d9f0 bls.n 8000ac0 <USART1_IRQHandler+0x98>
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ 8000ad2: 2300 movs r3, #0
+ 8000ad4: 617b str r3, [r7, #20]
+ 8000ad6: e00b b.n 8000af0 <USART1_IRQHandler+0xb0>
+ usart_tx_buf.packet_end[i] = -1;
+ 8000ad8: 4a21 ldr r2, [pc, #132] ; (8000b60 <USART1_IRQHandler+0x120>)
+ 8000ada: 697b ldr r3, [r7, #20]
+ 8000adc: 3306 adds r3, #6
+ 8000ade: 009b lsls r3, r3, #2
+ 8000ae0: 18d3 adds r3, r2, r3
+ 8000ae2: 3304 adds r3, #4
+ 8000ae4: 2201 movs r2, #1
+ 8000ae6: 4252 negs r2, r2
+ 8000ae8: 601a str r2, [r3, #0]
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ 8000aea: 697b ldr r3, [r7, #20]
+ 8000aec: 3301 adds r3, #1
+ 8000aee: 617b str r3, [r7, #20]
+ 8000af0: 697b ldr r3, [r7, #20]
+ 8000af2: 2b07 cmp r3, #7
+ 8000af4: d9f0 bls.n 8000ad8 <USART1_IRQHandler+0x98>
break;
- 8000ade: e024 b.n 8000b2a <USART1_IRQHandler+0x102>
+ 8000af6: e021 b.n 8000b3c <USART1_IRQHandler+0xfc>
case CTRL_PKT_ACK:
if (usart_ack_packet(pkt->orig_id))
- 8000ae0: 687b ldr r3, [r7, #4]
- 8000ae2: 785b ldrb r3, [r3, #1]
- 8000ae4: b2db uxtb r3, r3
- 8000ae6: 0018 movs r0, r3
- 8000ae8: f000 f86c bl 8000bc4 <usart_ack_packet>
- 8000aec: 1e03 subs r3, r0, #0
- 8000aee: d019 beq.n 8000b24 <USART1_IRQHandler+0xfc>
+ 8000af8: 687b ldr r3, [r7, #4]
+ 8000afa: 785b ldrb r3, [r3, #1]
+ 8000afc: b2db uxtb r3, r3
+ 8000afe: 0018 movs r0, r3
+ 8000b00: f000 f89a bl 8000c38 <usart_ack_packet>
+ 8000b04: 1e03 subs r3, r0, #0
+ 8000b06: d016 beq.n 8000b36 <USART1_IRQHandler+0xf6>
rx_protocol_errors++;
- 8000af0: 4b15 ldr r3, [pc, #84] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000af2: 681b ldr r3, [r3, #0]
- 8000af4: 1c5a adds r2, r3, #1
- 8000af6: 4b14 ldr r3, [pc, #80] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000af8: 601a str r2, [r3, #0]
+ 8000b08: 4b14 ldr r3, [pc, #80] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000b0a: 681b ldr r3, [r3, #0]
+ 8000b0c: 1c5a adds r2, r3, #1
+ 8000b0e: 4b13 ldr r3, [pc, #76] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000b10: 601a str r2, [r3, #0]
break;
- 8000afa: e013 b.n 8000b24 <USART1_IRQHandler+0xfc>
+ 8000b12: e010 b.n 8000b36 <USART1_IRQHandler+0xf6>
case CTRL_PKT_RETRANSMIT:
- if (usart_retransmit_packet(pkt->orig_id))
- 8000afc: 687b ldr r3, [r7, #4]
- 8000afe: 785b ldrb r3, [r3, #1]
- 8000b00: b2db uxtb r3, r3
- 8000b02: 0018 movs r0, r3
- 8000b04: f000 f904 bl 8000d10 <usart_retransmit_packet>
- 8000b08: 1e03 subs r3, r0, #0
- 8000b0a: d00d beq.n 8000b28 <USART1_IRQHandler+0x100>
- rx_protocol_errors++;
- 8000b0c: 4b0e ldr r3, [pc, #56] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000b0e: 681b ldr r3, [r3, #0]
- 8000b10: 1c5a adds r2, r3, #1
- 8000b12: 4b0d ldr r3, [pc, #52] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000b14: 601a str r2, [r3, #0]
+ usart_tx_buf.retransmit_rq = 1;
+ 8000b14: 4b12 ldr r3, [pc, #72] ; (8000b60 <USART1_IRQHandler+0x120>)
+ 8000b16: 2201 movs r2, #1
+ 8000b18: 60da str r2, [r3, #12]
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ 8000b1a: 4b12 ldr r3, [pc, #72] ; (8000b64 <USART1_IRQHandler+0x124>)
+ 8000b1c: 681b ldr r3, [r3, #0]
+ 8000b1e: 2201 movs r2, #1
+ 8000b20: 4013 ands r3, r2
+ 8000b22: d10a bne.n 8000b3a <USART1_IRQHandler+0xfa>
+ usart_schedule_dma();
+ 8000b24: f000 f820 bl 8000b68 <usart_schedule_dma>
break;
- 8000b16: e007 b.n 8000b28 <USART1_IRQHandler+0x100>
+ 8000b28: e007 b.n 8000b3a <USART1_IRQHandler+0xfa>
default:
rx_protocol_errors++;
- 8000b18: 4b0b ldr r3, [pc, #44] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000b1a: 681b ldr r3, [r3, #0]
- 8000b1c: 1c5a adds r2, r3, #1
- 8000b1e: 4b0a ldr r3, [pc, #40] ; (8000b48 <USART1_IRQHandler+0x120>)
- 8000b20: 601a str r2, [r3, #0]
+ 8000b2a: 4b0c ldr r3, [pc, #48] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000b2c: 681b ldr r3, [r3, #0]
+ 8000b2e: 1c5a adds r2, r3, #1
+ 8000b30: 4b0a ldr r3, [pc, #40] ; (8000b5c <USART1_IRQHandler+0x11c>)
+ 8000b32: 601a str r2, [r3, #0]
}
return;
- 8000b22: e004 b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000b34: e004 b.n 8000b40 <USART1_IRQHandler+0x100>
break;
- 8000b24: 46c0 nop ; (mov r8, r8)
- 8000b26: e002 b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000b36: 46c0 nop ; (mov r8, r8)
+ 8000b38: e002 b.n 8000b40 <USART1_IRQHandler+0x100>
break;
- 8000b28: 46c0 nop ; (mov r8, r8)
+ 8000b3a: 46c0 nop ; (mov r8, r8)
return;
- 8000b2a: e000 b.n 8000b2e <USART1_IRQHandler+0x106>
+ 8000b3c: e000 b.n 8000b40 <USART1_IRQHandler+0x100>
return;
- 8000b2c: 46c0 nop ; (mov r8, r8)
+ 8000b3e: 46c0 nop ; (mov r8, r8)
}
}
- 8000b2e: 46bd mov sp, r7
- 8000b30: b006 add sp, #24
- 8000b32: bd80 pop {r7, pc}
- 8000b34: 40013800 .word 0x40013800
- 8000b38: 2000013c .word 0x2000013c
- 8000b3c: 20000150 .word 0x20000150
- 8000b40: 20000148 .word 0x20000148
- 8000b44: 20000140 .word 0x20000140
- 8000b48: 20000144 .word 0x20000144
- 8000b4c: 20000198 .word 0x20000198
-
-08000b50 <usart_schedule_dma>:
+ 8000b40: 46bd mov sp, r7
+ 8000b42: b006 add sp, #24
+ 8000b44: bd80 pop {r7, pc}
+ 8000b46: 46c0 nop ; (mov r8, r8)
+ 8000b48: 40013800 .word 0x40013800
+ 8000b4c: 2000013c .word 0x2000013c
+ 8000b50: 20000150 .word 0x20000150
+ 8000b54: 20000148 .word 0x20000148
+ 8000b58: 20000140 .word 0x20000140
+ 8000b5c: 20000144 .word 0x20000144
+ 8000b60: 20000198 .word 0x20000198
+ 8000b64: 4002001c .word 0x4002001c
+
+08000b68 <usart_schedule_dma>:
void usart_schedule_dma() {
- 8000b50: b580 push {r7, lr}
- 8000b52: b084 sub sp, #16
- 8000b54: af00 add r7, sp, #0
+ 8000b68: b580 push {r7, lr}
+ 8000b6a: b086 sub sp, #24
+ 8000b6c: af00 add r7, sp, #0
/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
- 8000b56: 4b19 ldr r3, [pc, #100] ; (8000bbc <usart_schedule_dma+0x6c>)
- 8000b58: 60bb str r3, [r7, #8]
-
- ssize_t xfr_len, xfr_start = buf->xfr_end;
- 8000b5a: 68bb ldr r3, [r7, #8]
- 8000b5c: 685b ldr r3, [r3, #4]
- 8000b5e: 607b str r3, [r7, #4]
- if (buf->wr_pos > xfr_start) /* no wraparound */
- 8000b60: 68bb ldr r3, [r7, #8]
- 8000b62: 689b ldr r3, [r3, #8]
- 8000b64: 687a ldr r2, [r7, #4]
- 8000b66: 429a cmp r2, r3
- 8000b68: da05 bge.n 8000b76 <usart_schedule_dma+0x26>
- xfr_len = buf->wr_pos - xfr_start;
- 8000b6a: 68bb ldr r3, [r7, #8]
- 8000b6c: 689a ldr r2, [r3, #8]
- 8000b6e: 687b ldr r3, [r7, #4]
- 8000b70: 1ad3 subs r3, r2, r3
- 8000b72: 60fb str r3, [r7, #12]
- 8000b74: e004 b.n 8000b80 <usart_schedule_dma+0x30>
- else /* wraparound */
- xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */
- 8000b76: 687b ldr r3, [r7, #4]
- 8000b78: 2280 movs r2, #128 ; 0x80
- 8000b7a: 0092 lsls r2, r2, #2
- 8000b7c: 1ad3 subs r3, r2, r3
- 8000b7e: 60fb str r3, [r7, #12]
-
- buf->xfr_start = xfr_start;
+ 8000b6e: 4b30 ldr r3, [pc, #192] ; (8000c30 <usart_schedule_dma+0xc8>)
+ 8000b70: 60bb str r3, [r7, #8]
+
+ ssize_t next_start, next_idx;
+ if (buf->wraparound) {
+ 8000b72: 68bb ldr r3, [r7, #8]
+ 8000b74: 691b ldr r3, [r3, #16]
+ 8000b76: 2b00 cmp r3, #0
+ 8000b78: d008 beq.n 8000b8c <usart_schedule_dma+0x24>
+ buf->wraparound = 0;
+ 8000b7a: 68bb ldr r3, [r7, #8]
+ 8000b7c: 2200 movs r2, #0
+ 8000b7e: 611a str r2, [r3, #16]
+ next_idx = buf->cur_packet;
8000b80: 68bb ldr r3, [r7, #8]
- 8000b82: 687a ldr r2, [r7, #4]
- 8000b84: 601a str r2, [r3, #0]
- buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
- 8000b86: 687a ldr r2, [r7, #4]
- 8000b88: 68fb ldr r3, [r7, #12]
- 8000b8a: 18d3 adds r3, r2, r3
- 8000b8c: 05db lsls r3, r3, #23
- 8000b8e: 0dda lsrs r2, r3, #23
- 8000b90: 68bb ldr r3, [r7, #8]
- 8000b92: 605a str r2, [r3, #4]
+ 8000b82: 689b ldr r3, [r3, #8]
+ 8000b84: 613b str r3, [r7, #16]
+ next_start = 0;
+ 8000b86: 2300 movs r3, #0
+ 8000b88: 617b str r3, [r7, #20]
+ 8000b8a: e016 b.n 8000bba <usart_schedule_dma+0x52>
+
+ } else if (buf->retransmit_rq) {
+ 8000b8c: 68bb ldr r3, [r7, #8]
+ 8000b8e: 68db ldr r3, [r3, #12]
+ 8000b90: 2b00 cmp r3, #0
+ 8000b92: d009 beq.n 8000ba8 <usart_schedule_dma+0x40>
+ buf->retransmit_rq = 0;
+ 8000b94: 68bb ldr r3, [r7, #8]
+ 8000b96: 2200 movs r2, #0
+ 8000b98: 60da str r2, [r3, #12]
+ next_idx = buf->cur_packet;
+ 8000b9a: 68bb ldr r3, [r7, #8]
+ 8000b9c: 689b ldr r3, [r3, #8]
+ 8000b9e: 613b str r3, [r7, #16]
+ next_start = buf->xfr_start;
+ 8000ba0: 68bb ldr r3, [r7, #8]
+ 8000ba2: 681b ldr r3, [r3, #0]
+ 8000ba4: 617b str r3, [r7, #20]
+ 8000ba6: e008 b.n 8000bba <usart_schedule_dma+0x52>
+
+ } else {
+ next_idx = (buf->cur_packet + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
+ 8000ba8: 68bb ldr r3, [r7, #8]
+ 8000baa: 689b ldr r3, [r3, #8]
+ 8000bac: 3301 adds r3, #1
+ 8000bae: 2207 movs r2, #7
+ 8000bb0: 4013 ands r3, r2
+ 8000bb2: 613b str r3, [r7, #16]
+ next_start = buf->xfr_end;
+ 8000bb4: 68bb ldr r3, [r7, #8]
+ 8000bb6: 685b ldr r3, [r3, #4]
+ 8000bb8: 617b str r3, [r7, #20]
+ }
+
+ ssize_t next_end = buf->packet_end[next_idx];
+ 8000bba: 68ba ldr r2, [r7, #8]
+ 8000bbc: 693b ldr r3, [r7, #16]
+ 8000bbe: 3306 adds r3, #6
+ 8000bc0: 009b lsls r3, r3, #2
+ 8000bc2: 18d3 adds r3, r2, r3
+ 8000bc4: 3304 adds r3, #4
+ 8000bc6: 681b ldr r3, [r3, #0]
+ 8000bc8: 607b str r3, [r7, #4]
+
+ /* Nothing to trasnmit */
+ if (next_end == -1)
+ 8000bca: 687b ldr r3, [r7, #4]
+ 8000bcc: 3301 adds r3, #1
+ 8000bce: d02b beq.n 8000c28 <usart_schedule_dma+0xc0>
+ return;
+
+ ssize_t xfr_len;
+ if (next_end > next_start) /* no wraparound */
+ 8000bd0: 687a ldr r2, [r7, #4]
+ 8000bd2: 697b ldr r3, [r7, #20]
+ 8000bd4: 429a cmp r2, r3
+ 8000bd6: dd04 ble.n 8000be2 <usart_schedule_dma+0x7a>
+ xfr_len = next_end - next_start;
+ 8000bd8: 687a ldr r2, [r7, #4]
+ 8000bda: 697b ldr r3, [r7, #20]
+ 8000bdc: 1ad3 subs r3, r2, r3
+ 8000bde: 60fb str r3, [r7, #12]
+ 8000be0: e004 b.n 8000bec <usart_schedule_dma+0x84>
+ else /* wraparound */
+ xfr_len = sizeof(buf->data) - next_start; /* schedule transfer until end of buffer */
+ 8000be2: 697b ldr r3, [r7, #20]
+ 8000be4: 2280 movs r2, #128 ; 0x80
+ 8000be6: 0092 lsls r2, r2, #2
+ 8000be8: 1ad3 subs r3, r2, r3
+ 8000bea: 60fb str r3, [r7, #12]
+
+ buf->xfr_start = next_start;
+ 8000bec: 68bb ldr r3, [r7, #8]
+ 8000bee: 697a ldr r2, [r7, #20]
+ 8000bf0: 601a str r2, [r3, #0]
+ buf->xfr_end = (next_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
+ 8000bf2: 697a ldr r2, [r7, #20]
+ 8000bf4: 68fb ldr r3, [r7, #12]
+ 8000bf6: 18d3 adds r3, r2, r3
+ 8000bf8: 05db lsls r3, r3, #23
+ 8000bfa: 0dda lsrs r2, r3, #23
+ 8000bfc: 68bb ldr r3, [r7, #8]
+ 8000bfe: 605a str r2, [r3, #4]
+ buf->cur_packet = next_idx;
+ 8000c00: 68bb ldr r3, [r7, #8]
+ 8000c02: 693a ldr r2, [r7, #16]
+ 8000c04: 609a str r2, [r3, #8]
/* initiate transmission of new buffer */
- DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start);
- 8000b94: 68bb ldr r3, [r7, #8]
- 8000b96: 3320 adds r3, #32
- 8000b98: 001a movs r2, r3
- 8000b9a: 687b ldr r3, [r7, #4]
- 8000b9c: 18d2 adds r2, r2, r3
- 8000b9e: 4b08 ldr r3, [pc, #32] ; (8000bc0 <usart_schedule_dma+0x70>)
- 8000ba0: 60da str r2, [r3, #12]
+ DMA1_Channel2->CMAR = (uint32_t)(buf->data + next_start);
+ 8000c06: 68bb ldr r3, [r7, #8]
+ 8000c08: 333c adds r3, #60 ; 0x3c
+ 8000c0a: 001a movs r2, r3
+ 8000c0c: 697b ldr r3, [r7, #20]
+ 8000c0e: 18d2 adds r2, r2, r3
+ 8000c10: 4b08 ldr r3, [pc, #32] ; (8000c34 <usart_schedule_dma+0xcc>)
+ 8000c12: 60da str r2, [r3, #12]
DMA1_Channel2->CNDTR = xfr_len;
- 8000ba2: 4b07 ldr r3, [pc, #28] ; (8000bc0 <usart_schedule_dma+0x70>)
- 8000ba4: 68fa ldr r2, [r7, #12]
- 8000ba6: 605a str r2, [r3, #4]
+ 8000c14: 4b07 ldr r3, [pc, #28] ; (8000c34 <usart_schedule_dma+0xcc>)
+ 8000c16: 68fa ldr r2, [r7, #12]
+ 8000c18: 605a str r2, [r3, #4]
DMA1_Channel2->CCR |= DMA_CCR_EN;
- 8000ba8: 4b05 ldr r3, [pc, #20] ; (8000bc0 <usart_schedule_dma+0x70>)
- 8000baa: 681a ldr r2, [r3, #0]
- 8000bac: 4b04 ldr r3, [pc, #16] ; (8000bc0 <usart_schedule_dma+0x70>)
- 8000bae: 2101 movs r1, #1
- 8000bb0: 430a orrs r2, r1
- 8000bb2: 601a str r2, [r3, #0]
+ 8000c1a: 4b06 ldr r3, [pc, #24] ; (8000c34 <usart_schedule_dma+0xcc>)
+ 8000c1c: 681a ldr r2, [r3, #0]
+ 8000c1e: 4b05 ldr r3, [pc, #20] ; (8000c34 <usart_schedule_dma+0xcc>)
+ 8000c20: 2101 movs r1, #1
+ 8000c22: 430a orrs r2, r1
+ 8000c24: 601a str r2, [r3, #0]
+ 8000c26: e000 b.n 8000c2a <usart_schedule_dma+0xc2>
+ return;
+ 8000c28: 46c0 nop ; (mov r8, r8)
}
- 8000bb4: 46c0 nop ; (mov r8, r8)
- 8000bb6: 46bd mov sp, r7
- 8000bb8: b004 add sp, #16
- 8000bba: bd80 pop {r7, pc}
- 8000bbc: 20000198 .word 0x20000198
- 8000bc0: 4002001c .word 0x4002001c
+ 8000c2a: 46bd mov sp, r7
+ 8000c2c: b006 add sp, #24
+ 8000c2e: bd80 pop {r7, pc}
+ 8000c30: 20000198 .word 0x20000198
+ 8000c34: 4002001c .word 0x4002001c
-08000bc4 <usart_ack_packet>:
+08000c38 <usart_ack_packet>:
int usart_ack_packet(uint8_t idx) {
- 8000bc4: b580 push {r7, lr}
- 8000bc6: b082 sub sp, #8
- 8000bc8: af00 add r7, sp, #0
- 8000bca: 0002 movs r2, r0
- 8000bcc: 1dfb adds r3, r7, #7
- 8000bce: 701a strb r2, [r3, #0]
- if (idx > ARRAY_LEN(usart_tx_buf.packet_start))
- 8000bd0: 1dfb adds r3, r7, #7
- 8000bd2: 781b ldrb r3, [r3, #0]
- 8000bd4: 2b05 cmp r3, #5
- 8000bd6: d902 bls.n 8000bde <usart_ack_packet+0x1a>
+ 8000c38: b580 push {r7, lr}
+ 8000c3a: b082 sub sp, #8
+ 8000c3c: af00 add r7, sp, #0
+ 8000c3e: 0002 movs r2, r0
+ 8000c40: 1dfb adds r3, r7, #7
+ 8000c42: 701a strb r2, [r3, #0]
+ if (idx > ARRAY_LEN(usart_tx_buf.packet_end))
+ 8000c44: 1dfb adds r3, r7, #7
+ 8000c46: 781b ldrb r3, [r3, #0]
+ 8000c48: 2b08 cmp r3, #8
+ 8000c4a: d902 bls.n 8000c52 <usart_ack_packet+0x1a>
return -EINVAL;
- 8000bd8: 2316 movs r3, #22
- 8000bda: 425b negs r3, r3
- 8000bdc: e00a b.n 8000bf4 <usart_ack_packet+0x30>
-
- usart_tx_buf.packet_start[idx] = -1;
- 8000bde: 1dfb adds r3, r7, #7
- 8000be0: 781b ldrb r3, [r3, #0]
- 8000be2: 4a06 ldr r2, [pc, #24] ; (8000bfc <usart_ack_packet+0x38>)
- 8000be4: 3302 adds r3, #2
- 8000be6: 009b lsls r3, r3, #2
- 8000be8: 18d3 adds r3, r2, r3
- 8000bea: 3304 adds r3, #4
- 8000bec: 2201 movs r2, #1
- 8000bee: 4252 negs r2, r2
- 8000bf0: 601a str r2, [r3, #0]
+ 8000c4c: 2316 movs r3, #22
+ 8000c4e: 425b negs r3, r3
+ 8000c50: e01a b.n 8000c88 <usart_ack_packet+0x50>
+
+ if (idx != usart_tx_buf.cur_packet)
+ 8000c52: 1dfb adds r3, r7, #7
+ 8000c54: 781a ldrb r2, [r3, #0]
+ 8000c56: 4b0e ldr r3, [pc, #56] ; (8000c90 <usart_ack_packet+0x58>)
+ 8000c58: 689b ldr r3, [r3, #8]
+ 8000c5a: 429a cmp r2, r3
+ 8000c5c: d002 beq.n 8000c64 <usart_ack_packet+0x2c>
+ return -EINVAL;
+ 8000c5e: 2316 movs r3, #22
+ 8000c60: 425b negs r3, r3
+ 8000c62: e011 b.n 8000c88 <usart_ack_packet+0x50>
+
+ usart_tx_buf.packet_end[idx] = -1;
+ 8000c64: 1dfb adds r3, r7, #7
+ 8000c66: 781b ldrb r3, [r3, #0]
+ 8000c68: 4a09 ldr r2, [pc, #36] ; (8000c90 <usart_ack_packet+0x58>)
+ 8000c6a: 3306 adds r3, #6
+ 8000c6c: 009b lsls r3, r3, #2
+ 8000c6e: 18d3 adds r3, r2, r3
+ 8000c70: 3304 adds r3, #4
+ 8000c72: 2201 movs r2, #1
+ 8000c74: 4252 negs r2, r2
+ 8000c76: 601a str r2, [r3, #0]
+
+ /* If the DMA stream is idle right now, schedule the next transfer */
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ 8000c78: 4b06 ldr r3, [pc, #24] ; (8000c94 <usart_ack_packet+0x5c>)
+ 8000c7a: 681b ldr r3, [r3, #0]
+ 8000c7c: 2201 movs r2, #1
+ 8000c7e: 4013 ands r3, r2
+ 8000c80: d101 bne.n 8000c86 <usart_ack_packet+0x4e>
+ usart_schedule_dma();
+ 8000c82: f7ff ff71 bl 8000b68 <usart_schedule_dma>
return 0;
- 8000bf2: 2300 movs r3, #0
+ 8000c86: 2300 movs r3, #0
}
- 8000bf4: 0018 movs r0, r3
- 8000bf6: 46bd mov sp, r7
- 8000bf8: b002 add sp, #8
- 8000bfa: bd80 pop {r7, pc}
- 8000bfc: 20000198 .word 0x20000198
+ 8000c88: 0018 movs r0, r3
+ 8000c8a: 46bd mov sp, r7
+ 8000c8c: b002 add sp, #8
+ 8000c8e: bd80 pop {r7, pc}
+ 8000c90: 20000198 .word 0x20000198
+ 8000c94: 4002001c .word 0x4002001c
-08000c00 <usart_dma_fifo_push>:
+08000c98 <usart_dma_fifo_push>:
int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
- 8000c00: b580 push {r7, lr}
- 8000c02: b084 sub sp, #16
- 8000c04: af00 add r7, sp, #0
- 8000c06: 6078 str r0, [r7, #4]
- 8000c08: 000a movs r2, r1
- 8000c0a: 1cfb adds r3, r7, #3
- 8000c0c: 701a strb r2, [r3, #0]
+ 8000c98: b580 push {r7, lr}
+ 8000c9a: b082 sub sp, #8
+ 8000c9c: af00 add r7, sp, #0
+ 8000c9e: 6078 str r0, [r7, #4]
+ 8000ca0: 000a movs r2, r1
+ 8000ca2: 1cfb adds r3, r7, #3
+ 8000ca4: 701a strb r2, [r3, #0]
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
- 8000c0e: 200a movs r0, #10
- 8000c10: f7ff fe1a bl 8000848 <NVIC_DisableIRQ>
-
- /* If the write pointer hit any unacknowledged packet start position we can't advance it.
- * Packet start positions are unordered and we have to scan here. */
- for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
- 8000c14: 2300 movs r3, #0
- 8000c16: 60fb str r3, [r7, #12]
- 8000c18: e013 b.n 8000c42 <usart_dma_fifo_push+0x42>
- if (buf->wr_pos == buf->packet_start[i]) {
- 8000c1a: 687b ldr r3, [r7, #4]
- 8000c1c: 689a ldr r2, [r3, #8]
- 8000c1e: 6879 ldr r1, [r7, #4]
- 8000c20: 68fb ldr r3, [r7, #12]
- 8000c22: 3302 adds r3, #2
- 8000c24: 009b lsls r3, r3, #2
- 8000c26: 18cb adds r3, r1, r3
- 8000c28: 3304 adds r3, #4
- 8000c2a: 681b ldr r3, [r3, #0]
- 8000c2c: 429a cmp r2, r3
- 8000c2e: d105 bne.n 8000c3c <usart_dma_fifo_push+0x3c>
- NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000c30: 200a movs r0, #10
- 8000c32: f7ff fdf3 bl 800081c <NVIC_EnableIRQ>
- return -EBUSY;
- 8000c36: 2310 movs r3, #16
- 8000c38: 425b negs r3, r3
- 8000c3a: e019 b.n 8000c70 <usart_dma_fifo_push+0x70>
- for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
- 8000c3c: 68fb ldr r3, [r7, #12]
- 8000c3e: 3301 adds r3, #1
- 8000c40: 60fb str r3, [r7, #12]
- 8000c42: 68fb ldr r3, [r7, #12]
- 8000c44: 2b04 cmp r3, #4
- 8000c46: d9e8 bls.n 8000c1a <usart_dma_fifo_push+0x1a>
- }
+ 8000ca6: 200a movs r0, #10
+ 8000ca8: f7ff fdce bl 8000848 <NVIC_DisableIRQ>
+
+ if (buf->wr_pos == buf->xfr_start) {
+ 8000cac: 687b ldr r3, [r7, #4]
+ 8000cae: 695a ldr r2, [r3, #20]
+ 8000cb0: 687b ldr r3, [r7, #4]
+ 8000cb2: 681b ldr r3, [r3, #0]
+ 8000cb4: 429a cmp r2, r3
+ 8000cb6: d105 bne.n 8000cc4 <usart_dma_fifo_push+0x2c>
+ NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ 8000cb8: 200a movs r0, #10
+ 8000cba: f7ff fdaf bl 800081c <NVIC_EnableIRQ>
+ return -EBUSY;
+ 8000cbe: 2310 movs r3, #16
+ 8000cc0: 425b negs r3, r3
+ 8000cc2: e013 b.n 8000cec <usart_dma_fifo_push+0x54>
}
- /* write byte, then increment to avoid racing the DMA ISR reading wr_pos */
buf->data[buf->wr_pos] = c;
- 8000c48: 687b ldr r3, [r7, #4]
- 8000c4a: 689b ldr r3, [r3, #8]
- 8000c4c: 687a ldr r2, [r7, #4]
- 8000c4e: 2120 movs r1, #32
- 8000c50: 18d3 adds r3, r2, r3
- 8000c52: 185b adds r3, r3, r1
- 8000c54: 1cfa adds r2, r7, #3
- 8000c56: 7812 ldrb r2, [r2, #0]
- 8000c58: 701a strb r2, [r3, #0]
+ 8000cc4: 687b ldr r3, [r7, #4]
+ 8000cc6: 695b ldr r3, [r3, #20]
+ 8000cc8: 687a ldr r2, [r7, #4]
+ 8000cca: 213c movs r1, #60 ; 0x3c
+ 8000ccc: 18d3 adds r3, r2, r3
+ 8000cce: 185b adds r3, r3, r1
+ 8000cd0: 1cfa adds r2, r7, #3
+ 8000cd2: 7812 ldrb r2, [r2, #0]
+ 8000cd4: 701a strb r2, [r3, #0]
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
- 8000c5a: 687b ldr r3, [r7, #4]
- 8000c5c: 689b ldr r3, [r3, #8]
- 8000c5e: 3301 adds r3, #1
- 8000c60: 05db lsls r3, r3, #23
- 8000c62: 0dda lsrs r2, r3, #23
- 8000c64: 687b ldr r3, [r7, #4]
- 8000c66: 609a str r2, [r3, #8]
+ 8000cd6: 687b ldr r3, [r7, #4]
+ 8000cd8: 695b ldr r3, [r3, #20]
+ 8000cda: 3301 adds r3, #1
+ 8000cdc: 05db lsls r3, r3, #23
+ 8000cde: 0dda lsrs r2, r3, #23
+ 8000ce0: 687b ldr r3, [r7, #4]
+ 8000ce2: 615a str r2, [r3, #20]
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000c68: 200a movs r0, #10
- 8000c6a: f7ff fdd7 bl 800081c <NVIC_EnableIRQ>
+ 8000ce4: 200a movs r0, #10
+ 8000ce6: f7ff fd99 bl 800081c <NVIC_EnableIRQ>
return 0;
- 8000c6e: 2300 movs r3, #0
+ 8000cea: 2300 movs r3, #0
}
- 8000c70: 0018 movs r0, r3
- 8000c72: 46bd mov sp, r7
- 8000c74: b004 add sp, #16
- 8000c76: bd80 pop {r7, pc}
+ 8000cec: 0018 movs r0, r3
+ 8000cee: 46bd mov sp, r7
+ 8000cf0: b002 add sp, #8
+ 8000cf2: bd80 pop {r7, pc}
-08000c78 <usart_putc>:
+08000cf4 <usart_putc>:
int usart_putc(uint8_t c) {
- 8000c78: b580 push {r7, lr}
- 8000c7a: b082 sub sp, #8
- 8000c7c: af00 add r7, sp, #0
- 8000c7e: 0002 movs r2, r0
- 8000c80: 1dfb adds r3, r7, #7
- 8000c82: 701a strb r2, [r3, #0]
+ 8000cf4: b580 push {r7, lr}
+ 8000cf6: b082 sub sp, #8
+ 8000cf8: af00 add r7, sp, #0
+ 8000cfa: 0002 movs r2, r0
+ 8000cfc: 1dfb adds r3, r7, #7
+ 8000cfe: 701a strb r2, [r3, #0]
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
- 8000c84: 46c0 nop ; (mov r8, r8)
- 8000c86: 1dfb adds r3, r7, #7
- 8000c88: 781a ldrb r2, [r3, #0]
- 8000c8a: 4b06 ldr r3, [pc, #24] ; (8000ca4 <usart_putc+0x2c>)
- 8000c8c: 0011 movs r1, r2
- 8000c8e: 0018 movs r0, r3
- 8000c90: f7ff ffb6 bl 8000c00 <usart_dma_fifo_push>
- 8000c94: 0003 movs r3, r0
- 8000c96: 3310 adds r3, #16
- 8000c98: d0f5 beq.n 8000c86 <usart_putc+0xe>
+ 8000d00: 46c0 nop ; (mov r8, r8)
+ 8000d02: 1dfb adds r3, r7, #7
+ 8000d04: 781a ldrb r2, [r3, #0]
+ 8000d06: 4b06 ldr r3, [pc, #24] ; (8000d20 <usart_putc+0x2c>)
+ 8000d08: 0011 movs r1, r2
+ 8000d0a: 0018 movs r0, r3
+ 8000d0c: f7ff ffc4 bl 8000c98 <usart_dma_fifo_push>
+ 8000d10: 0003 movs r3, r0
+ 8000d12: 3310 adds r3, #16
+ 8000d14: d0f5 beq.n 8000d02 <usart_putc+0xe>
/* idle */
}
return 0;
- 8000c9a: 2300 movs r3, #0
+ 8000d16: 2300 movs r3, #0
}
- 8000c9c: 0018 movs r0, r3
- 8000c9e: 46bd mov sp, r7
- 8000ca0: b002 add sp, #8
- 8000ca2: bd80 pop {r7, pc}
- 8000ca4: 20000198 .word 0x20000198
+ 8000d18: 0018 movs r0, r3
+ 8000d1a: 46bd mov sp, r7
+ 8000d1c: b002 add sp, #8
+ 8000d1e: bd80 pop {r7, pc}
+ 8000d20: 20000198 .word 0x20000198
-08000ca8 <usart_putc_nonblocking>:
+08000d24 <usart_putc_nonblocking>:
int usart_putc_nonblocking(uint8_t c) {
- 8000ca8: b580 push {r7, lr}
- 8000caa: b082 sub sp, #8
- 8000cac: af00 add r7, sp, #0
- 8000cae: 0002 movs r2, r0
- 8000cb0: 1dfb adds r3, r7, #7
- 8000cb2: 701a strb r2, [r3, #0]
+ 8000d24: b580 push {r7, lr}
+ 8000d26: b082 sub sp, #8
+ 8000d28: af00 add r7, sp, #0
+ 8000d2a: 0002 movs r2, r0
+ 8000d2c: 1dfb adds r3, r7, #7
+ 8000d2e: 701a strb r2, [r3, #0]
return usart_dma_fifo_push(&usart_tx_buf, c);
- 8000cb4: 1dfb adds r3, r7, #7
- 8000cb6: 781a ldrb r2, [r3, #0]
- 8000cb8: 4b04 ldr r3, [pc, #16] ; (8000ccc <usart_putc_nonblocking+0x24>)
- 8000cba: 0011 movs r1, r2
- 8000cbc: 0018 movs r0, r3
- 8000cbe: f7ff ff9f bl 8000c00 <usart_dma_fifo_push>
- 8000cc2: 0003 movs r3, r0
+ 8000d30: 1dfb adds r3, r7, #7
+ 8000d32: 781a ldrb r2, [r3, #0]
+ 8000d34: 4b04 ldr r3, [pc, #16] ; (8000d48 <usart_putc_nonblocking+0x24>)
+ 8000d36: 0011 movs r1, r2
+ 8000d38: 0018 movs r0, r3
+ 8000d3a: f7ff ffad bl 8000c98 <usart_dma_fifo_push>
+ 8000d3e: 0003 movs r3, r0
}
- 8000cc4: 0018 movs r0, r3
- 8000cc6: 46bd mov sp, r7
- 8000cc8: b002 add sp, #8
- 8000cca: bd80 pop {r7, pc}
- 8000ccc: 20000198 .word 0x20000198
+ 8000d40: 0018 movs r0, r3
+ 8000d42: 46bd mov sp, r7
+ 8000d44: b002 add sp, #8
+ 8000d46: bd80 pop {r7, pc}
+ 8000d48: 20000198 .word 0x20000198
-08000cd0 <DMA1_Channel2_3_IRQHandler>:
+08000d4c <DMA1_Channel2_3_IRQHandler>:
void DMA1_Channel2_3_IRQHandler(void) {
- 8000cd0: b580 push {r7, lr}
- 8000cd2: af00 add r7, sp, #0
+ 8000d4c: b580 push {r7, lr}
+ 8000d4e: af00 add r7, sp, #0
/* Transfer complete */
DMA1->IFCR |= DMA_IFCR_CTCIF2;
- 8000cd4: 4b0b ldr r3, [pc, #44] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000cd6: 685a ldr r2, [r3, #4]
- 8000cd8: 4b0a ldr r3, [pc, #40] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000cda: 2120 movs r1, #32
- 8000cdc: 430a orrs r2, r1
- 8000cde: 605a str r2, [r3, #4]
+ 8000d50: 4b0c ldr r3, [pc, #48] ; (8000d84 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000d52: 685a ldr r2, [r3, #4]
+ 8000d54: 4b0b ldr r3, [pc, #44] ; (8000d84 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000d56: 2120 movs r1, #32
+ 8000d58: 430a orrs r2, r1
+ 8000d5a: 605a str r2, [r3, #4]
DMA1_Channel2->CCR &= ~DMA_CCR_EN;
- 8000ce0: 4b09 ldr r3, [pc, #36] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000ce2: 681a ldr r2, [r3, #0]
- 8000ce4: 4b08 ldr r3, [pc, #32] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000ce6: 2101 movs r1, #1
- 8000ce8: 438a bics r2, r1
- 8000cea: 601a str r2, [r3, #0]
- if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */
- 8000cec: 4b07 ldr r3, [pc, #28] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000cee: 689a ldr r2, [r3, #8]
- 8000cf0: 4b06 ldr r3, [pc, #24] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000cf2: 685b ldr r3, [r3, #4]
- 8000cf4: 429a cmp r2, r3
- 8000cf6: d001 beq.n 8000cfc <DMA1_Channel2_3_IRQHandler+0x2c>
+ 8000d5c: 4b0a ldr r3, [pc, #40] ; (8000d88 <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000d5e: 681a ldr r2, [r3, #0]
+ 8000d60: 4b09 ldr r3, [pc, #36] ; (8000d88 <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000d62: 2101 movs r1, #1
+ 8000d64: 438a bics r2, r1
+ 8000d66: 601a str r2, [r3, #0]
+ if (usart_tx_buf.retransmit_rq || usart_tx_buf.wraparound)
+ 8000d68: 4b08 ldr r3, [pc, #32] ; (8000d8c <DMA1_Channel2_3_IRQHandler+0x40>)
+ 8000d6a: 68db ldr r3, [r3, #12]
+ 8000d6c: 2b00 cmp r3, #0
+ 8000d6e: d103 bne.n 8000d78 <DMA1_Channel2_3_IRQHandler+0x2c>
+ 8000d70: 4b06 ldr r3, [pc, #24] ; (8000d8c <DMA1_Channel2_3_IRQHandler+0x40>)
+ 8000d72: 691b ldr r3, [r3, #16]
+ 8000d74: 2b00 cmp r3, #0
+ 8000d76: d001 beq.n 8000d7c <DMA1_Channel2_3_IRQHandler+0x30>
usart_schedule_dma();
- 8000cf8: f7ff ff2a bl 8000b50 <usart_schedule_dma>
+ 8000d78: f7ff fef6 bl 8000b68 <usart_schedule_dma>
}
- 8000cfc: 46c0 nop ; (mov r8, r8)
- 8000cfe: 46bd mov sp, r7
- 8000d00: bd80 pop {r7, pc}
- 8000d02: 46c0 nop ; (mov r8, r8)
- 8000d04: 40020000 .word 0x40020000
- 8000d08: 4002001c .word 0x4002001c
- 8000d0c: 20000198 .word 0x20000198
-
-08000d10 <usart_retransmit_packet>:
-
-int usart_retransmit_packet(uint8_t idx) {
- 8000d10: b590 push {r4, r7, lr}
- 8000d12: b087 sub sp, #28
- 8000d14: af00 add r7, sp, #0
- 8000d16: 0002 movs r2, r0
- 8000d18: 1dfb adds r3, r7, #7
- 8000d1a: 701a strb r2, [r3, #0]
- /* Disable ADC DMA IRQ to prevent write races */
- NVIC_DisableIRQ(DMA1_Channel1_IRQn);
- 8000d1c: 2009 movs r0, #9
- 8000d1e: f7ff fd93 bl 8000848 <NVIC_DisableIRQ>
-
- ssize_t i = usart_tx_buf.packet_start[idx];
- 8000d22: 1dfb adds r3, r7, #7
- 8000d24: 781b ldrb r3, [r3, #0]
- 8000d26: 4a23 ldr r2, [pc, #140] ; (8000db4 <usart_retransmit_packet+0xa4>)
- 8000d28: 3302 adds r3, #2
- 8000d2a: 009b lsls r3, r3, #2
- 8000d2c: 18d3 adds r3, r2, r3
- 8000d2e: 3304 adds r3, #4
- 8000d30: 681b ldr r3, [r3, #0]
- 8000d32: 617b str r3, [r7, #20]
- ssize_t start = i;
- 8000d34: 697b ldr r3, [r7, #20]
- 8000d36: 613b str r3, [r7, #16]
-
- /* Copy packet */
- uint8_t c;
- while ((c = usart_tx_buf.data[i++])) {
- 8000d38: e00f b.n 8000d5a <usart_retransmit_packet+0x4a>
- if (usart_putc_nonblocking(c)) {
- 8000d3a: 230f movs r3, #15
- 8000d3c: 18fb adds r3, r7, r3
- 8000d3e: 781b ldrb r3, [r3, #0]
- 8000d40: 0018 movs r0, r3
- 8000d42: f7ff ffb1 bl 8000ca8 <usart_putc_nonblocking>
- 8000d46: 1e03 subs r3, r0, #0
- 8000d48: d007 beq.n 8000d5a <usart_retransmit_packet+0x4a>
- tx_overruns++;
- 8000d4a: 4b1b ldr r3, [pc, #108] ; (8000db8 <usart_retransmit_packet+0xa8>)
- 8000d4c: 681b ldr r3, [r3, #0]
- 8000d4e: 1c5a adds r2, r3, #1
- 8000d50: 4b19 ldr r3, [pc, #100] ; (8000db8 <usart_retransmit_packet+0xa8>)
- 8000d52: 601a str r2, [r3, #0]
- return -EBUSY;
- 8000d54: 2310 movs r3, #16
- 8000d56: 425b negs r3, r3
- 8000d58: e028 b.n 8000dac <usart_retransmit_packet+0x9c>
- while ((c = usart_tx_buf.data[i++])) {
- 8000d5a: 697b ldr r3, [r7, #20]
- 8000d5c: 1c5a adds r2, r3, #1
- 8000d5e: 617a str r2, [r7, #20]
- 8000d60: 240f movs r4, #15
- 8000d62: 193a adds r2, r7, r4
- 8000d64: 4913 ldr r1, [pc, #76] ; (8000db4 <usart_retransmit_packet+0xa4>)
- 8000d66: 2020 movs r0, #32
- 8000d68: 18cb adds r3, r1, r3
- 8000d6a: 181b adds r3, r3, r0
- 8000d6c: 781b ldrb r3, [r3, #0]
- 8000d6e: 7013 strb r3, [r2, #0]
- 8000d70: 193b adds r3, r7, r4
- 8000d72: 781b ldrb r3, [r3, #0]
- 8000d74: 2b00 cmp r3, #0
- 8000d76: d1e0 bne.n 8000d3a <usart_retransmit_packet+0x2a>
- }
- }
+ 8000d7c: 46c0 nop ; (mov r8, r8)
+ 8000d7e: 46bd mov sp, r7
+ 8000d80: bd80 pop {r7, pc}
+ 8000d82: 46c0 nop ; (mov r8, r8)
+ 8000d84: 40020000 .word 0x40020000
+ 8000d88: 4002001c .word 0x4002001c
+ 8000d8c: 20000198 .word 0x20000198
+
+08000d90 <usart_send_packet_nonblocking>:
- /* Terminating null byte */
- if (usart_putc_nonblocking(0)) {
- 8000d78: 2000 movs r0, #0
- 8000d7a: f7ff ff95 bl 8000ca8 <usart_putc_nonblocking>
- 8000d7e: 1e03 subs r3, r0, #0
- 8000d80: d007 beq.n 8000d92 <usart_retransmit_packet+0x82>
+/* len is the packet length including headers */
+int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
+ 8000d90: b590 push {r4, r7, lr}
+ 8000d92: b085 sub sp, #20
+ 8000d94: af00 add r7, sp, #0
+ 8000d96: 6078 str r0, [r7, #4]
+ 8000d98: 6039 str r1, [r7, #0]
+
+ if (usart_tx_buf.packet_end[usart_tx_buf.wr_idx] != -1) {
+ 8000d9a: 4b41 ldr r3, [pc, #260] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000d9c: 699b ldr r3, [r3, #24]
+ 8000d9e: 4a40 ldr r2, [pc, #256] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000da0: 3306 adds r3, #6
+ 8000da2: 009b lsls r3, r3, #2
+ 8000da4: 18d3 adds r3, r2, r3
+ 8000da6: 3304 adds r3, #4
+ 8000da8: 681b ldr r3, [r3, #0]
+ 8000daa: 3301 adds r3, #1
+ 8000dac: d007 beq.n 8000dbe <usart_send_packet_nonblocking+0x2e>
+ /* Find a free slot for this packet */
tx_overruns++;
- 8000d82: 4b0d ldr r3, [pc, #52] ; (8000db8 <usart_retransmit_packet+0xa8>)
- 8000d84: 681b ldr r3, [r3, #0]
- 8000d86: 1c5a adds r2, r3, #1
- 8000d88: 4b0b ldr r3, [pc, #44] ; (8000db8 <usart_retransmit_packet+0xa8>)
- 8000d8a: 601a str r2, [r3, #0]
+ 8000dae: 4b3d ldr r3, [pc, #244] ; (8000ea4 <usart_send_packet_nonblocking+0x114>)
+ 8000db0: 681b ldr r3, [r3, #0]
+ 8000db2: 1c5a adds r2, r3, #1
+ 8000db4: 4b3b ldr r3, [pc, #236] ; (8000ea4 <usart_send_packet_nonblocking+0x114>)
+ 8000db6: 601a str r2, [r3, #0]
return -EBUSY;
- 8000d8c: 2310 movs r3, #16
- 8000d8e: 425b negs r3, r3
- 8000d90: e00c b.n 8000dac <usart_retransmit_packet+0x9c>
+ 8000db8: 2310 movs r3, #16
+ 8000dba: 425b negs r3, r3
+ 8000dbc: e06c b.n 8000e98 <usart_send_packet_nonblocking+0x108>
}
- /* Update start index */
- usart_tx_buf.packet_start[idx] = start;
- 8000d92: 1dfb adds r3, r7, #7
- 8000d94: 781b ldrb r3, [r3, #0]
- 8000d96: 4a07 ldr r2, [pc, #28] ; (8000db4 <usart_retransmit_packet+0xa4>)
- 8000d98: 3302 adds r3, #2
- 8000d9a: 009b lsls r3, r3, #2
- 8000d9c: 18d3 adds r3, r2, r3
- 8000d9e: 3304 adds r3, #4
- 8000da0: 693a ldr r2, [r7, #16]
- 8000da2: 601a str r2, [r3, #0]
-
- NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- 8000da4: 2009 movs r0, #9
- 8000da6: f7ff fd39 bl 800081c <NVIC_EnableIRQ>
- return 0;
- 8000daa: 2300 movs r3, #0
-}
- 8000dac: 0018 movs r0, r3
- 8000dae: 46bd mov sp, r7
- 8000db0: b007 add sp, #28
- 8000db2: bd90 pop {r4, r7, pc}
- 8000db4: 20000198 .word 0x20000198
- 8000db8: 20000138 .word 0x20000138
-
-08000dbc <usart_send_packet_nonblocking>:
-
-/* len is the packet length including headers */
-int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
- 8000dbc: b590 push {r4, r7, lr}
- 8000dbe: b087 sub sp, #28
- 8000dc0: af00 add r7, sp, #0
- 8000dc2: 6078 str r0, [r7, #4]
- 8000dc4: 6039 str r1, [r7, #0]
-
- ssize_t start = usart_tx_buf.wr_pos;
- 8000dc6: 4b40 ldr r3, [pc, #256] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
- 8000dc8: 689b ldr r3, [r3, #8]
- 8000dca: 60fb str r3, [r7, #12]
- /* Find a free slot for this packet */
- size_t packet_idx = 0;
- 8000dcc: 2300 movs r3, #0
- 8000dce: 617b str r3, [r7, #20]
- do {
- if (usart_tx_buf.packet_start[packet_idx] == -1)
- 8000dd0: 4a3d ldr r2, [pc, #244] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
- 8000dd2: 697b ldr r3, [r7, #20]
- 8000dd4: 3302 adds r3, #2
- 8000dd6: 009b lsls r3, r3, #2
- 8000dd8: 18d3 adds r3, r2, r3
- 8000dda: 3304 adds r3, #4
- 8000ddc: 681b ldr r3, [r3, #0]
- 8000dde: 3301 adds r3, #1
- 8000de0: d00d beq.n 8000dfe <usart_send_packet_nonblocking+0x42>
- goto success;
- } while (++packet_idx <ARRAY_LEN(usart_tx_buf.packet_start));
- 8000de2: 697b ldr r3, [r7, #20]
- 8000de4: 3301 adds r3, #1
- 8000de6: 617b str r3, [r7, #20]
- 8000de8: 697b ldr r3, [r7, #20]
- 8000dea: 2b04 cmp r3, #4
- 8000dec: d9f0 bls.n 8000dd0 <usart_send_packet_nonblocking+0x14>
-
- tx_overruns++;
- 8000dee: 4b37 ldr r3, [pc, #220] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
- 8000df0: 681b ldr r3, [r3, #0]
- 8000df2: 1c5a adds r2, r3, #1
- 8000df4: 4b35 ldr r3, [pc, #212] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
- 8000df6: 601a str r2, [r3, #0]
- return -EBUSY;
- 8000df8: 2310 movs r3, #16
- 8000dfa: 425b negs r3, r3
- 8000dfc: e060 b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
- goto success;
- 8000dfe: 46c0 nop ; (mov r8, r8)
-
-success:
- pkt->pid = packet_idx;
- 8000e00: 697b ldr r3, [r7, #20]
- 8000e02: b2da uxtb r2, r3
- 8000e04: 687b ldr r3, [r7, #4]
- 8000e06: 711a strb r2, [r3, #4]
+ pkt->pid = usart_tx_buf.wr_idx;
+ 8000dbe: 4b38 ldr r3, [pc, #224] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000dc0: 699b ldr r3, [r3, #24]
+ 8000dc2: b2da uxtb r2, r3
+ 8000dc4: 687b ldr r3, [r7, #4]
+ 8000dc6: 711a strb r2, [r3, #4]
+ pkt->_pad = 0;
+ 8000dc8: 687b ldr r3, [r7, #4]
+ 8000dca: 2200 movs r2, #0
+ 8000dcc: 715a strb r2, [r3, #5]
/* make the value this wonky-ass CRC implementation produces match zlib etc. */
CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET;
- 8000e08: 4b31 ldr r3, [pc, #196] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
- 8000e0a: 22a1 movs r2, #161 ; 0xa1
- 8000e0c: 609a str r2, [r3, #8]
+ 8000dce: 4b36 ldr r3, [pc, #216] ; (8000ea8 <usart_send_packet_nonblocking+0x118>)
+ 8000dd0: 22a1 movs r2, #161 ; 0xa1
+ 8000dd2: 609a str r2, [r3, #8]
for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
- 8000e0e: 2304 movs r3, #4
- 8000e10: 613b str r3, [r7, #16]
- 8000e12: e008 b.n 8000e26 <usart_send_packet_nonblocking+0x6a>
+ 8000dd4: 2304 movs r3, #4
+ 8000dd6: 60fb str r3, [r7, #12]
+ 8000dd8: e008 b.n 8000dec <usart_send_packet_nonblocking+0x5c>
CRC->DR = ((uint8_t *)pkt)[i];
- 8000e14: 687a ldr r2, [r7, #4]
- 8000e16: 693b ldr r3, [r7, #16]
- 8000e18: 18d3 adds r3, r2, r3
- 8000e1a: 781a ldrb r2, [r3, #0]
- 8000e1c: 4b2c ldr r3, [pc, #176] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
- 8000e1e: 601a str r2, [r3, #0]
+ 8000dda: 687a ldr r2, [r7, #4]
+ 8000ddc: 68fb ldr r3, [r7, #12]
+ 8000dde: 18d3 adds r3, r2, r3
+ 8000de0: 781a ldrb r2, [r3, #0]
+ 8000de2: 4b31 ldr r3, [pc, #196] ; (8000ea8 <usart_send_packet_nonblocking+0x118>)
+ 8000de4: 601a str r2, [r3, #0]
for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
- 8000e20: 693b ldr r3, [r7, #16]
- 8000e22: 3301 adds r3, #1
- 8000e24: 613b str r3, [r7, #16]
- 8000e26: 693a ldr r2, [r7, #16]
- 8000e28: 683b ldr r3, [r7, #0]
- 8000e2a: 429a cmp r2, r3
- 8000e2c: d3f2 bcc.n 8000e14 <usart_send_packet_nonblocking+0x58>
+ 8000de6: 68fb ldr r3, [r7, #12]
+ 8000de8: 3301 adds r3, #1
+ 8000dea: 60fb str r3, [r7, #12]
+ 8000dec: 68fa ldr r2, [r7, #12]
+ 8000dee: 683b ldr r3, [r7, #0]
+ 8000df0: 429a cmp r2, r3
+ 8000df2: d3f2 bcc.n 8000dda <usart_send_packet_nonblocking+0x4a>
pkt->crc32 = ~CRC->DR;
- 8000e2e: 4b28 ldr r3, [pc, #160] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
- 8000e30: 681b ldr r3, [r3, #0]
- 8000e32: 43da mvns r2, r3
- 8000e34: 687b ldr r3, [r7, #4]
- 8000e36: 21ff movs r1, #255 ; 0xff
- 8000e38: 4011 ands r1, r2
- 8000e3a: 000c movs r4, r1
- 8000e3c: 7819 ldrb r1, [r3, #0]
- 8000e3e: 2000 movs r0, #0
- 8000e40: 4001 ands r1, r0
- 8000e42: 1c08 adds r0, r1, #0
- 8000e44: 1c21 adds r1, r4, #0
- 8000e46: 4301 orrs r1, r0
- 8000e48: 7019 strb r1, [r3, #0]
- 8000e4a: 0a11 lsrs r1, r2, #8
- 8000e4c: 20ff movs r0, #255 ; 0xff
- 8000e4e: 4001 ands r1, r0
- 8000e50: 000c movs r4, r1
- 8000e52: 7859 ldrb r1, [r3, #1]
- 8000e54: 2000 movs r0, #0
- 8000e56: 4001 ands r1, r0
- 8000e58: 1c08 adds r0, r1, #0
- 8000e5a: 1c21 adds r1, r4, #0
- 8000e5c: 4301 orrs r1, r0
- 8000e5e: 7059 strb r1, [r3, #1]
- 8000e60: 0c11 lsrs r1, r2, #16
- 8000e62: 20ff movs r0, #255 ; 0xff
- 8000e64: 4001 ands r1, r0
- 8000e66: 000c movs r4, r1
- 8000e68: 7899 ldrb r1, [r3, #2]
- 8000e6a: 2000 movs r0, #0
- 8000e6c: 4001 ands r1, r0
- 8000e6e: 1c08 adds r0, r1, #0
- 8000e70: 1c21 adds r1, r4, #0
- 8000e72: 4301 orrs r1, r0
- 8000e74: 7099 strb r1, [r3, #2]
- 8000e76: 0e10 lsrs r0, r2, #24
- 8000e78: 78da ldrb r2, [r3, #3]
- 8000e7a: 2100 movs r1, #0
- 8000e7c: 400a ands r2, r1
- 8000e7e: 1c11 adds r1, r2, #0
- 8000e80: 1c02 adds r2, r0, #0
- 8000e82: 430a orrs r2, r1
- 8000e84: 70da strb r2, [r3, #3]
+ 8000df4: 4b2c ldr r3, [pc, #176] ; (8000ea8 <usart_send_packet_nonblocking+0x118>)
+ 8000df6: 681b ldr r3, [r3, #0]
+ 8000df8: 43da mvns r2, r3
+ 8000dfa: 687b ldr r3, [r7, #4]
+ 8000dfc: 21ff movs r1, #255 ; 0xff
+ 8000dfe: 4011 ands r1, r2
+ 8000e00: 000c movs r4, r1
+ 8000e02: 7819 ldrb r1, [r3, #0]
+ 8000e04: 2000 movs r0, #0
+ 8000e06: 4001 ands r1, r0
+ 8000e08: 1c08 adds r0, r1, #0
+ 8000e0a: 1c21 adds r1, r4, #0
+ 8000e0c: 4301 orrs r1, r0
+ 8000e0e: 7019 strb r1, [r3, #0]
+ 8000e10: 0a11 lsrs r1, r2, #8
+ 8000e12: 20ff movs r0, #255 ; 0xff
+ 8000e14: 4001 ands r1, r0
+ 8000e16: 000c movs r4, r1
+ 8000e18: 7859 ldrb r1, [r3, #1]
+ 8000e1a: 2000 movs r0, #0
+ 8000e1c: 4001 ands r1, r0
+ 8000e1e: 1c08 adds r0, r1, #0
+ 8000e20: 1c21 adds r1, r4, #0
+ 8000e22: 4301 orrs r1, r0
+ 8000e24: 7059 strb r1, [r3, #1]
+ 8000e26: 0c11 lsrs r1, r2, #16
+ 8000e28: 20ff movs r0, #255 ; 0xff
+ 8000e2a: 4001 ands r1, r0
+ 8000e2c: 000c movs r4, r1
+ 8000e2e: 7899 ldrb r1, [r3, #2]
+ 8000e30: 2000 movs r0, #0
+ 8000e32: 4001 ands r1, r0
+ 8000e34: 1c08 adds r0, r1, #0
+ 8000e36: 1c21 adds r1, r4, #0
+ 8000e38: 4301 orrs r1, r0
+ 8000e3a: 7099 strb r1, [r3, #2]
+ 8000e3c: 0e10 lsrs r0, r2, #24
+ 8000e3e: 78da ldrb r2, [r3, #3]
+ 8000e40: 2100 movs r1, #0
+ 8000e42: 400a ands r2, r1
+ 8000e44: 1c11 adds r1, r2, #0
+ 8000e46: 1c02 adds r2, r0, #0
+ 8000e48: 430a orrs r2, r1
+ 8000e4a: 70da strb r2, [r3, #3]
+
int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
- 8000e86: 683a ldr r2, [r7, #0]
- 8000e88: 6879 ldr r1, [r7, #4]
- 8000e8a: 4b12 ldr r3, [pc, #72] ; (8000ed4 <usart_send_packet_nonblocking+0x118>)
- 8000e8c: 0018 movs r0, r3
- 8000e8e: f000 f825 bl 8000edc <cobs_encode_usart>
- 8000e92: 0003 movs r3, r0
- 8000e94: 60bb str r3, [r7, #8]
+ 8000e4c: 683a ldr r2, [r7, #0]
+ 8000e4e: 6879 ldr r1, [r7, #4]
+ 8000e50: 4b16 ldr r3, [pc, #88] ; (8000eac <usart_send_packet_nonblocking+0x11c>)
+ 8000e52: 0018 movs r0, r3
+ 8000e54: f000 f82e bl 8000eb4 <cobs_encode_usart>
+ 8000e58: 0003 movs r3, r0
+ 8000e5a: 60bb str r3, [r7, #8]
if (rc)
- 8000e96: 68bb ldr r3, [r7, #8]
- 8000e98: 2b00 cmp r3, #0
- 8000e9a: d001 beq.n 8000ea0 <usart_send_packet_nonblocking+0xe4>
+ 8000e5c: 68bb ldr r3, [r7, #8]
+ 8000e5e: 2b00 cmp r3, #0
+ 8000e60: d001 beq.n 8000e66 <usart_send_packet_nonblocking+0xd6>
return rc;
- 8000e9c: 68bb ldr r3, [r7, #8]
- 8000e9e: e00f b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
-
- /* Checkpoint packet start index to prevent overwriting before ack */
- usart_tx_buf.packet_start[packet_idx] = start;
- 8000ea0: 4a09 ldr r2, [pc, #36] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
- 8000ea2: 697b ldr r3, [r7, #20]
- 8000ea4: 3302 adds r3, #2
- 8000ea6: 009b lsls r3, r3, #2
- 8000ea8: 18d3 adds r3, r2, r3
- 8000eaa: 3304 adds r3, #4
- 8000eac: 68fa ldr r2, [r7, #12]
- 8000eae: 601a str r2, [r3, #0]
- for (size_t i=0; i<351; i++)
- usart_putc_nonblocking(x++);
- */
+ 8000e62: 68bb ldr r3, [r7, #8]
+ 8000e64: e018 b.n 8000e98 <usart_send_packet_nonblocking+0x108>
+
+ usart_tx_buf.packet_end[usart_tx_buf.wr_idx] = usart_tx_buf.wr_pos;
+ 8000e66: 4b0e ldr r3, [pc, #56] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000e68: 6998 ldr r0, [r3, #24]
+ 8000e6a: 4b0d ldr r3, [pc, #52] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000e6c: 695a ldr r2, [r3, #20]
+ 8000e6e: 490c ldr r1, [pc, #48] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000e70: 1d83 adds r3, r0, #6
+ 8000e72: 009b lsls r3, r3, #2
+ 8000e74: 18cb adds r3, r1, r3
+ 8000e76: 3304 adds r3, #4
+ 8000e78: 601a str r2, [r3, #0]
+ usart_tx_buf.wr_idx = (usart_tx_buf.wr_idx + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
+ 8000e7a: 4b09 ldr r3, [pc, #36] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000e7c: 699b ldr r3, [r3, #24]
+ 8000e7e: 3301 adds r3, #1
+ 8000e80: 2207 movs r2, #7
+ 8000e82: 401a ands r2, r3
+ 8000e84: 4b06 ldr r3, [pc, #24] ; (8000ea0 <usart_send_packet_nonblocking+0x110>)
+ 8000e86: 619a str r2, [r3, #24]
- /* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
- 8000eb0: 4b09 ldr r3, [pc, #36] ; (8000ed8 <usart_send_packet_nonblocking+0x11c>)
- 8000eb2: 681b ldr r3, [r3, #0]
- 8000eb4: 2201 movs r2, #1
- 8000eb6: 4013 ands r3, r2
- 8000eb8: d101 bne.n 8000ebe <usart_send_packet_nonblocking+0x102>
+ 8000e88: 4b09 ldr r3, [pc, #36] ; (8000eb0 <usart_send_packet_nonblocking+0x120>)
+ 8000e8a: 681b ldr r3, [r3, #0]
+ 8000e8c: 2201 movs r2, #1
+ 8000e8e: 4013 ands r3, r2
+ 8000e90: d101 bne.n 8000e96 <usart_send_packet_nonblocking+0x106>
usart_schedule_dma();
- 8000eba: f7ff fe49 bl 8000b50 <usart_schedule_dma>
+ 8000e92: f7ff fe69 bl 8000b68 <usart_schedule_dma>
return 0;
- 8000ebe: 2300 movs r3, #0
+ 8000e96: 2300 movs r3, #0
}
- 8000ec0: 0018 movs r0, r3
- 8000ec2: 46bd mov sp, r7
- 8000ec4: b007 add sp, #28
- 8000ec6: bd90 pop {r4, r7, pc}
- 8000ec8: 20000198 .word 0x20000198
- 8000ecc: 20000138 .word 0x20000138
- 8000ed0: 40023000 .word 0x40023000
- 8000ed4: 08000ca9 .word 0x08000ca9
- 8000ed8: 4002001c .word 0x4002001c
-
-08000edc <cobs_encode_usart>:
+ 8000e98: 0018 movs r0, r3
+ 8000e9a: 46bd mov sp, r7
+ 8000e9c: b005 add sp, #20
+ 8000e9e: bd90 pop {r4, r7, pc}
+ 8000ea0: 20000198 .word 0x20000198
+ 8000ea4: 20000138 .word 0x20000138
+ 8000ea8: 40023000 .word 0x40023000
+ 8000eac: 08000d25 .word 0x08000d25
+ 8000eb0: 4002001c .word 0x4002001c
+
+08000eb4 <cobs_encode_usart>:
#include "serial.h"
#include "cobs.h"
int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) {
- 8000edc: b580 push {r7, lr}
- 8000ede: b08a sub sp, #40 ; 0x28
- 8000ee0: af00 add r7, sp, #0
- 8000ee2: 60f8 str r0, [r7, #12]
- 8000ee4: 60b9 str r1, [r7, #8]
- 8000ee6: 607a str r2, [r7, #4]
+ 8000eb4: b580 push {r7, lr}
+ 8000eb6: b08a sub sp, #40 ; 0x28
+ 8000eb8: af00 add r7, sp, #0
+ 8000eba: 60f8 str r0, [r7, #12]
+ 8000ebc: 60b9 str r1, [r7, #8]
+ 8000ebe: 607a str r2, [r7, #4]
if (srclen > 254)
- 8000ee8: 687b ldr r3, [r7, #4]
- 8000eea: 2bfe cmp r3, #254 ; 0xfe
- 8000eec: d902 bls.n 8000ef4 <cobs_encode_usart+0x18>
+ 8000ec0: 687b ldr r3, [r7, #4]
+ 8000ec2: 2bfe cmp r3, #254 ; 0xfe
+ 8000ec4: d902 bls.n 8000ecc <cobs_encode_usart+0x18>
return -1;
- 8000eee: 2301 movs r3, #1
- 8000ef0: 425b negs r3, r3
- 8000ef2: e04e b.n 8000f92 <cobs_encode_usart+0xb6>
+ 8000ec6: 2301 movs r3, #1
+ 8000ec8: 425b negs r3, r3
+ 8000eca: e04e b.n 8000f6a <cobs_encode_usart+0xb6>
size_t p = 0;
- 8000ef4: 2300 movs r3, #0
- 8000ef6: 627b str r3, [r7, #36] ; 0x24
+ 8000ecc: 2300 movs r3, #0
+ 8000ece: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
- 8000ef8: e03c b.n 8000f74 <cobs_encode_usart+0x98>
+ 8000ed0: e03c b.n 8000f4c <cobs_encode_usart+0x98>
char val;
if (p != 0 && src[p-1] != 0) {
- 8000efa: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000efc: 2b00 cmp r3, #0
- 8000efe: d00f beq.n 8000f20 <cobs_encode_usart+0x44>
- 8000f00: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000f02: 3b01 subs r3, #1
- 8000f04: 68ba ldr r2, [r7, #8]
- 8000f06: 18d3 adds r3, r2, r3
- 8000f08: 781b ldrb r3, [r3, #0]
- 8000f0a: 2b00 cmp r3, #0
- 8000f0c: d008 beq.n 8000f20 <cobs_encode_usart+0x44>
+ 8000ed2: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000ed4: 2b00 cmp r3, #0
+ 8000ed6: d00f beq.n 8000ef8 <cobs_encode_usart+0x44>
+ 8000ed8: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000eda: 3b01 subs r3, #1
+ 8000edc: 68ba ldr r2, [r7, #8]
+ 8000ede: 18d3 adds r3, r2, r3
+ 8000ee0: 781b ldrb r3, [r3, #0]
+ 8000ee2: 2b00 cmp r3, #0
+ 8000ee4: d008 beq.n 8000ef8 <cobs_encode_usart+0x44>
val = src[p-1];
- 8000f0e: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000f10: 3b01 subs r3, #1
- 8000f12: 68ba ldr r2, [r7, #8]
- 8000f14: 18d2 adds r2, r2, r3
- 8000f16: 2323 movs r3, #35 ; 0x23
- 8000f18: 18fb adds r3, r7, r3
- 8000f1a: 7812 ldrb r2, [r2, #0]
- 8000f1c: 701a strb r2, [r3, #0]
- 8000f1e: e019 b.n 8000f54 <cobs_encode_usart+0x78>
+ 8000ee6: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000ee8: 3b01 subs r3, #1
+ 8000eea: 68ba ldr r2, [r7, #8]
+ 8000eec: 18d2 adds r2, r2, r3
+ 8000eee: 2323 movs r3, #35 ; 0x23
+ 8000ef0: 18fb adds r3, r7, r3
+ 8000ef2: 7812 ldrb r2, [r2, #0]
+ 8000ef4: 701a strb r2, [r3, #0]
+ 8000ef6: e019 b.n 8000f2c <cobs_encode_usart+0x78>
} else {
size_t q = p;
- 8000f20: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000f22: 61fb str r3, [r7, #28]
+ 8000ef8: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000efa: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
- 8000f24: e002 b.n 8000f2c <cobs_encode_usart+0x50>
+ 8000efc: e002 b.n 8000f04 <cobs_encode_usart+0x50>
q++;
- 8000f26: 69fb ldr r3, [r7, #28]
- 8000f28: 3301 adds r3, #1
- 8000f2a: 61fb str r3, [r7, #28]
+ 8000efe: 69fb ldr r3, [r7, #28]
+ 8000f00: 3301 adds r3, #1
+ 8000f02: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
- 8000f2c: 69fa ldr r2, [r7, #28]
- 8000f2e: 687b ldr r3, [r7, #4]
- 8000f30: 429a cmp r2, r3
- 8000f32: d205 bcs.n 8000f40 <cobs_encode_usart+0x64>
- 8000f34: 68ba ldr r2, [r7, #8]
- 8000f36: 69fb ldr r3, [r7, #28]
- 8000f38: 18d3 adds r3, r2, r3
- 8000f3a: 781b ldrb r3, [r3, #0]
- 8000f3c: 2b00 cmp r3, #0
- 8000f3e: d1f2 bne.n 8000f26 <cobs_encode_usart+0x4a>
+ 8000f04: 69fa ldr r2, [r7, #28]
+ 8000f06: 687b ldr r3, [r7, #4]
+ 8000f08: 429a cmp r2, r3
+ 8000f0a: d205 bcs.n 8000f18 <cobs_encode_usart+0x64>
+ 8000f0c: 68ba ldr r2, [r7, #8]
+ 8000f0e: 69fb ldr r3, [r7, #28]
+ 8000f10: 18d3 adds r3, r2, r3
+ 8000f12: 781b ldrb r3, [r3, #0]
+ 8000f14: 2b00 cmp r3, #0
+ 8000f16: d1f2 bne.n 8000efe <cobs_encode_usart+0x4a>
val = (char)q-p+1;
- 8000f40: 69fb ldr r3, [r7, #28]
- 8000f42: b2da uxtb r2, r3
- 8000f44: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000f46: b2db uxtb r3, r3
- 8000f48: 1ad3 subs r3, r2, r3
- 8000f4a: b2da uxtb r2, r3
- 8000f4c: 2323 movs r3, #35 ; 0x23
- 8000f4e: 18fb adds r3, r7, r3
- 8000f50: 3201 adds r2, #1
- 8000f52: 701a strb r2, [r3, #0]
+ 8000f18: 69fb ldr r3, [r7, #28]
+ 8000f1a: b2da uxtb r2, r3
+ 8000f1c: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f1e: b2db uxtb r3, r3
+ 8000f20: 1ad3 subs r3, r2, r3
+ 8000f22: b2da uxtb r2, r3
+ 8000f24: 2323 movs r3, #35 ; 0x23
+ 8000f26: 18fb adds r3, r7, r3
+ 8000f28: 3201 adds r2, #1
+ 8000f2a: 701a strb r2, [r3, #0]
}
int rv = output(val);
- 8000f54: 2323 movs r3, #35 ; 0x23
- 8000f56: 18fb adds r3, r7, r3
- 8000f58: 781a ldrb r2, [r3, #0]
- 8000f5a: 68fb ldr r3, [r7, #12]
- 8000f5c: 0010 movs r0, r2
- 8000f5e: 4798 blx r3
- 8000f60: 0003 movs r3, r0
- 8000f62: 617b str r3, [r7, #20]
+ 8000f2c: 2323 movs r3, #35 ; 0x23
+ 8000f2e: 18fb adds r3, r7, r3
+ 8000f30: 781a ldrb r2, [r3, #0]
+ 8000f32: 68fb ldr r3, [r7, #12]
+ 8000f34: 0010 movs r0, r2
+ 8000f36: 4798 blx r3
+ 8000f38: 0003 movs r3, r0
+ 8000f3a: 617b str r3, [r7, #20]
if (rv)
- 8000f64: 697b ldr r3, [r7, #20]
- 8000f66: 2b00 cmp r3, #0
- 8000f68: d001 beq.n 8000f6e <cobs_encode_usart+0x92>
+ 8000f3c: 697b ldr r3, [r7, #20]
+ 8000f3e: 2b00 cmp r3, #0
+ 8000f40: d001 beq.n 8000f46 <cobs_encode_usart+0x92>
return rv;
- 8000f6a: 697b ldr r3, [r7, #20]
- 8000f6c: e011 b.n 8000f92 <cobs_encode_usart+0xb6>
+ 8000f42: 697b ldr r3, [r7, #20]
+ 8000f44: e011 b.n 8000f6a <cobs_encode_usart+0xb6>
p++;
- 8000f6e: 6a7b ldr r3, [r7, #36] ; 0x24
- 8000f70: 3301 adds r3, #1
- 8000f72: 627b str r3, [r7, #36] ; 0x24
+ 8000f46: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000f48: 3301 adds r3, #1
+ 8000f4a: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
- 8000f74: 6a7a ldr r2, [r7, #36] ; 0x24
- 8000f76: 687b ldr r3, [r7, #4]
- 8000f78: 429a cmp r2, r3
- 8000f7a: d9be bls.n 8000efa <cobs_encode_usart+0x1e>
+ 8000f4c: 6a7a ldr r2, [r7, #36] ; 0x24
+ 8000f4e: 687b ldr r3, [r7, #4]
+ 8000f50: 429a cmp r2, r3
+ 8000f52: d9be bls.n 8000ed2 <cobs_encode_usart+0x1e>
}
int rv = output(0);
- 8000f7c: 68fb ldr r3, [r7, #12]
- 8000f7e: 2000 movs r0, #0
- 8000f80: 4798 blx r3
- 8000f82: 0003 movs r3, r0
- 8000f84: 61bb str r3, [r7, #24]
+ 8000f54: 68fb ldr r3, [r7, #12]
+ 8000f56: 2000 movs r0, #0
+ 8000f58: 4798 blx r3
+ 8000f5a: 0003 movs r3, r0
+ 8000f5c: 61bb str r3, [r7, #24]
if (rv)
- 8000f86: 69bb ldr r3, [r7, #24]
- 8000f88: 2b00 cmp r3, #0
- 8000f8a: d001 beq.n 8000f90 <cobs_encode_usart+0xb4>
+ 8000f5e: 69bb ldr r3, [r7, #24]
+ 8000f60: 2b00 cmp r3, #0
+ 8000f62: d001 beq.n 8000f68 <cobs_encode_usart+0xb4>
return rv;
- 8000f8c: 69bb ldr r3, [r7, #24]
- 8000f8e: e000 b.n 8000f92 <cobs_encode_usart+0xb6>
+ 8000f64: 69bb ldr r3, [r7, #24]
+ 8000f66: e000 b.n 8000f6a <cobs_encode_usart+0xb6>
return 0;
- 8000f90: 2300 movs r3, #0
+ 8000f68: 2300 movs r3, #0
}
- 8000f92: 0018 movs r0, r3
- 8000f94: 46bd mov sp, r7
- 8000f96: b00a add sp, #40 ; 0x28
- 8000f98: bd80 pop {r7, pc}
+ 8000f6a: 0018 movs r0, r3
+ 8000f6c: 46bd mov sp, r7
+ 8000f6e: b00a add sp, #40 ; 0x28
+ 8000f70: bd80 pop {r7, pc}
-08000f9a <cobs_decode>:
+08000f72 <cobs_decode>:
@ ensures \result == -1;
@
@ complete behaviors;
@ disjoint behaviors;
@*/
ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) {
- 8000f9a: b580 push {r7, lr}
- 8000f9c: b088 sub sp, #32
- 8000f9e: af00 add r7, sp, #0
- 8000fa0: 60f8 str r0, [r7, #12]
- 8000fa2: 60b9 str r1, [r7, #8]
- 8000fa4: 607a str r2, [r7, #4]
- 8000fa6: 603b str r3, [r7, #0]
+ 8000f72: b580 push {r7, lr}
+ 8000f74: b088 sub sp, #32
+ 8000f76: af00 add r7, sp, #0
+ 8000f78: 60f8 str r0, [r7, #12]
+ 8000f7a: 60b9 str r1, [r7, #8]
+ 8000f7c: 607a str r2, [r7, #4]
+ 8000f7e: 603b str r3, [r7, #0]
if (dstlen > 65535 || srclen > 65535)
- 8000fa8: 68ba ldr r2, [r7, #8]
- 8000faa: 2380 movs r3, #128 ; 0x80
- 8000fac: 025b lsls r3, r3, #9
- 8000fae: 429a cmp r2, r3
- 8000fb0: d204 bcs.n 8000fbc <cobs_decode+0x22>
- 8000fb2: 683a ldr r2, [r7, #0]
- 8000fb4: 2380 movs r3, #128 ; 0x80
- 8000fb6: 025b lsls r3, r3, #9
- 8000fb8: 429a cmp r2, r3
- 8000fba: d302 bcc.n 8000fc2 <cobs_decode+0x28>
+ 8000f80: 68ba ldr r2, [r7, #8]
+ 8000f82: 2380 movs r3, #128 ; 0x80
+ 8000f84: 025b lsls r3, r3, #9
+ 8000f86: 429a cmp r2, r3
+ 8000f88: d204 bcs.n 8000f94 <cobs_decode+0x22>
+ 8000f8a: 683a ldr r2, [r7, #0]
+ 8000f8c: 2380 movs r3, #128 ; 0x80
+ 8000f8e: 025b lsls r3, r3, #9
+ 8000f90: 429a cmp r2, r3
+ 8000f92: d302 bcc.n 8000f9a <cobs_decode+0x28>
return -1;
- 8000fbc: 2301 movs r3, #1
- 8000fbe: 425b negs r3, r3
- 8000fc0: e052 b.n 8001068 <cobs_decode+0xce>
+ 8000f94: 2301 movs r3, #1
+ 8000f96: 425b negs r3, r3
+ 8000f98: e052 b.n 8001040 <cobs_decode+0xce>
if (srclen < 1)
- 8000fc2: 683b ldr r3, [r7, #0]
- 8000fc4: 2b00 cmp r3, #0
- 8000fc6: d102 bne.n 8000fce <cobs_decode+0x34>
+ 8000f9a: 683b ldr r3, [r7, #0]
+ 8000f9c: 2b00 cmp r3, #0
+ 8000f9e: d102 bne.n 8000fa6 <cobs_decode+0x34>
return -1;
- 8000fc8: 2301 movs r3, #1
- 8000fca: 425b negs r3, r3
- 8000fcc: e04c b.n 8001068 <cobs_decode+0xce>
+ 8000fa0: 2301 movs r3, #1
+ 8000fa2: 425b negs r3, r3
+ 8000fa4: e04c b.n 8001040 <cobs_decode+0xce>
if (dstlen < srclen)
- 8000fce: 68ba ldr r2, [r7, #8]
- 8000fd0: 683b ldr r3, [r7, #0]
- 8000fd2: 429a cmp r2, r3
- 8000fd4: d202 bcs.n 8000fdc <cobs_decode+0x42>
+ 8000fa6: 68ba ldr r2, [r7, #8]
+ 8000fa8: 683b ldr r3, [r7, #0]
+ 8000faa: 429a cmp r2, r3
+ 8000fac: d202 bcs.n 8000fb4 <cobs_decode+0x42>
return -1;
- 8000fd6: 2301 movs r3, #1
- 8000fd8: 425b negs r3, r3
- 8000fda: e045 b.n 8001068 <cobs_decode+0xce>
+ 8000fae: 2301 movs r3, #1
+ 8000fb0: 425b negs r3, r3
+ 8000fb2: e045 b.n 8001040 <cobs_decode+0xce>
size_t p = 1;
- 8000fdc: 2301 movs r3, #1
- 8000fde: 61fb str r3, [r7, #28]
+ 8000fb4: 2301 movs r3, #1
+ 8000fb6: 61fb str r3, [r7, #28]
size_t c = (unsigned char)src[0];
- 8000fe0: 687b ldr r3, [r7, #4]
- 8000fe2: 781b ldrb r3, [r3, #0]
- 8000fe4: 61bb str r3, [r7, #24]
+ 8000fb8: 687b ldr r3, [r7, #4]
+ 8000fba: 781b ldrb r3, [r3, #0]
+ 8000fbc: 61bb str r3, [r7, #24]
//@ assert 0 <= c < 256;
//@ assert 0 <= c;
//@ assert c < 256;
if (c == 0)
- 8000fe6: 69bb ldr r3, [r7, #24]
- 8000fe8: 2b00 cmp r3, #0
- 8000fea: d124 bne.n 8001036 <cobs_decode+0x9c>
+ 8000fbe: 69bb ldr r3, [r7, #24]
+ 8000fc0: 2b00 cmp r3, #0
+ 8000fc2: d124 bne.n 800100e <cobs_decode+0x9c>
return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8000fec: 2302 movs r3, #2
- 8000fee: 425b negs r3, r3
- 8000ff0: e03a b.n 8001068 <cobs_decode+0xce>
+ 8000fc4: 2302 movs r3, #2
+ 8000fc6: 425b negs r3, r3
+ 8000fc8: e03a b.n 8001040 <cobs_decode+0xce>
@ loop assigns dst[0..dstlen-1], p, c;
@ loop variant srclen-p;
@*/
while (p < srclen && src[p]) {
char val;
c--;
- 8000ff2: 69bb ldr r3, [r7, #24]
- 8000ff4: 3b01 subs r3, #1
- 8000ff6: 61bb str r3, [r7, #24]
+ 8000fca: 69bb ldr r3, [r7, #24]
+ 8000fcc: 3b01 subs r3, #1
+ 8000fce: 61bb str r3, [r7, #24]
//@ assert src[p] != 0;
if (c == 0) {
- 8000ff8: 69bb ldr r3, [r7, #24]
- 8000ffa: 2b00 cmp r3, #0
- 8000ffc: d109 bne.n 8001012 <cobs_decode+0x78>
+ 8000fd0: 69bb ldr r3, [r7, #24]
+ 8000fd2: 2b00 cmp r3, #0
+ 8000fd4: d109 bne.n 8000fea <cobs_decode+0x78>
c = (unsigned char)src[p];
- 8000ffe: 687a ldr r2, [r7, #4]
- 8001000: 69fb ldr r3, [r7, #28]
- 8001002: 18d3 adds r3, r2, r3
- 8001004: 781b ldrb r3, [r3, #0]
- 8001006: 61bb str r3, [r7, #24]
+ 8000fd6: 687a ldr r2, [r7, #4]
+ 8000fd8: 69fb ldr r3, [r7, #28]
+ 8000fda: 18d3 adds r3, r2, r3
+ 8000fdc: 781b ldrb r3, [r3, #0]
+ 8000fde: 61bb str r3, [r7, #24]
val = 0;
- 8001008: 2317 movs r3, #23
- 800100a: 18fb adds r3, r7, r3
- 800100c: 2200 movs r2, #0
- 800100e: 701a strb r2, [r3, #0]
- 8001010: e006 b.n 8001020 <cobs_decode+0x86>
+ 8000fe0: 2317 movs r3, #23
+ 8000fe2: 18fb adds r3, r7, r3
+ 8000fe4: 2200 movs r2, #0
+ 8000fe6: 701a strb r2, [r3, #0]
+ 8000fe8: e006 b.n 8000ff8 <cobs_decode+0x86>
} else {
val = src[p];
- 8001012: 687a ldr r2, [r7, #4]
- 8001014: 69fb ldr r3, [r7, #28]
- 8001016: 18d2 adds r2, r2, r3
- 8001018: 2317 movs r3, #23
- 800101a: 18fb adds r3, r7, r3
- 800101c: 7812 ldrb r2, [r2, #0]
- 800101e: 701a strb r2, [r3, #0]
+ 8000fea: 687a ldr r2, [r7, #4]
+ 8000fec: 69fb ldr r3, [r7, #28]
+ 8000fee: 18d2 adds r2, r2, r3
+ 8000ff0: 2317 movs r3, #23
+ 8000ff2: 18fb adds r3, r7, r3
+ 8000ff4: 7812 ldrb r2, [r2, #0]
+ 8000ff6: 701a strb r2, [r3, #0]
}
//@ assert 0 <= p-1 <= dstlen-1;
dst[p-1] = val;
- 8001020: 69fb ldr r3, [r7, #28]
- 8001022: 3b01 subs r3, #1
- 8001024: 68fa ldr r2, [r7, #12]
- 8001026: 18d3 adds r3, r2, r3
- 8001028: 2217 movs r2, #23
- 800102a: 18ba adds r2, r7, r2
- 800102c: 7812 ldrb r2, [r2, #0]
- 800102e: 701a strb r2, [r3, #0]
+ 8000ff8: 69fb ldr r3, [r7, #28]
+ 8000ffa: 3b01 subs r3, #1
+ 8000ffc: 68fa ldr r2, [r7, #12]
+ 8000ffe: 18d3 adds r3, r2, r3
+ 8001000: 2217 movs r2, #23
+ 8001002: 18ba adds r2, r7, r2
+ 8001004: 7812 ldrb r2, [r2, #0]
+ 8001006: 701a strb r2, [r3, #0]
p++;
- 8001030: 69fb ldr r3, [r7, #28]
- 8001032: 3301 adds r3, #1
- 8001034: 61fb str r3, [r7, #28]
+ 8001008: 69fb ldr r3, [r7, #28]
+ 800100a: 3301 adds r3, #1
+ 800100c: 61fb str r3, [r7, #28]
while (p < srclen && src[p]) {
- 8001036: 69fa ldr r2, [r7, #28]
- 8001038: 683b ldr r3, [r7, #0]
- 800103a: 429a cmp r2, r3
- 800103c: d205 bcs.n 800104a <cobs_decode+0xb0>
- 800103e: 687a ldr r2, [r7, #4]
- 8001040: 69fb ldr r3, [r7, #28]
- 8001042: 18d3 adds r3, r2, r3
- 8001044: 781b ldrb r3, [r3, #0]
- 8001046: 2b00 cmp r3, #0
- 8001048: d1d3 bne.n 8000ff2 <cobs_decode+0x58>
+ 800100e: 69fa ldr r2, [r7, #28]
+ 8001010: 683b ldr r3, [r7, #0]
+ 8001012: 429a cmp r2, r3
+ 8001014: d205 bcs.n 8001022 <cobs_decode+0xb0>
+ 8001016: 687a ldr r2, [r7, #4]
+ 8001018: 69fb ldr r3, [r7, #28]
+ 800101a: 18d3 adds r3, r2, r3
+ 800101c: 781b ldrb r3, [r3, #0]
+ 800101e: 2b00 cmp r3, #0
+ 8001020: d1d3 bne.n 8000fca <cobs_decode+0x58>
}
if (p == srclen)
- 800104a: 69fa ldr r2, [r7, #28]
- 800104c: 683b ldr r3, [r7, #0]
- 800104e: 429a cmp r2, r3
- 8001050: d102 bne.n 8001058 <cobs_decode+0xbe>
+ 8001022: 69fa ldr r2, [r7, #28]
+ 8001024: 683b ldr r3, [r7, #0]
+ 8001026: 429a cmp r2, r3
+ 8001028: d102 bne.n 8001030 <cobs_decode+0xbe>
return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */
- 8001052: 2302 movs r3, #2
- 8001054: 425b negs r3, r3
- 8001056: e007 b.n 8001068 <cobs_decode+0xce>
+ 800102a: 2302 movs r3, #2
+ 800102c: 425b negs r3, r3
+ 800102e: e007 b.n 8001040 <cobs_decode+0xce>
if (c != 1)
- 8001058: 69bb ldr r3, [r7, #24]
- 800105a: 2b01 cmp r3, #1
- 800105c: d002 beq.n 8001064 <cobs_decode+0xca>
+ 8001030: 69bb ldr r3, [r7, #24]
+ 8001032: 2b01 cmp r3, #1
+ 8001034: d002 beq.n 800103c <cobs_decode+0xca>
return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 800105e: 2303 movs r3, #3
- 8001060: 425b negs r3, r3
- 8001062: e001 b.n 8001068 <cobs_decode+0xce>
+ 8001036: 2303 movs r3, #3
+ 8001038: 425b negs r3, r3
+ 800103a: e001 b.n 8001040 <cobs_decode+0xce>
//@ assert 0 < p <= srclen <= 65535;
//@ assert src[p] == 0;
//@ assert \forall integer i; 1 <= i < p ==> src[i] != 0;
return p-1;
- 8001064: 69fb ldr r3, [r7, #28]
- 8001066: 3b01 subs r3, #1
+ 800103c: 69fb ldr r3, [r7, #28]
+ 800103e: 3b01 subs r3, #1
}
- 8001068: 0018 movs r0, r3
- 800106a: 46bd mov sp, r7
- 800106c: b008 add sp, #32
- 800106e: bd80 pop {r7, pc}
+ 8001040: 0018 movs r0, r3
+ 8001042: 46bd mov sp, r7
+ 8001044: b008 add sp, #32
+ 8001046: bd80 pop {r7, pc}
-08001070 <cobs_decode_incremental_initialize>:
+08001048 <cobs_decode_incremental_initialize>:
void cobs_decode_incremental_initialize(struct cobs_decode_state *state) {
- 8001070: b580 push {r7, lr}
- 8001072: b082 sub sp, #8
- 8001074: af00 add r7, sp, #0
- 8001076: 6078 str r0, [r7, #4]
+ 8001048: b580 push {r7, lr}
+ 800104a: b082 sub sp, #8
+ 800104c: af00 add r7, sp, #0
+ 800104e: 6078 str r0, [r7, #4]
state->p = 0;
- 8001078: 687b ldr r3, [r7, #4]
- 800107a: 2200 movs r2, #0
- 800107c: 601a str r2, [r3, #0]
+ 8001050: 687b ldr r3, [r7, #4]
+ 8001052: 2200 movs r2, #0
+ 8001054: 601a str r2, [r3, #0]
state->c = 0;
- 800107e: 687b ldr r3, [r7, #4]
- 8001080: 2200 movs r2, #0
- 8001082: 605a str r2, [r3, #4]
+ 8001056: 687b ldr r3, [r7, #4]
+ 8001058: 2200 movs r2, #0
+ 800105a: 605a str r2, [r3, #4]
}
- 8001084: 46c0 nop ; (mov r8, r8)
- 8001086: 46bd mov sp, r7
- 8001088: b002 add sp, #8
- 800108a: bd80 pop {r7, pc}
+ 800105c: 46c0 nop ; (mov r8, r8)
+ 800105e: 46bd mov sp, r7
+ 8001060: b002 add sp, #8
+ 8001062: bd80 pop {r7, pc}
-0800108c <cobs_decode_incremental>:
+08001064 <cobs_decode_incremental>:
int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) {
- 800108c: b580 push {r7, lr}
- 800108e: b088 sub sp, #32
- 8001090: af00 add r7, sp, #0
- 8001092: 60f8 str r0, [r7, #12]
- 8001094: 60b9 str r1, [r7, #8]
- 8001096: 607a str r2, [r7, #4]
- 8001098: 001a movs r2, r3
- 800109a: 1cfb adds r3, r7, #3
- 800109c: 701a strb r2, [r3, #0]
+ 8001064: b580 push {r7, lr}
+ 8001066: b088 sub sp, #32
+ 8001068: af00 add r7, sp, #0
+ 800106a: 60f8 str r0, [r7, #12]
+ 800106c: 60b9 str r1, [r7, #8]
+ 800106e: 607a str r2, [r7, #4]
+ 8001070: 001a movs r2, r3
+ 8001072: 1cfb adds r3, r7, #3
+ 8001074: 701a strb r2, [r3, #0]
if (state->p == 0) {
- 800109e: 68fb ldr r3, [r7, #12]
- 80010a0: 681b ldr r3, [r3, #0]
- 80010a2: 2b00 cmp r3, #0
- 80010a4: d10e bne.n 80010c4 <cobs_decode_incremental+0x38>
+ 8001076: 68fb ldr r3, [r7, #12]
+ 8001078: 681b ldr r3, [r3, #0]
+ 800107a: 2b00 cmp r3, #0
+ 800107c: d10e bne.n 800109c <cobs_decode_incremental+0x38>
if (src == 0)
- 80010a6: 1cfb adds r3, r7, #3
- 80010a8: 781b ldrb r3, [r3, #0]
- 80010aa: 2b00 cmp r3, #0
- 80010ac: d054 beq.n 8001158 <cobs_decode_incremental+0xcc>
+ 800107e: 1cfb adds r3, r7, #3
+ 8001080: 781b ldrb r3, [r3, #0]
+ 8001082: 2b00 cmp r3, #0
+ 8001084: d054 beq.n 8001130 <cobs_decode_incremental+0xcc>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
state->c = (unsigned char)src;
- 80010ae: 1cfb adds r3, r7, #3
- 80010b0: 781a ldrb r2, [r3, #0]
- 80010b2: 68fb ldr r3, [r7, #12]
- 80010b4: 605a str r2, [r3, #4]
+ 8001086: 1cfb adds r3, r7, #3
+ 8001088: 781a ldrb r2, [r3, #0]
+ 800108a: 68fb ldr r3, [r7, #12]
+ 800108c: 605a str r2, [r3, #4]
state->p++;
- 80010b6: 68fb ldr r3, [r7, #12]
- 80010b8: 681b ldr r3, [r3, #0]
- 80010ba: 1c5a adds r2, r3, #1
- 80010bc: 68fb ldr r3, [r7, #12]
- 80010be: 601a str r2, [r3, #0]
+ 800108e: 68fb ldr r3, [r7, #12]
+ 8001090: 681b ldr r3, [r3, #0]
+ 8001092: 1c5a adds r2, r3, #1
+ 8001094: 68fb ldr r3, [r7, #12]
+ 8001096: 601a str r2, [r3, #0]
return 0;
- 80010c0: 2300 movs r3, #0
- 80010c2: e050 b.n 8001166 <cobs_decode_incremental+0xda>
+ 8001098: 2300 movs r3, #0
+ 800109a: e050 b.n 800113e <cobs_decode_incremental+0xda>
}
if (!src) {
- 80010c4: 1cfb adds r3, r7, #3
- 80010c6: 781b ldrb r3, [r3, #0]
- 80010c8: 2b00 cmp r3, #0
- 80010ca: d10d bne.n 80010e8 <cobs_decode_incremental+0x5c>
+ 800109c: 1cfb adds r3, r7, #3
+ 800109e: 781b ldrb r3, [r3, #0]
+ 80010a0: 2b00 cmp r3, #0
+ 80010a2: d10d bne.n 80010c0 <cobs_decode_incremental+0x5c>
if (state->c != 1)
- 80010cc: 68fb ldr r3, [r7, #12]
- 80010ce: 685b ldr r3, [r3, #4]
- 80010d0: 2b01 cmp r3, #1
- 80010d2: d139 bne.n 8001148 <cobs_decode_incremental+0xbc>
+ 80010a4: 68fb ldr r3, [r7, #12]
+ 80010a6: 685b ldr r3, [r3, #4]
+ 80010a8: 2b01 cmp r3, #1
+ 80010aa: d139 bne.n 8001120 <cobs_decode_incremental+0xbc>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
int rv = state->p-1;
- 80010d4: 68fb ldr r3, [r7, #12]
- 80010d6: 681b ldr r3, [r3, #0]
- 80010d8: 3b01 subs r3, #1
- 80010da: 617b str r3, [r7, #20]
+ 80010ac: 68fb ldr r3, [r7, #12]
+ 80010ae: 681b ldr r3, [r3, #0]
+ 80010b0: 3b01 subs r3, #1
+ 80010b2: 617b str r3, [r7, #20]
cobs_decode_incremental_initialize(state);
- 80010dc: 68fb ldr r3, [r7, #12]
- 80010de: 0018 movs r0, r3
- 80010e0: f7ff ffc6 bl 8001070 <cobs_decode_incremental_initialize>
+ 80010b4: 68fb ldr r3, [r7, #12]
+ 80010b6: 0018 movs r0, r3
+ 80010b8: f7ff ffc6 bl 8001048 <cobs_decode_incremental_initialize>
return rv;
- 80010e4: 697b ldr r3, [r7, #20]
- 80010e6: e03e b.n 8001166 <cobs_decode_incremental+0xda>
+ 80010bc: 697b ldr r3, [r7, #20]
+ 80010be: e03e b.n 800113e <cobs_decode_incremental+0xda>
}
char val;
state->c--;
- 80010e8: 68fb ldr r3, [r7, #12]
- 80010ea: 685b ldr r3, [r3, #4]
- 80010ec: 1e5a subs r2, r3, #1
- 80010ee: 68fb ldr r3, [r7, #12]
- 80010f0: 605a str r2, [r3, #4]
+ 80010c0: 68fb ldr r3, [r7, #12]
+ 80010c2: 685b ldr r3, [r3, #4]
+ 80010c4: 1e5a subs r2, r3, #1
+ 80010c6: 68fb ldr r3, [r7, #12]
+ 80010c8: 605a str r2, [r3, #4]
if (state->c == 0) {
- 80010f2: 68fb ldr r3, [r7, #12]
- 80010f4: 685b ldr r3, [r3, #4]
- 80010f6: 2b00 cmp r3, #0
- 80010f8: d108 bne.n 800110c <cobs_decode_incremental+0x80>
+ 80010ca: 68fb ldr r3, [r7, #12]
+ 80010cc: 685b ldr r3, [r3, #4]
+ 80010ce: 2b00 cmp r3, #0
+ 80010d0: d108 bne.n 80010e4 <cobs_decode_incremental+0x80>
state->c = (unsigned char)src;
- 80010fa: 1cfb adds r3, r7, #3
- 80010fc: 781a ldrb r2, [r3, #0]
- 80010fe: 68fb ldr r3, [r7, #12]
- 8001100: 605a str r2, [r3, #4]
+ 80010d2: 1cfb adds r3, r7, #3
+ 80010d4: 781a ldrb r2, [r3, #0]
+ 80010d6: 68fb ldr r3, [r7, #12]
+ 80010d8: 605a str r2, [r3, #4]
val = 0;
- 8001102: 231f movs r3, #31
- 8001104: 18fb adds r3, r7, r3
- 8001106: 2200 movs r2, #0
- 8001108: 701a strb r2, [r3, #0]
- 800110a: e004 b.n 8001116 <cobs_decode_incremental+0x8a>
+ 80010da: 231f movs r3, #31
+ 80010dc: 18fb adds r3, r7, r3
+ 80010de: 2200 movs r2, #0
+ 80010e0: 701a strb r2, [r3, #0]
+ 80010e2: e004 b.n 80010ee <cobs_decode_incremental+0x8a>
} else {
val = src;
- 800110c: 231f movs r3, #31
- 800110e: 18fb adds r3, r7, r3
- 8001110: 1cfa adds r2, r7, #3
- 8001112: 7812 ldrb r2, [r2, #0]
- 8001114: 701a strb r2, [r3, #0]
+ 80010e4: 231f movs r3, #31
+ 80010e6: 18fb adds r3, r7, r3
+ 80010e8: 1cfa adds r2, r7, #3
+ 80010ea: 7812 ldrb r2, [r2, #0]
+ 80010ec: 701a strb r2, [r3, #0]
}
size_t pos = state->p-1;
- 8001116: 68fb ldr r3, [r7, #12]
- 8001118: 681b ldr r3, [r3, #0]
- 800111a: 3b01 subs r3, #1
- 800111c: 61bb str r3, [r7, #24]
+ 80010ee: 68fb ldr r3, [r7, #12]
+ 80010f0: 681b ldr r3, [r3, #0]
+ 80010f2: 3b01 subs r3, #1
+ 80010f4: 61bb str r3, [r7, #24]
if (pos >= dstlen)
- 800111e: 69ba ldr r2, [r7, #24]
- 8001120: 687b ldr r3, [r7, #4]
- 8001122: 429a cmp r2, r3
- 8001124: d302 bcc.n 800112c <cobs_decode_incremental+0xa0>
+ 80010f6: 69ba ldr r2, [r7, #24]
+ 80010f8: 687b ldr r3, [r7, #4]
+ 80010fa: 429a cmp r2, r3
+ 80010fc: d302 bcc.n 8001104 <cobs_decode_incremental+0xa0>
return -2; /* output buffer too small */
- 8001126: 2302 movs r3, #2
- 8001128: 425b negs r3, r3
- 800112a: e01c b.n 8001166 <cobs_decode_incremental+0xda>
+ 80010fe: 2302 movs r3, #2
+ 8001100: 425b negs r3, r3
+ 8001102: e01c b.n 800113e <cobs_decode_incremental+0xda>
dst[pos] = val;
- 800112c: 68ba ldr r2, [r7, #8]
- 800112e: 69bb ldr r3, [r7, #24]
- 8001130: 18d3 adds r3, r2, r3
- 8001132: 221f movs r2, #31
- 8001134: 18ba adds r2, r7, r2
- 8001136: 7812 ldrb r2, [r2, #0]
- 8001138: 701a strb r2, [r3, #0]
+ 8001104: 68ba ldr r2, [r7, #8]
+ 8001106: 69bb ldr r3, [r7, #24]
+ 8001108: 18d3 adds r3, r2, r3
+ 800110a: 221f movs r2, #31
+ 800110c: 18ba adds r2, r7, r2
+ 800110e: 7812 ldrb r2, [r2, #0]
+ 8001110: 701a strb r2, [r3, #0]
state->p++;
- 800113a: 68fb ldr r3, [r7, #12]
- 800113c: 681b ldr r3, [r3, #0]
- 800113e: 1c5a adds r2, r3, #1
- 8001140: 68fb ldr r3, [r7, #12]
- 8001142: 601a str r2, [r3, #0]
+ 8001112: 68fb ldr r3, [r7, #12]
+ 8001114: 681b ldr r3, [r3, #0]
+ 8001116: 1c5a adds r2, r3, #1
+ 8001118: 68fb ldr r3, [r7, #12]
+ 800111a: 601a str r2, [r3, #0]
return 0;
- 8001144: 2300 movs r3, #0
- 8001146: e00e b.n 8001166 <cobs_decode_incremental+0xda>
+ 800111c: 2300 movs r3, #0
+ 800111e: e00e b.n 800113e <cobs_decode_incremental+0xda>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 8001148: 46c0 nop ; (mov r8, r8)
+ 8001120: 46c0 nop ; (mov r8, r8)
errout:
cobs_decode_incremental_initialize(state);
- 800114a: 68fb ldr r3, [r7, #12]
- 800114c: 0018 movs r0, r3
- 800114e: f7ff ff8f bl 8001070 <cobs_decode_incremental_initialize>
+ 8001122: 68fb ldr r3, [r7, #12]
+ 8001124: 0018 movs r0, r3
+ 8001126: f7ff ff8f bl 8001048 <cobs_decode_incremental_initialize>
return -1;
- 8001152: 2301 movs r3, #1
- 8001154: 425b negs r3, r3
- 8001156: e006 b.n 8001166 <cobs_decode_incremental+0xda>
+ 800112a: 2301 movs r3, #1
+ 800112c: 425b negs r3, r3
+ 800112e: e006 b.n 800113e <cobs_decode_incremental+0xda>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8001158: 46c0 nop ; (mov r8, r8)
+ 8001130: 46c0 nop ; (mov r8, r8)
empty_errout:
cobs_decode_incremental_initialize(state);
- 800115a: 68fb ldr r3, [r7, #12]
- 800115c: 0018 movs r0, r3
- 800115e: f7ff ff87 bl 8001070 <cobs_decode_incremental_initialize>
+ 8001132: 68fb ldr r3, [r7, #12]
+ 8001134: 0018 movs r0, r3
+ 8001136: f7ff ff87 bl 8001048 <cobs_decode_incremental_initialize>
return -3;
- 8001162: 2303 movs r3, #3
- 8001164: 425b negs r3, r3
+ 800113a: 2303 movs r3, #3
+ 800113c: 425b negs r3, r3
}
- 8001166: 0018 movs r0, r3
- 8001168: 46bd mov sp, r7
- 800116a: b008 add sp, #32
- 800116c: bd80 pop {r7, pc}
- 800116e: 1c64 .short 0x1c64
- 8001170: 00000800 .word 0x00000800
- 8001174: 00942000 .word 0x00942000
- 8001178: 00942000 .word 0x00942000
- 800117c: 03b82000 .word 0x03b82000
- 8001180: 00002000 .word 0x00002000
-
-08001184 <SystemInit>:
+ 800113e: 0018 movs r0, r3
+ 8001140: 46bd mov sp, r7
+ 8001142: b008 add sp, #32
+ 8001144: bd80 pop {r7, pc}
+ 8001146: 1c3c .short 0x1c3c
+ 8001148: 00000800 .word 0x00000800
+ 800114c: 00942000 .word 0x00942000
+ 8001150: 00942000 .word 0x00942000
+ 8001154: 03d42000 .word 0x03d42000
+ 8001158: 00002000 .word 0x00002000
+
+0800115c <SystemInit>:
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 8001184: b580 push {r7, lr}
- 8001186: af00 add r7, sp, #0
+ 800115c: b580 push {r7, lr}
+ 800115e: af00 add r7, sp, #0
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
- 8001188: 4b1a ldr r3, [pc, #104] ; (80011f4 <SystemInit+0x70>)
- 800118a: 681a ldr r2, [r3, #0]
- 800118c: 4b19 ldr r3, [pc, #100] ; (80011f4 <SystemInit+0x70>)
- 800118e: 2101 movs r1, #1
- 8001190: 430a orrs r2, r1
- 8001192: 601a str r2, [r3, #0]
+ 8001160: 4b1a ldr r3, [pc, #104] ; (80011cc <SystemInit+0x70>)
+ 8001162: 681a ldr r2, [r3, #0]
+ 8001164: 4b19 ldr r3, [pc, #100] ; (80011cc <SystemInit+0x70>)
+ 8001166: 2101 movs r1, #1
+ 8001168: 430a orrs r2, r1
+ 800116a: 601a str r2, [r3, #0]
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
- 8001194: 4b17 ldr r3, [pc, #92] ; (80011f4 <SystemInit+0x70>)
- 8001196: 685a ldr r2, [r3, #4]
- 8001198: 4b16 ldr r3, [pc, #88] ; (80011f4 <SystemInit+0x70>)
- 800119a: 4917 ldr r1, [pc, #92] ; (80011f8 <SystemInit+0x74>)
- 800119c: 400a ands r2, r1
- 800119e: 605a str r2, [r3, #4]
+ 800116c: 4b17 ldr r3, [pc, #92] ; (80011cc <SystemInit+0x70>)
+ 800116e: 685a ldr r2, [r3, #4]
+ 8001170: 4b16 ldr r3, [pc, #88] ; (80011cc <SystemInit+0x70>)
+ 8001172: 4917 ldr r1, [pc, #92] ; (80011d0 <SystemInit+0x74>)
+ 8001174: 400a ands r2, r1
+ 8001176: 605a str r2, [r3, #4]
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
- 80011a0: 4b14 ldr r3, [pc, #80] ; (80011f4 <SystemInit+0x70>)
- 80011a2: 681a ldr r2, [r3, #0]
- 80011a4: 4b13 ldr r3, [pc, #76] ; (80011f4 <SystemInit+0x70>)
- 80011a6: 4915 ldr r1, [pc, #84] ; (80011fc <SystemInit+0x78>)
- 80011a8: 400a ands r2, r1
- 80011aa: 601a str r2, [r3, #0]
+ 8001178: 4b14 ldr r3, [pc, #80] ; (80011cc <SystemInit+0x70>)
+ 800117a: 681a ldr r2, [r3, #0]
+ 800117c: 4b13 ldr r3, [pc, #76] ; (80011cc <SystemInit+0x70>)
+ 800117e: 4915 ldr r1, [pc, #84] ; (80011d4 <SystemInit+0x78>)
+ 8001180: 400a ands r2, r1
+ 8001182: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
- 80011ac: 4b11 ldr r3, [pc, #68] ; (80011f4 <SystemInit+0x70>)
- 80011ae: 681a ldr r2, [r3, #0]
- 80011b0: 4b10 ldr r3, [pc, #64] ; (80011f4 <SystemInit+0x70>)
- 80011b2: 4913 ldr r1, [pc, #76] ; (8001200 <SystemInit+0x7c>)
- 80011b4: 400a ands r2, r1
- 80011b6: 601a str r2, [r3, #0]
+ 8001184: 4b11 ldr r3, [pc, #68] ; (80011cc <SystemInit+0x70>)
+ 8001186: 681a ldr r2, [r3, #0]
+ 8001188: 4b10 ldr r3, [pc, #64] ; (80011cc <SystemInit+0x70>)
+ 800118a: 4913 ldr r1, [pc, #76] ; (80011d8 <SystemInit+0x7c>)
+ 800118c: 400a ands r2, r1
+ 800118e: 601a str r2, [r3, #0]
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
- 80011b8: 4b0e ldr r3, [pc, #56] ; (80011f4 <SystemInit+0x70>)
- 80011ba: 685a ldr r2, [r3, #4]
- 80011bc: 4b0d ldr r3, [pc, #52] ; (80011f4 <SystemInit+0x70>)
- 80011be: 4911 ldr r1, [pc, #68] ; (8001204 <SystemInit+0x80>)
- 80011c0: 400a ands r2, r1
- 80011c2: 605a str r2, [r3, #4]
+ 8001190: 4b0e ldr r3, [pc, #56] ; (80011cc <SystemInit+0x70>)
+ 8001192: 685a ldr r2, [r3, #4]
+ 8001194: 4b0d ldr r3, [pc, #52] ; (80011cc <SystemInit+0x70>)
+ 8001196: 4911 ldr r1, [pc, #68] ; (80011dc <SystemInit+0x80>)
+ 8001198: 400a ands r2, r1
+ 800119a: 605a str r2, [r3, #4]
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
- 80011c4: 4b0b ldr r3, [pc, #44] ; (80011f4 <SystemInit+0x70>)
- 80011c6: 6ada ldr r2, [r3, #44] ; 0x2c
- 80011c8: 4b0a ldr r3, [pc, #40] ; (80011f4 <SystemInit+0x70>)
- 80011ca: 210f movs r1, #15
- 80011cc: 438a bics r2, r1
- 80011ce: 62da str r2, [r3, #44] ; 0x2c
+ 800119c: 4b0b ldr r3, [pc, #44] ; (80011cc <SystemInit+0x70>)
+ 800119e: 6ada ldr r2, [r3, #44] ; 0x2c
+ 80011a0: 4b0a ldr r3, [pc, #40] ; (80011cc <SystemInit+0x70>)
+ 80011a2: 210f movs r1, #15
+ 80011a4: 438a bics r2, r1
+ 80011a6: 62da str r2, [r3, #44] ; 0x2c
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
- 80011d0: 4b08 ldr r3, [pc, #32] ; (80011f4 <SystemInit+0x70>)
- 80011d2: 6b1a ldr r2, [r3, #48] ; 0x30
- 80011d4: 4b07 ldr r3, [pc, #28] ; (80011f4 <SystemInit+0x70>)
- 80011d6: 490c ldr r1, [pc, #48] ; (8001208 <SystemInit+0x84>)
- 80011d8: 400a ands r2, r1
- 80011da: 631a str r2, [r3, #48] ; 0x30
+ 80011a8: 4b08 ldr r3, [pc, #32] ; (80011cc <SystemInit+0x70>)
+ 80011aa: 6b1a ldr r2, [r3, #48] ; 0x30
+ 80011ac: 4b07 ldr r3, [pc, #28] ; (80011cc <SystemInit+0x70>)
+ 80011ae: 490c ldr r1, [pc, #48] ; (80011e0 <SystemInit+0x84>)
+ 80011b0: 400a ands r2, r1
+ 80011b2: 631a str r2, [r3, #48] ; 0x30
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
- 80011dc: 4b05 ldr r3, [pc, #20] ; (80011f4 <SystemInit+0x70>)
- 80011de: 6b5a ldr r2, [r3, #52] ; 0x34
- 80011e0: 4b04 ldr r3, [pc, #16] ; (80011f4 <SystemInit+0x70>)
- 80011e2: 2101 movs r1, #1
- 80011e4: 438a bics r2, r1
- 80011e6: 635a str r2, [r3, #52] ; 0x34
+ 80011b4: 4b05 ldr r3, [pc, #20] ; (80011cc <SystemInit+0x70>)
+ 80011b6: 6b5a ldr r2, [r3, #52] ; 0x34
+ 80011b8: 4b04 ldr r3, [pc, #16] ; (80011cc <SystemInit+0x70>)
+ 80011ba: 2101 movs r1, #1
+ 80011bc: 438a bics r2, r1
+ 80011be: 635a str r2, [r3, #52] ; 0x34
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
- 80011e8: 4b02 ldr r3, [pc, #8] ; (80011f4 <SystemInit+0x70>)
- 80011ea: 2200 movs r2, #0
- 80011ec: 609a str r2, [r3, #8]
+ 80011c0: 4b02 ldr r3, [pc, #8] ; (80011cc <SystemInit+0x70>)
+ 80011c2: 2200 movs r2, #0
+ 80011c4: 609a str r2, [r3, #8]
}
- 80011ee: 46c0 nop ; (mov r8, r8)
- 80011f0: 46bd mov sp, r7
- 80011f2: bd80 pop {r7, pc}
- 80011f4: 40021000 .word 0x40021000
- 80011f8: 08ffb80c .word 0x08ffb80c
- 80011fc: fef6ffff .word 0xfef6ffff
- 8001200: fffbffff .word 0xfffbffff
- 8001204: ffc0ffff .word 0xffc0ffff
- 8001208: fffffeec .word 0xfffffeec
-
-0800120c <SystemCoreClockUpdate>:
+ 80011c6: 46c0 nop ; (mov r8, r8)
+ 80011c8: 46bd mov sp, r7
+ 80011ca: bd80 pop {r7, pc}
+ 80011cc: 40021000 .word 0x40021000
+ 80011d0: 08ffb80c .word 0x08ffb80c
+ 80011d4: fef6ffff .word 0xfef6ffff
+ 80011d8: fffbffff .word 0xfffbffff
+ 80011dc: ffc0ffff .word 0xffc0ffff
+ 80011e0: fffffeec .word 0xfffffeec
+
+080011e4 <SystemCoreClockUpdate>:
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
- 800120c: b580 push {r7, lr}
- 800120e: b084 sub sp, #16
- 8001210: af00 add r7, sp, #0
+ 80011e4: b580 push {r7, lr}
+ 80011e6: b084 sub sp, #16
+ 80011e8: af00 add r7, sp, #0
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
- 8001212: 2300 movs r3, #0
- 8001214: 60fb str r3, [r7, #12]
- 8001216: 2300 movs r3, #0
- 8001218: 60bb str r3, [r7, #8]
- 800121a: 2300 movs r3, #0
- 800121c: 607b str r3, [r7, #4]
- 800121e: 2300 movs r3, #0
- 8001220: 603b str r3, [r7, #0]
+ 80011ea: 2300 movs r3, #0
+ 80011ec: 60fb str r3, [r7, #12]
+ 80011ee: 2300 movs r3, #0
+ 80011f0: 60bb str r3, [r7, #8]
+ 80011f2: 2300 movs r3, #0
+ 80011f4: 607b str r3, [r7, #4]
+ 80011f6: 2300 movs r3, #0
+ 80011f8: 603b str r3, [r7, #0]
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
- 8001222: 4b31 ldr r3, [pc, #196] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
- 8001224: 685b ldr r3, [r3, #4]
- 8001226: 220c movs r2, #12
- 8001228: 4013 ands r3, r2
- 800122a: 60fb str r3, [r7, #12]
+ 80011fa: 4b31 ldr r3, [pc, #196] ; (80012c0 <SystemCoreClockUpdate+0xdc>)
+ 80011fc: 685b ldr r3, [r3, #4]
+ 80011fe: 220c movs r2, #12
+ 8001200: 4013 ands r3, r2
+ 8001202: 60fb str r3, [r7, #12]
switch (tmp)
- 800122c: 68fb ldr r3, [r7, #12]
- 800122e: 2b08 cmp r3, #8
- 8001230: d011 beq.n 8001256 <SystemCoreClockUpdate+0x4a>
- 8001232: 68fb ldr r3, [r7, #12]
- 8001234: 2b08 cmp r3, #8
- 8001236: d841 bhi.n 80012bc <SystemCoreClockUpdate+0xb0>
- 8001238: 68fb ldr r3, [r7, #12]
- 800123a: 2b00 cmp r3, #0
- 800123c: d003 beq.n 8001246 <SystemCoreClockUpdate+0x3a>
- 800123e: 68fb ldr r3, [r7, #12]
- 8001240: 2b04 cmp r3, #4
- 8001242: d004 beq.n 800124e <SystemCoreClockUpdate+0x42>
- 8001244: e03a b.n 80012bc <SystemCoreClockUpdate+0xb0>
+ 8001204: 68fb ldr r3, [r7, #12]
+ 8001206: 2b08 cmp r3, #8
+ 8001208: d011 beq.n 800122e <SystemCoreClockUpdate+0x4a>
+ 800120a: 68fb ldr r3, [r7, #12]
+ 800120c: 2b08 cmp r3, #8
+ 800120e: d841 bhi.n 8001294 <SystemCoreClockUpdate+0xb0>
+ 8001210: 68fb ldr r3, [r7, #12]
+ 8001212: 2b00 cmp r3, #0
+ 8001214: d003 beq.n 800121e <SystemCoreClockUpdate+0x3a>
+ 8001216: 68fb ldr r3, [r7, #12]
+ 8001218: 2b04 cmp r3, #4
+ 800121a: d004 beq.n 8001226 <SystemCoreClockUpdate+0x42>
+ 800121c: e03a b.n 8001294 <SystemCoreClockUpdate+0xb0>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 8001246: 4b29 ldr r3, [pc, #164] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 8001248: 4a29 ldr r2, [pc, #164] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
- 800124a: 601a str r2, [r3, #0]
+ 800121e: 4b29 ldr r3, [pc, #164] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 8001220: 4a29 ldr r2, [pc, #164] ; (80012c8 <SystemCoreClockUpdate+0xe4>)
+ 8001222: 601a str r2, [r3, #0]
break;
- 800124c: e03a b.n 80012c4 <SystemCoreClockUpdate+0xb8>
+ 8001224: e03a b.n 800129c <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
- 800124e: 4b27 ldr r3, [pc, #156] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 8001250: 4a27 ldr r2, [pc, #156] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
- 8001252: 601a str r2, [r3, #0]
+ 8001226: 4b27 ldr r3, [pc, #156] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 8001228: 4a27 ldr r2, [pc, #156] ; (80012c8 <SystemCoreClockUpdate+0xe4>)
+ 800122a: 601a str r2, [r3, #0]
break;
- 8001254: e036 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
+ 800122c: e036 b.n 800129c <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- 8001256: 4b24 ldr r3, [pc, #144] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
- 8001258: 685a ldr r2, [r3, #4]
- 800125a: 23f0 movs r3, #240 ; 0xf0
- 800125c: 039b lsls r3, r3, #14
- 800125e: 4013 ands r3, r2
- 8001260: 60bb str r3, [r7, #8]
+ 800122e: 4b24 ldr r3, [pc, #144] ; (80012c0 <SystemCoreClockUpdate+0xdc>)
+ 8001230: 685a ldr r2, [r3, #4]
+ 8001232: 23f0 movs r3, #240 ; 0xf0
+ 8001234: 039b lsls r3, r3, #14
+ 8001236: 4013 ands r3, r2
+ 8001238: 60bb str r3, [r7, #8]
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- 8001262: 4b21 ldr r3, [pc, #132] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
- 8001264: 685a ldr r2, [r3, #4]
- 8001266: 2380 movs r3, #128 ; 0x80
- 8001268: 025b lsls r3, r3, #9
- 800126a: 4013 ands r3, r2
- 800126c: 607b str r3, [r7, #4]
+ 800123a: 4b21 ldr r3, [pc, #132] ; (80012c0 <SystemCoreClockUpdate+0xdc>)
+ 800123c: 685a ldr r2, [r3, #4]
+ 800123e: 2380 movs r3, #128 ; 0x80
+ 8001240: 025b lsls r3, r3, #9
+ 8001242: 4013 ands r3, r2
+ 8001244: 607b str r3, [r7, #4]
pllmull = ( pllmull >> 18) + 2;
- 800126e: 68bb ldr r3, [r7, #8]
- 8001270: 0c9b lsrs r3, r3, #18
- 8001272: 3302 adds r3, #2
- 8001274: 60bb str r3, [r7, #8]
+ 8001246: 68bb ldr r3, [r7, #8]
+ 8001248: 0c9b lsrs r3, r3, #18
+ 800124a: 3302 adds r3, #2
+ 800124c: 60bb str r3, [r7, #8]
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- 8001276: 4b1c ldr r3, [pc, #112] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
- 8001278: 6adb ldr r3, [r3, #44] ; 0x2c
- 800127a: 220f movs r2, #15
- 800127c: 4013 ands r3, r2
- 800127e: 3301 adds r3, #1
- 8001280: 603b str r3, [r7, #0]
+ 800124e: 4b1c ldr r3, [pc, #112] ; (80012c0 <SystemCoreClockUpdate+0xdc>)
+ 8001250: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8001252: 220f movs r2, #15
+ 8001254: 4013 ands r3, r2
+ 8001256: 3301 adds r3, #1
+ 8001258: 603b str r3, [r7, #0]
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- 8001282: 687a ldr r2, [r7, #4]
- 8001284: 2380 movs r3, #128 ; 0x80
- 8001286: 025b lsls r3, r3, #9
- 8001288: 429a cmp r2, r3
- 800128a: d10a bne.n 80012a2 <SystemCoreClockUpdate+0x96>
+ 800125a: 687a ldr r2, [r7, #4]
+ 800125c: 2380 movs r3, #128 ; 0x80
+ 800125e: 025b lsls r3, r3, #9
+ 8001260: 429a cmp r2, r3
+ 8001262: d10a bne.n 800127a <SystemCoreClockUpdate+0x96>
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- 800128c: 6839 ldr r1, [r7, #0]
- 800128e: 4818 ldr r0, [pc, #96] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
- 8001290: f000 fb3e bl 8001910 <__udivsi3>
- 8001294: 0003 movs r3, r0
- 8001296: 001a movs r2, r3
- 8001298: 68bb ldr r3, [r7, #8]
- 800129a: 435a muls r2, r3
- 800129c: 4b13 ldr r3, [pc, #76] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 800129e: 601a str r2, [r3, #0]
+ 8001264: 6839 ldr r1, [r7, #0]
+ 8001266: 4818 ldr r0, [pc, #96] ; (80012c8 <SystemCoreClockUpdate+0xe4>)
+ 8001268: f000 fb3e bl 80018e8 <__udivsi3>
+ 800126c: 0003 movs r3, r0
+ 800126e: 001a movs r2, r3
+ 8001270: 68bb ldr r3, [r7, #8]
+ 8001272: 435a muls r2, r3
+ 8001274: 4b13 ldr r3, [pc, #76] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 8001276: 601a str r2, [r3, #0]
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
- 80012a0: e010 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
+ 8001278: e010 b.n 800129c <SystemCoreClockUpdate+0xb8>
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- 80012a2: 68b9 ldr r1, [r7, #8]
- 80012a4: 000a movs r2, r1
- 80012a6: 0152 lsls r2, r2, #5
- 80012a8: 1a52 subs r2, r2, r1
- 80012aa: 0193 lsls r3, r2, #6
- 80012ac: 1a9b subs r3, r3, r2
- 80012ae: 00db lsls r3, r3, #3
- 80012b0: 185b adds r3, r3, r1
- 80012b2: 021b lsls r3, r3, #8
- 80012b4: 001a movs r2, r3
- 80012b6: 4b0d ldr r3, [pc, #52] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 80012b8: 601a str r2, [r3, #0]
+ 800127a: 68b9 ldr r1, [r7, #8]
+ 800127c: 000a movs r2, r1
+ 800127e: 0152 lsls r2, r2, #5
+ 8001280: 1a52 subs r2, r2, r1
+ 8001282: 0193 lsls r3, r2, #6
+ 8001284: 1a9b subs r3, r3, r2
+ 8001286: 00db lsls r3, r3, #3
+ 8001288: 185b adds r3, r3, r1
+ 800128a: 021b lsls r3, r3, #8
+ 800128c: 001a movs r2, r3
+ 800128e: 4b0d ldr r3, [pc, #52] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 8001290: 601a str r2, [r3, #0]
break;
- 80012ba: e003 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
+ 8001292: e003 b.n 800129c <SystemCoreClockUpdate+0xb8>
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 80012bc: 4b0b ldr r3, [pc, #44] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 80012be: 4a0c ldr r2, [pc, #48] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
- 80012c0: 601a str r2, [r3, #0]
+ 8001294: 4b0b ldr r3, [pc, #44] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 8001296: 4a0c ldr r2, [pc, #48] ; (80012c8 <SystemCoreClockUpdate+0xe4>)
+ 8001298: 601a str r2, [r3, #0]
break;
- 80012c2: 46c0 nop ; (mov r8, r8)
+ 800129a: 46c0 nop ; (mov r8, r8)
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- 80012c4: 4b08 ldr r3, [pc, #32] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
- 80012c6: 685b ldr r3, [r3, #4]
- 80012c8: 091b lsrs r3, r3, #4
- 80012ca: 220f movs r2, #15
- 80012cc: 4013 ands r3, r2
- 80012ce: 4a09 ldr r2, [pc, #36] ; (80012f4 <SystemCoreClockUpdate+0xe8>)
- 80012d0: 5cd3 ldrb r3, [r2, r3]
- 80012d2: 60fb str r3, [r7, #12]
+ 800129c: 4b08 ldr r3, [pc, #32] ; (80012c0 <SystemCoreClockUpdate+0xdc>)
+ 800129e: 685b ldr r3, [r3, #4]
+ 80012a0: 091b lsrs r3, r3, #4
+ 80012a2: 220f movs r2, #15
+ 80012a4: 4013 ands r3, r2
+ 80012a6: 4a09 ldr r2, [pc, #36] ; (80012cc <SystemCoreClockUpdate+0xe8>)
+ 80012a8: 5cd3 ldrb r3, [r2, r3]
+ 80012aa: 60fb str r3, [r7, #12]
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
- 80012d4: 4b05 ldr r3, [pc, #20] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 80012d6: 681a ldr r2, [r3, #0]
- 80012d8: 68fb ldr r3, [r7, #12]
- 80012da: 40da lsrs r2, r3
- 80012dc: 4b03 ldr r3, [pc, #12] ; (80012ec <SystemCoreClockUpdate+0xe0>)
- 80012de: 601a str r2, [r3, #0]
+ 80012ac: 4b05 ldr r3, [pc, #20] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 80012ae: 681a ldr r2, [r3, #0]
+ 80012b0: 68fb ldr r3, [r7, #12]
+ 80012b2: 40da lsrs r2, r3
+ 80012b4: 4b03 ldr r3, [pc, #12] ; (80012c4 <SystemCoreClockUpdate+0xe0>)
+ 80012b6: 601a str r2, [r3, #0]
}
- 80012e0: 46c0 nop ; (mov r8, r8)
- 80012e2: 46bd mov sp, r7
- 80012e4: b004 add sp, #16
- 80012e6: bd80 pop {r7, pc}
- 80012e8: 40021000 .word 0x40021000
- 80012ec: 20000000 .word 0x20000000
- 80012f0: 007a1200 .word 0x007a1200
- 80012f4: 08001c4c .word 0x08001c4c
-
-080012f8 <LL_RCC_HSE_EnableBypass>:
+ 80012b8: 46c0 nop ; (mov r8, r8)
+ 80012ba: 46bd mov sp, r7
+ 80012bc: b004 add sp, #16
+ 80012be: bd80 pop {r7, pc}
+ 80012c0: 40021000 .word 0x40021000
+ 80012c4: 20000000 .word 0x20000000
+ 80012c8: 007a1200 .word 0x007a1200
+ 80012cc: 08001c24 .word 0x08001c24
+
+080012d0 <LL_RCC_HSE_EnableBypass>:
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
- 80012f8: b580 push {r7, lr}
- 80012fa: af00 add r7, sp, #0
+ 80012d0: b580 push {r7, lr}
+ 80012d2: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
- 80012fc: 4b04 ldr r3, [pc, #16] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
- 80012fe: 681a ldr r2, [r3, #0]
- 8001300: 4b03 ldr r3, [pc, #12] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
- 8001302: 2180 movs r1, #128 ; 0x80
- 8001304: 02c9 lsls r1, r1, #11
- 8001306: 430a orrs r2, r1
- 8001308: 601a str r2, [r3, #0]
+ 80012d4: 4b04 ldr r3, [pc, #16] ; (80012e8 <LL_RCC_HSE_EnableBypass+0x18>)
+ 80012d6: 681a ldr r2, [r3, #0]
+ 80012d8: 4b03 ldr r3, [pc, #12] ; (80012e8 <LL_RCC_HSE_EnableBypass+0x18>)
+ 80012da: 2180 movs r1, #128 ; 0x80
+ 80012dc: 02c9 lsls r1, r1, #11
+ 80012de: 430a orrs r2, r1
+ 80012e0: 601a str r2, [r3, #0]
}
- 800130a: 46c0 nop ; (mov r8, r8)
- 800130c: 46bd mov sp, r7
- 800130e: bd80 pop {r7, pc}
- 8001310: 40021000 .word 0x40021000
+ 80012e2: 46c0 nop ; (mov r8, r8)
+ 80012e4: 46bd mov sp, r7
+ 80012e6: bd80 pop {r7, pc}
+ 80012e8: 40021000 .word 0x40021000
-08001314 <LL_RCC_HSE_DisableBypass>:
+080012ec <LL_RCC_HSE_DisableBypass>:
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
- 8001314: b580 push {r7, lr}
- 8001316: af00 add r7, sp, #0
+ 80012ec: b580 push {r7, lr}
+ 80012ee: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
- 8001318: 4b04 ldr r3, [pc, #16] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
- 800131a: 681a ldr r2, [r3, #0]
- 800131c: 4b03 ldr r3, [pc, #12] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
- 800131e: 4904 ldr r1, [pc, #16] ; (8001330 <LL_RCC_HSE_DisableBypass+0x1c>)
- 8001320: 400a ands r2, r1
- 8001322: 601a str r2, [r3, #0]
+ 80012f0: 4b04 ldr r3, [pc, #16] ; (8001304 <LL_RCC_HSE_DisableBypass+0x18>)
+ 80012f2: 681a ldr r2, [r3, #0]
+ 80012f4: 4b03 ldr r3, [pc, #12] ; (8001304 <LL_RCC_HSE_DisableBypass+0x18>)
+ 80012f6: 4904 ldr r1, [pc, #16] ; (8001308 <LL_RCC_HSE_DisableBypass+0x1c>)
+ 80012f8: 400a ands r2, r1
+ 80012fa: 601a str r2, [r3, #0]
}
- 8001324: 46c0 nop ; (mov r8, r8)
- 8001326: 46bd mov sp, r7
- 8001328: bd80 pop {r7, pc}
- 800132a: 46c0 nop ; (mov r8, r8)
- 800132c: 40021000 .word 0x40021000
- 8001330: fffbffff .word 0xfffbffff
-
-08001334 <LL_RCC_HSE_Enable>:
+ 80012fc: 46c0 nop ; (mov r8, r8)
+ 80012fe: 46bd mov sp, r7
+ 8001300: bd80 pop {r7, pc}
+ 8001302: 46c0 nop ; (mov r8, r8)
+ 8001304: 40021000 .word 0x40021000
+ 8001308: fffbffff .word 0xfffbffff
+
+0800130c <LL_RCC_HSE_Enable>:
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
- 8001334: b580 push {r7, lr}
- 8001336: af00 add r7, sp, #0
+ 800130c: b580 push {r7, lr}
+ 800130e: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEON);
- 8001338: 4b04 ldr r3, [pc, #16] ; (800134c <LL_RCC_HSE_Enable+0x18>)
- 800133a: 681a ldr r2, [r3, #0]
- 800133c: 4b03 ldr r3, [pc, #12] ; (800134c <LL_RCC_HSE_Enable+0x18>)
- 800133e: 2180 movs r1, #128 ; 0x80
- 8001340: 0249 lsls r1, r1, #9
- 8001342: 430a orrs r2, r1
- 8001344: 601a str r2, [r3, #0]
+ 8001310: 4b04 ldr r3, [pc, #16] ; (8001324 <LL_RCC_HSE_Enable+0x18>)
+ 8001312: 681a ldr r2, [r3, #0]
+ 8001314: 4b03 ldr r3, [pc, #12] ; (8001324 <LL_RCC_HSE_Enable+0x18>)
+ 8001316: 2180 movs r1, #128 ; 0x80
+ 8001318: 0249 lsls r1, r1, #9
+ 800131a: 430a orrs r2, r1
+ 800131c: 601a str r2, [r3, #0]
}
- 8001346: 46c0 nop ; (mov r8, r8)
- 8001348: 46bd mov sp, r7
- 800134a: bd80 pop {r7, pc}
- 800134c: 40021000 .word 0x40021000
+ 800131e: 46c0 nop ; (mov r8, r8)
+ 8001320: 46bd mov sp, r7
+ 8001322: bd80 pop {r7, pc}
+ 8001324: 40021000 .word 0x40021000
-08001350 <LL_RCC_HSE_IsReady>:
+08001328 <LL_RCC_HSE_IsReady>:
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
- 8001350: b580 push {r7, lr}
- 8001352: af00 add r7, sp, #0
+ 8001328: b580 push {r7, lr}
+ 800132a: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
- 8001354: 4b06 ldr r3, [pc, #24] ; (8001370 <LL_RCC_HSE_IsReady+0x20>)
- 8001356: 681a ldr r2, [r3, #0]
- 8001358: 2380 movs r3, #128 ; 0x80
- 800135a: 029b lsls r3, r3, #10
- 800135c: 4013 ands r3, r2
- 800135e: 4a05 ldr r2, [pc, #20] ; (8001374 <LL_RCC_HSE_IsReady+0x24>)
- 8001360: 4694 mov ip, r2
- 8001362: 4463 add r3, ip
- 8001364: 425a negs r2, r3
- 8001366: 4153 adcs r3, r2
- 8001368: b2db uxtb r3, r3
+ 800132c: 4b06 ldr r3, [pc, #24] ; (8001348 <LL_RCC_HSE_IsReady+0x20>)
+ 800132e: 681a ldr r2, [r3, #0]
+ 8001330: 2380 movs r3, #128 ; 0x80
+ 8001332: 029b lsls r3, r3, #10
+ 8001334: 4013 ands r3, r2
+ 8001336: 4a05 ldr r2, [pc, #20] ; (800134c <LL_RCC_HSE_IsReady+0x24>)
+ 8001338: 4694 mov ip, r2
+ 800133a: 4463 add r3, ip
+ 800133c: 425a negs r2, r3
+ 800133e: 4153 adcs r3, r2
+ 8001340: b2db uxtb r3, r3
}
- 800136a: 0018 movs r0, r3
- 800136c: 46bd mov sp, r7
- 800136e: bd80 pop {r7, pc}
- 8001370: 40021000 .word 0x40021000
- 8001374: fffe0000 .word 0xfffe0000
+ 8001342: 0018 movs r0, r3
+ 8001344: 46bd mov sp, r7
+ 8001346: bd80 pop {r7, pc}
+ 8001348: 40021000 .word 0x40021000
+ 800134c: fffe0000 .word 0xfffe0000
-08001378 <LL_RCC_HSI_Enable>:
+08001350 <LL_RCC_HSI_Enable>:
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
- 8001378: b580 push {r7, lr}
- 800137a: af00 add r7, sp, #0
+ 8001350: b580 push {r7, lr}
+ 8001352: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSION);
- 800137c: 4b04 ldr r3, [pc, #16] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
- 800137e: 681a ldr r2, [r3, #0]
- 8001380: 4b03 ldr r3, [pc, #12] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
- 8001382: 2101 movs r1, #1
- 8001384: 430a orrs r2, r1
- 8001386: 601a str r2, [r3, #0]
+ 8001354: 4b04 ldr r3, [pc, #16] ; (8001368 <LL_RCC_HSI_Enable+0x18>)
+ 8001356: 681a ldr r2, [r3, #0]
+ 8001358: 4b03 ldr r3, [pc, #12] ; (8001368 <LL_RCC_HSI_Enable+0x18>)
+ 800135a: 2101 movs r1, #1
+ 800135c: 430a orrs r2, r1
+ 800135e: 601a str r2, [r3, #0]
}
- 8001388: 46c0 nop ; (mov r8, r8)
- 800138a: 46bd mov sp, r7
- 800138c: bd80 pop {r7, pc}
- 800138e: 46c0 nop ; (mov r8, r8)
- 8001390: 40021000 .word 0x40021000
+ 8001360: 46c0 nop ; (mov r8, r8)
+ 8001362: 46bd mov sp, r7
+ 8001364: bd80 pop {r7, pc}
+ 8001366: 46c0 nop ; (mov r8, r8)
+ 8001368: 40021000 .word 0x40021000
-08001394 <LL_RCC_HSI_IsReady>:
+0800136c <LL_RCC_HSI_IsReady>:
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
- 8001394: b580 push {r7, lr}
- 8001396: af00 add r7, sp, #0
+ 800136c: b580 push {r7, lr}
+ 800136e: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
- 8001398: 4b05 ldr r3, [pc, #20] ; (80013b0 <LL_RCC_HSI_IsReady+0x1c>)
- 800139a: 681b ldr r3, [r3, #0]
- 800139c: 2202 movs r2, #2
- 800139e: 4013 ands r3, r2
- 80013a0: 3b02 subs r3, #2
- 80013a2: 425a negs r2, r3
- 80013a4: 4153 adcs r3, r2
- 80013a6: b2db uxtb r3, r3
+ 8001370: 4b05 ldr r3, [pc, #20] ; (8001388 <LL_RCC_HSI_IsReady+0x1c>)
+ 8001372: 681b ldr r3, [r3, #0]
+ 8001374: 2202 movs r2, #2
+ 8001376: 4013 ands r3, r2
+ 8001378: 3b02 subs r3, #2
+ 800137a: 425a negs r2, r3
+ 800137c: 4153 adcs r3, r2
+ 800137e: b2db uxtb r3, r3
}
- 80013a8: 0018 movs r0, r3
- 80013aa: 46bd mov sp, r7
- 80013ac: bd80 pop {r7, pc}
- 80013ae: 46c0 nop ; (mov r8, r8)
- 80013b0: 40021000 .word 0x40021000
+ 8001380: 0018 movs r0, r3
+ 8001382: 46bd mov sp, r7
+ 8001384: bd80 pop {r7, pc}
+ 8001386: 46c0 nop ; (mov r8, r8)
+ 8001388: 40021000 .word 0x40021000
-080013b4 <LL_RCC_SetSysClkSource>:
+0800138c <LL_RCC_SetSysClkSource>:
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
- 80013b4: b580 push {r7, lr}
- 80013b6: b082 sub sp, #8
- 80013b8: af00 add r7, sp, #0
- 80013ba: 6078 str r0, [r7, #4]
+ 800138c: b580 push {r7, lr}
+ 800138e: b082 sub sp, #8
+ 8001390: af00 add r7, sp, #0
+ 8001392: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
- 80013bc: 4b06 ldr r3, [pc, #24] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
- 80013be: 685b ldr r3, [r3, #4]
- 80013c0: 2203 movs r2, #3
- 80013c2: 4393 bics r3, r2
- 80013c4: 0019 movs r1, r3
- 80013c6: 4b04 ldr r3, [pc, #16] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
- 80013c8: 687a ldr r2, [r7, #4]
- 80013ca: 430a orrs r2, r1
- 80013cc: 605a str r2, [r3, #4]
+ 8001394: 4b06 ldr r3, [pc, #24] ; (80013b0 <LL_RCC_SetSysClkSource+0x24>)
+ 8001396: 685b ldr r3, [r3, #4]
+ 8001398: 2203 movs r2, #3
+ 800139a: 4393 bics r3, r2
+ 800139c: 0019 movs r1, r3
+ 800139e: 4b04 ldr r3, [pc, #16] ; (80013b0 <LL_RCC_SetSysClkSource+0x24>)
+ 80013a0: 687a ldr r2, [r7, #4]
+ 80013a2: 430a orrs r2, r1
+ 80013a4: 605a str r2, [r3, #4]
}
- 80013ce: 46c0 nop ; (mov r8, r8)
- 80013d0: 46bd mov sp, r7
- 80013d2: b002 add sp, #8
- 80013d4: bd80 pop {r7, pc}
- 80013d6: 46c0 nop ; (mov r8, r8)
- 80013d8: 40021000 .word 0x40021000
-
-080013dc <LL_RCC_GetSysClkSource>:
+ 80013a6: 46c0 nop ; (mov r8, r8)
+ 80013a8: 46bd mov sp, r7
+ 80013aa: b002 add sp, #8
+ 80013ac: bd80 pop {r7, pc}
+ 80013ae: 46c0 nop ; (mov r8, r8)
+ 80013b0: 40021000 .word 0x40021000
+
+080013b4 <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
- 80013dc: b580 push {r7, lr}
- 80013de: af00 add r7, sp, #0
+ 80013b4: b580 push {r7, lr}
+ 80013b6: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
- 80013e0: 4b03 ldr r3, [pc, #12] ; (80013f0 <LL_RCC_GetSysClkSource+0x14>)
- 80013e2: 685b ldr r3, [r3, #4]
- 80013e4: 220c movs r2, #12
- 80013e6: 4013 ands r3, r2
+ 80013b8: 4b03 ldr r3, [pc, #12] ; (80013c8 <LL_RCC_GetSysClkSource+0x14>)
+ 80013ba: 685b ldr r3, [r3, #4]
+ 80013bc: 220c movs r2, #12
+ 80013be: 4013 ands r3, r2
}
- 80013e8: 0018 movs r0, r3
- 80013ea: 46bd mov sp, r7
- 80013ec: bd80 pop {r7, pc}
- 80013ee: 46c0 nop ; (mov r8, r8)
- 80013f0: 40021000 .word 0x40021000
+ 80013c0: 0018 movs r0, r3
+ 80013c2: 46bd mov sp, r7
+ 80013c4: bd80 pop {r7, pc}
+ 80013c6: 46c0 nop ; (mov r8, r8)
+ 80013c8: 40021000 .word 0x40021000
-080013f4 <LL_RCC_SetAHBPrescaler>:
+080013cc <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
+ 80013cc: b580 push {r7, lr}
+ 80013ce: b082 sub sp, #8
+ 80013d0: af00 add r7, sp, #0
+ 80013d2: 6078 str r0, [r7, #4]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+ 80013d4: 4b06 ldr r3, [pc, #24] ; (80013f0 <LL_RCC_SetAHBPrescaler+0x24>)
+ 80013d6: 685b ldr r3, [r3, #4]
+ 80013d8: 22f0 movs r2, #240 ; 0xf0
+ 80013da: 4393 bics r3, r2
+ 80013dc: 0019 movs r1, r3
+ 80013de: 4b04 ldr r3, [pc, #16] ; (80013f0 <LL_RCC_SetAHBPrescaler+0x24>)
+ 80013e0: 687a ldr r2, [r7, #4]
+ 80013e2: 430a orrs r2, r1
+ 80013e4: 605a str r2, [r3, #4]
+}
+ 80013e6: 46c0 nop ; (mov r8, r8)
+ 80013e8: 46bd mov sp, r7
+ 80013ea: b002 add sp, #8
+ 80013ec: bd80 pop {r7, pc}
+ 80013ee: 46c0 nop ; (mov r8, r8)
+ 80013f0: 40021000 .word 0x40021000
+
+080013f4 <LL_RCC_SetAPB1Prescaler>:
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
80013f4: b580 push {r7, lr}
80013f6: b082 sub sp, #8
80013f8: af00 add r7, sp, #0
80013fa: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
- 80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
+ 80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 <LL_RCC_SetAPB1Prescaler+0x24>)
80013fe: 685b ldr r3, [r3, #4]
- 8001400: 22f0 movs r2, #240 ; 0xf0
- 8001402: 4393 bics r3, r2
+ 8001400: 4a06 ldr r2, [pc, #24] ; (800141c <LL_RCC_SetAPB1Prescaler+0x28>)
+ 8001402: 4013 ands r3, r2
8001404: 0019 movs r1, r3
- 8001406: 4b04 ldr r3, [pc, #16] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
+ 8001406: 4b04 ldr r3, [pc, #16] ; (8001418 <LL_RCC_SetAPB1Prescaler+0x24>)
8001408: 687a ldr r2, [r7, #4]
800140a: 430a orrs r2, r1
800140c: 605a str r2, [r3, #4]
@@ -3496,1485 +3496,1456 @@ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
8001414: bd80 pop {r7, pc}
8001416: 46c0 nop ; (mov r8, r8)
8001418: 40021000 .word 0x40021000
+ 800141c: fffff8ff .word 0xfffff8ff
-0800141c <LL_RCC_SetAPB1Prescaler>:
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- 800141c: b580 push {r7, lr}
- 800141e: b082 sub sp, #8
- 8001420: af00 add r7, sp, #0
- 8001422: 6078 str r0, [r7, #4]
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
- 8001424: 4b06 ldr r3, [pc, #24] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
- 8001426: 685b ldr r3, [r3, #4]
- 8001428: 4a06 ldr r2, [pc, #24] ; (8001444 <LL_RCC_SetAPB1Prescaler+0x28>)
- 800142a: 4013 ands r3, r2
- 800142c: 0019 movs r1, r3
- 800142e: 4b04 ldr r3, [pc, #16] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
- 8001430: 687a ldr r2, [r7, #4]
- 8001432: 430a orrs r2, r1
- 8001434: 605a str r2, [r3, #4]
-}
- 8001436: 46c0 nop ; (mov r8, r8)
- 8001438: 46bd mov sp, r7
- 800143a: b002 add sp, #8
- 800143c: bd80 pop {r7, pc}
- 800143e: 46c0 nop ; (mov r8, r8)
- 8001440: 40021000 .word 0x40021000
- 8001444: fffff8ff .word 0xfffff8ff
-
-08001448 <LL_RCC_PLL_Enable>:
+08001420 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
- 8001448: b580 push {r7, lr}
- 800144a: af00 add r7, sp, #0
+ 8001420: b580 push {r7, lr}
+ 8001422: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
- 800144c: 4b04 ldr r3, [pc, #16] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
- 800144e: 681a ldr r2, [r3, #0]
- 8001450: 4b03 ldr r3, [pc, #12] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
- 8001452: 2180 movs r1, #128 ; 0x80
- 8001454: 0449 lsls r1, r1, #17
- 8001456: 430a orrs r2, r1
- 8001458: 601a str r2, [r3, #0]
+ 8001424: 4b04 ldr r3, [pc, #16] ; (8001438 <LL_RCC_PLL_Enable+0x18>)
+ 8001426: 681a ldr r2, [r3, #0]
+ 8001428: 4b03 ldr r3, [pc, #12] ; (8001438 <LL_RCC_PLL_Enable+0x18>)
+ 800142a: 2180 movs r1, #128 ; 0x80
+ 800142c: 0449 lsls r1, r1, #17
+ 800142e: 430a orrs r2, r1
+ 8001430: 601a str r2, [r3, #0]
}
- 800145a: 46c0 nop ; (mov r8, r8)
- 800145c: 46bd mov sp, r7
- 800145e: bd80 pop {r7, pc}
- 8001460: 40021000 .word 0x40021000
+ 8001432: 46c0 nop ; (mov r8, r8)
+ 8001434: 46bd mov sp, r7
+ 8001436: bd80 pop {r7, pc}
+ 8001438: 40021000 .word 0x40021000
-08001464 <LL_RCC_PLL_IsReady>:
+0800143c <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
- 8001464: b580 push {r7, lr}
- 8001466: af00 add r7, sp, #0
+ 800143c: b580 push {r7, lr}
+ 800143e: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
- 8001468: 4b07 ldr r3, [pc, #28] ; (8001488 <LL_RCC_PLL_IsReady+0x24>)
- 800146a: 681a ldr r2, [r3, #0]
- 800146c: 2380 movs r3, #128 ; 0x80
- 800146e: 049b lsls r3, r3, #18
- 8001470: 4013 ands r3, r2
- 8001472: 22fe movs r2, #254 ; 0xfe
- 8001474: 0612 lsls r2, r2, #24
- 8001476: 4694 mov ip, r2
- 8001478: 4463 add r3, ip
- 800147a: 425a negs r2, r3
- 800147c: 4153 adcs r3, r2
- 800147e: b2db uxtb r3, r3
+ 8001440: 4b07 ldr r3, [pc, #28] ; (8001460 <LL_RCC_PLL_IsReady+0x24>)
+ 8001442: 681a ldr r2, [r3, #0]
+ 8001444: 2380 movs r3, #128 ; 0x80
+ 8001446: 049b lsls r3, r3, #18
+ 8001448: 4013 ands r3, r2
+ 800144a: 22fe movs r2, #254 ; 0xfe
+ 800144c: 0612 lsls r2, r2, #24
+ 800144e: 4694 mov ip, r2
+ 8001450: 4463 add r3, ip
+ 8001452: 425a negs r2, r3
+ 8001454: 4153 adcs r3, r2
+ 8001456: b2db uxtb r3, r3
}
- 8001480: 0018 movs r0, r3
- 8001482: 46bd mov sp, r7
- 8001484: bd80 pop {r7, pc}
- 8001486: 46c0 nop ; (mov r8, r8)
- 8001488: 40021000 .word 0x40021000
+ 8001458: 0018 movs r0, r3
+ 800145a: 46bd mov sp, r7
+ 800145c: bd80 pop {r7, pc}
+ 800145e: 46c0 nop ; (mov r8, r8)
+ 8001460: 40021000 .word 0x40021000
-0800148c <LL_RCC_PLL_ConfigDomain_SYS>:
+08001464 <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLL_MUL_15
* @arg @ref LL_RCC_PLL_MUL_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
{
- 800148c: b580 push {r7, lr}
- 800148e: b082 sub sp, #8
- 8001490: af00 add r7, sp, #0
- 8001492: 6078 str r0, [r7, #4]
- 8001494: 6039 str r1, [r7, #0]
+ 8001464: b580 push {r7, lr}
+ 8001466: b082 sub sp, #8
+ 8001468: af00 add r7, sp, #0
+ 800146a: 6078 str r0, [r7, #4]
+ 800146c: 6039 str r1, [r7, #0]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
- 8001496: 4b0e ldr r3, [pc, #56] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 8001498: 685b ldr r3, [r3, #4]
- 800149a: 4a0e ldr r2, [pc, #56] ; (80014d4 <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
- 800149c: 4013 ands r3, r2
- 800149e: 0019 movs r1, r3
- 80014a0: 687a ldr r2, [r7, #4]
- 80014a2: 2380 movs r3, #128 ; 0x80
- 80014a4: 025b lsls r3, r3, #9
- 80014a6: 401a ands r2, r3
- 80014a8: 683b ldr r3, [r7, #0]
- 80014aa: 431a orrs r2, r3
- 80014ac: 4b08 ldr r3, [pc, #32] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 80014ae: 430a orrs r2, r1
- 80014b0: 605a str r2, [r3, #4]
+ 800146e: 4b0e ldr r3, [pc, #56] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 8001470: 685b ldr r3, [r3, #4]
+ 8001472: 4a0e ldr r2, [pc, #56] ; (80014ac <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
+ 8001474: 4013 ands r3, r2
+ 8001476: 0019 movs r1, r3
+ 8001478: 687a ldr r2, [r7, #4]
+ 800147a: 2380 movs r3, #128 ; 0x80
+ 800147c: 025b lsls r3, r3, #9
+ 800147e: 401a ands r2, r3
+ 8001480: 683b ldr r3, [r7, #0]
+ 8001482: 431a orrs r2, r3
+ 8001484: 4b08 ldr r3, [pc, #32] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 8001486: 430a orrs r2, r1
+ 8001488: 605a str r2, [r3, #4]
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
- 80014b2: 4b07 ldr r3, [pc, #28] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 80014b4: 6adb ldr r3, [r3, #44] ; 0x2c
- 80014b6: 220f movs r2, #15
- 80014b8: 4393 bics r3, r2
- 80014ba: 0019 movs r1, r3
- 80014bc: 687b ldr r3, [r7, #4]
- 80014be: 220f movs r2, #15
- 80014c0: 401a ands r2, r3
- 80014c2: 4b03 ldr r3, [pc, #12] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 80014c4: 430a orrs r2, r1
- 80014c6: 62da str r2, [r3, #44] ; 0x2c
+ 800148a: 4b07 ldr r3, [pc, #28] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 800148c: 6adb ldr r3, [r3, #44] ; 0x2c
+ 800148e: 220f movs r2, #15
+ 8001490: 4393 bics r3, r2
+ 8001492: 0019 movs r1, r3
+ 8001494: 687b ldr r3, [r7, #4]
+ 8001496: 220f movs r2, #15
+ 8001498: 401a ands r2, r3
+ 800149a: 4b03 ldr r3, [pc, #12] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 800149c: 430a orrs r2, r1
+ 800149e: 62da str r2, [r3, #44] ; 0x2c
}
- 80014c8: 46c0 nop ; (mov r8, r8)
- 80014ca: 46bd mov sp, r7
- 80014cc: b002 add sp, #8
- 80014ce: bd80 pop {r7, pc}
- 80014d0: 40021000 .word 0x40021000
- 80014d4: ffc2ffff .word 0xffc2ffff
-
-080014d8 <LL_InitTick>:
+ 80014a0: 46c0 nop ; (mov r8, r8)
+ 80014a2: 46bd mov sp, r7
+ 80014a4: b002 add sp, #8
+ 80014a6: bd80 pop {r7, pc}
+ 80014a8: 40021000 .word 0x40021000
+ 80014ac: ffc2ffff .word 0xffc2ffff
+
+080014b0 <LL_InitTick>:
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
- 80014d8: b580 push {r7, lr}
- 80014da: b082 sub sp, #8
- 80014dc: af00 add r7, sp, #0
- 80014de: 6078 str r0, [r7, #4]
- 80014e0: 6039 str r1, [r7, #0]
+ 80014b0: b580 push {r7, lr}
+ 80014b2: b082 sub sp, #8
+ 80014b4: af00 add r7, sp, #0
+ 80014b6: 6078 str r0, [r7, #4]
+ 80014b8: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- 80014e2: 6839 ldr r1, [r7, #0]
- 80014e4: 6878 ldr r0, [r7, #4]
- 80014e6: f000 fa13 bl 8001910 <__udivsi3>
- 80014ea: 0003 movs r3, r0
- 80014ec: 001a movs r2, r3
- 80014ee: 4b06 ldr r3, [pc, #24] ; (8001508 <LL_InitTick+0x30>)
- 80014f0: 3a01 subs r2, #1
- 80014f2: 605a str r2, [r3, #4]
+ 80014ba: 6839 ldr r1, [r7, #0]
+ 80014bc: 6878 ldr r0, [r7, #4]
+ 80014be: f000 fa13 bl 80018e8 <__udivsi3>
+ 80014c2: 0003 movs r3, r0
+ 80014c4: 001a movs r2, r3
+ 80014c6: 4b06 ldr r3, [pc, #24] ; (80014e0 <LL_InitTick+0x30>)
+ 80014c8: 3a01 subs r2, #1
+ 80014ca: 605a str r2, [r3, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 80014f4: 4b04 ldr r3, [pc, #16] ; (8001508 <LL_InitTick+0x30>)
- 80014f6: 2200 movs r2, #0
- 80014f8: 609a str r2, [r3, #8]
+ 80014cc: 4b04 ldr r3, [pc, #16] ; (80014e0 <LL_InitTick+0x30>)
+ 80014ce: 2200 movs r2, #0
+ 80014d0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 80014fa: 4b03 ldr r3, [pc, #12] ; (8001508 <LL_InitTick+0x30>)
- 80014fc: 2205 movs r2, #5
- 80014fe: 601a str r2, [r3, #0]
+ 80014d2: 4b03 ldr r3, [pc, #12] ; (80014e0 <LL_InitTick+0x30>)
+ 80014d4: 2205 movs r2, #5
+ 80014d6: 601a str r2, [r3, #0]
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
- 8001500: 46c0 nop ; (mov r8, r8)
- 8001502: 46bd mov sp, r7
- 8001504: b002 add sp, #8
- 8001506: bd80 pop {r7, pc}
- 8001508: e000e010 .word 0xe000e010
+ 80014d8: 46c0 nop ; (mov r8, r8)
+ 80014da: 46bd mov sp, r7
+ 80014dc: b002 add sp, #8
+ 80014de: bd80 pop {r7, pc}
+ 80014e0: e000e010 .word 0xe000e010
-0800150c <LL_FLASH_SetLatency>:
+080014e4 <LL_FLASH_SetLatency>:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
- 800150c: b580 push {r7, lr}
- 800150e: b082 sub sp, #8
- 8001510: af00 add r7, sp, #0
- 8001512: 6078 str r0, [r7, #4]
+ 80014e4: b580 push {r7, lr}
+ 80014e6: b082 sub sp, #8
+ 80014e8: af00 add r7, sp, #0
+ 80014ea: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- 8001514: 4b06 ldr r3, [pc, #24] ; (8001530 <LL_FLASH_SetLatency+0x24>)
- 8001516: 681b ldr r3, [r3, #0]
- 8001518: 2201 movs r2, #1
- 800151a: 4393 bics r3, r2
- 800151c: 0019 movs r1, r3
- 800151e: 4b04 ldr r3, [pc, #16] ; (8001530 <LL_FLASH_SetLatency+0x24>)
- 8001520: 687a ldr r2, [r7, #4]
- 8001522: 430a orrs r2, r1
- 8001524: 601a str r2, [r3, #0]
+ 80014ec: 4b06 ldr r3, [pc, #24] ; (8001508 <LL_FLASH_SetLatency+0x24>)
+ 80014ee: 681b ldr r3, [r3, #0]
+ 80014f0: 2201 movs r2, #1
+ 80014f2: 4393 bics r3, r2
+ 80014f4: 0019 movs r1, r3
+ 80014f6: 4b04 ldr r3, [pc, #16] ; (8001508 <LL_FLASH_SetLatency+0x24>)
+ 80014f8: 687a ldr r2, [r7, #4]
+ 80014fa: 430a orrs r2, r1
+ 80014fc: 601a str r2, [r3, #0]
}
- 8001526: 46c0 nop ; (mov r8, r8)
- 8001528: 46bd mov sp, r7
- 800152a: b002 add sp, #8
- 800152c: bd80 pop {r7, pc}
- 800152e: 46c0 nop ; (mov r8, r8)
- 8001530: 40022000 .word 0x40022000
-
-08001534 <LL_FLASH_GetLatency>:
+ 80014fe: 46c0 nop ; (mov r8, r8)
+ 8001500: 46bd mov sp, r7
+ 8001502: b002 add sp, #8
+ 8001504: bd80 pop {r7, pc}
+ 8001506: 46c0 nop ; (mov r8, r8)
+ 8001508: 40022000 .word 0x40022000
+
+0800150c <LL_FLASH_GetLatency>:
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
- 8001534: b580 push {r7, lr}
- 8001536: af00 add r7, sp, #0
+ 800150c: b580 push {r7, lr}
+ 800150e: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
- 8001538: 4b03 ldr r3, [pc, #12] ; (8001548 <LL_FLASH_GetLatency+0x14>)
- 800153a: 681b ldr r3, [r3, #0]
- 800153c: 2201 movs r2, #1
- 800153e: 4013 ands r3, r2
+ 8001510: 4b03 ldr r3, [pc, #12] ; (8001520 <LL_FLASH_GetLatency+0x14>)
+ 8001512: 681b ldr r3, [r3, #0]
+ 8001514: 2201 movs r2, #1
+ 8001516: 4013 ands r3, r2
}
- 8001540: 0018 movs r0, r3
- 8001542: 46bd mov sp, r7
- 8001544: bd80 pop {r7, pc}
- 8001546: 46c0 nop ; (mov r8, r8)
- 8001548: 40022000 .word 0x40022000
+ 8001518: 0018 movs r0, r3
+ 800151a: 46bd mov sp, r7
+ 800151c: bd80 pop {r7, pc}
+ 800151e: 46c0 nop ; (mov r8, r8)
+ 8001520: 40022000 .word 0x40022000
-0800154c <LL_Init1msTick>:
+08001524 <LL_Init1msTick>:
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
- 800154c: b580 push {r7, lr}
- 800154e: b082 sub sp, #8
- 8001550: af00 add r7, sp, #0
- 8001552: 6078 str r0, [r7, #4]
+ 8001524: b580 push {r7, lr}
+ 8001526: b082 sub sp, #8
+ 8001528: af00 add r7, sp, #0
+ 800152a: 6078 str r0, [r7, #4]
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
- 8001554: 23fa movs r3, #250 ; 0xfa
- 8001556: 009a lsls r2, r3, #2
- 8001558: 687b ldr r3, [r7, #4]
- 800155a: 0011 movs r1, r2
- 800155c: 0018 movs r0, r3
- 800155e: f7ff ffbb bl 80014d8 <LL_InitTick>
+ 800152c: 23fa movs r3, #250 ; 0xfa
+ 800152e: 009a lsls r2, r3, #2
+ 8001530: 687b ldr r3, [r7, #4]
+ 8001532: 0011 movs r1, r2
+ 8001534: 0018 movs r0, r3
+ 8001536: f7ff ffbb bl 80014b0 <LL_InitTick>
}
- 8001562: 46c0 nop ; (mov r8, r8)
- 8001564: 46bd mov sp, r7
- 8001566: b002 add sp, #8
- 8001568: bd80 pop {r7, pc}
+ 800153a: 46c0 nop ; (mov r8, r8)
+ 800153c: 46bd mov sp, r7
+ 800153e: b002 add sp, #8
+ 8001540: bd80 pop {r7, pc}
-0800156a <LL_mDelay>:
+08001542 <LL_mDelay>:
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
- 800156a: b580 push {r7, lr}
- 800156c: b084 sub sp, #16
- 800156e: af00 add r7, sp, #0
- 8001570: 6078 str r0, [r7, #4]
+ 8001542: b580 push {r7, lr}
+ 8001544: b084 sub sp, #16
+ 8001546: af00 add r7, sp, #0
+ 8001548: 6078 str r0, [r7, #4]
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- 8001572: 4b0e ldr r3, [pc, #56] ; (80015ac <LL_mDelay+0x42>)
- 8001574: 681b ldr r3, [r3, #0]
- 8001576: 60fb str r3, [r7, #12]
+ 800154a: 4b0e ldr r3, [pc, #56] ; (8001584 <LL_mDelay+0x42>)
+ 800154c: 681b ldr r3, [r3, #0]
+ 800154e: 60fb str r3, [r7, #12]
/* Add this code to indicate that local variable is not used */
((void)tmp);
- 8001578: 68fb ldr r3, [r7, #12]
+ 8001550: 68fb ldr r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
- 800157a: 687b ldr r3, [r7, #4]
- 800157c: 3301 adds r3, #1
- 800157e: d00c beq.n 800159a <LL_mDelay+0x30>
+ 8001552: 687b ldr r3, [r7, #4]
+ 8001554: 3301 adds r3, #1
+ 8001556: d00c beq.n 8001572 <LL_mDelay+0x30>
{
Delay++;
- 8001580: 687b ldr r3, [r7, #4]
- 8001582: 3301 adds r3, #1
- 8001584: 607b str r3, [r7, #4]
+ 8001558: 687b ldr r3, [r7, #4]
+ 800155a: 3301 adds r3, #1
+ 800155c: 607b str r3, [r7, #4]
}
while (Delay)
- 8001586: e008 b.n 800159a <LL_mDelay+0x30>
+ 800155e: e008 b.n 8001572 <LL_mDelay+0x30>
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- 8001588: 4b08 ldr r3, [pc, #32] ; (80015ac <LL_mDelay+0x42>)
- 800158a: 681a ldr r2, [r3, #0]
- 800158c: 2380 movs r3, #128 ; 0x80
- 800158e: 025b lsls r3, r3, #9
- 8001590: 4013 ands r3, r2
- 8001592: d002 beq.n 800159a <LL_mDelay+0x30>
+ 8001560: 4b08 ldr r3, [pc, #32] ; (8001584 <LL_mDelay+0x42>)
+ 8001562: 681a ldr r2, [r3, #0]
+ 8001564: 2380 movs r3, #128 ; 0x80
+ 8001566: 025b lsls r3, r3, #9
+ 8001568: 4013 ands r3, r2
+ 800156a: d002 beq.n 8001572 <LL_mDelay+0x30>
{
Delay--;
- 8001594: 687b ldr r3, [r7, #4]
- 8001596: 3b01 subs r3, #1
- 8001598: 607b str r3, [r7, #4]
+ 800156c: 687b ldr r3, [r7, #4]
+ 800156e: 3b01 subs r3, #1
+ 8001570: 607b str r3, [r7, #4]
while (Delay)
- 800159a: 687b ldr r3, [r7, #4]
- 800159c: 2b00 cmp r3, #0
- 800159e: d1f3 bne.n 8001588 <LL_mDelay+0x1e>
+ 8001572: 687b ldr r3, [r7, #4]
+ 8001574: 2b00 cmp r3, #0
+ 8001576: d1f3 bne.n 8001560 <LL_mDelay+0x1e>
}
}
}
- 80015a0: 46c0 nop ; (mov r8, r8)
- 80015a2: 46c0 nop ; (mov r8, r8)
- 80015a4: 46bd mov sp, r7
- 80015a6: b004 add sp, #16
- 80015a8: bd80 pop {r7, pc}
- 80015aa: 46c0 nop ; (mov r8, r8)
- 80015ac: e000e010 .word 0xe000e010
-
-080015b0 <LL_SetSystemCoreClock>:
+ 8001578: 46c0 nop ; (mov r8, r8)
+ 800157a: 46c0 nop ; (mov r8, r8)
+ 800157c: 46bd mov sp, r7
+ 800157e: b004 add sp, #16
+ 8001580: bd80 pop {r7, pc}
+ 8001582: 46c0 nop ; (mov r8, r8)
+ 8001584: e000e010 .word 0xe000e010
+
+08001588 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
- 80015b0: b580 push {r7, lr}
- 80015b2: b082 sub sp, #8
- 80015b4: af00 add r7, sp, #0
- 80015b6: 6078 str r0, [r7, #4]
+ 8001588: b580 push {r7, lr}
+ 800158a: b082 sub sp, #8
+ 800158c: af00 add r7, sp, #0
+ 800158e: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
- 80015b8: 4b03 ldr r3, [pc, #12] ; (80015c8 <LL_SetSystemCoreClock+0x18>)
- 80015ba: 687a ldr r2, [r7, #4]
- 80015bc: 601a str r2, [r3, #0]
+ 8001590: 4b03 ldr r3, [pc, #12] ; (80015a0 <LL_SetSystemCoreClock+0x18>)
+ 8001592: 687a ldr r2, [r7, #4]
+ 8001594: 601a str r2, [r3, #0]
}
- 80015be: 46c0 nop ; (mov r8, r8)
- 80015c0: 46bd mov sp, r7
- 80015c2: b002 add sp, #8
- 80015c4: bd80 pop {r7, pc}
- 80015c6: 46c0 nop ; (mov r8, r8)
- 80015c8: 20000000 .word 0x20000000
-
-080015cc <LL_PLL_ConfigSystemClock_HSI>:
+ 8001596: 46c0 nop ; (mov r8, r8)
+ 8001598: 46bd mov sp, r7
+ 800159a: b002 add sp, #8
+ 800159c: bd80 pop {r7, pc}
+ 800159e: 46c0 nop ; (mov r8, r8)
+ 80015a0: 20000000 .word 0x20000000
+
+080015a4 <LL_PLL_ConfigSystemClock_HSI>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 80015cc: b590 push {r4, r7, lr}
- 80015ce: b085 sub sp, #20
- 80015d0: af00 add r7, sp, #0
- 80015d2: 6078 str r0, [r7, #4]
- 80015d4: 6039 str r1, [r7, #0]
+ 80015a4: b590 push {r4, r7, lr}
+ 80015a6: b085 sub sp, #20
+ 80015a8: af00 add r7, sp, #0
+ 80015aa: 6078 str r0, [r7, #4]
+ 80015ac: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 80015d6: 230f movs r3, #15
- 80015d8: 18fb adds r3, r7, r3
- 80015da: 2201 movs r2, #1
- 80015dc: 701a strb r2, [r3, #0]
+ 80015ae: 230f movs r3, #15
+ 80015b0: 18fb adds r3, r7, r3
+ 80015b2: 2201 movs r2, #1
+ 80015b4: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 80015de: 2300 movs r3, #0
- 80015e0: 60bb str r3, [r7, #8]
+ 80015b6: 2300 movs r3, #0
+ 80015b8: 60bb str r3, [r7, #8]
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 80015e2: f000 f8d4 bl 800178e <UTILS_PLL_IsBusy>
- 80015e6: 0003 movs r3, r0
- 80015e8: 2b01 cmp r3, #1
- 80015ea: d128 bne.n 800163e <LL_PLL_ConfigSystemClock_HSI+0x72>
+ 80015ba: f000 f8d4 bl 8001766 <UTILS_PLL_IsBusy>
+ 80015be: 0003 movs r3, r0
+ 80015c0: 2b01 cmp r3, #1
+ 80015c2: d128 bne.n 8001616 <LL_PLL_ConfigSystemClock_HSI+0x72>
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
- 80015ec: 687b ldr r3, [r7, #4]
- 80015ee: 2201 movs r2, #1
- 80015f0: 605a str r2, [r3, #4]
+ 80015c4: 687b ldr r3, [r7, #4]
+ 80015c6: 2201 movs r2, #1
+ 80015c8: 605a str r2, [r3, #4]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
- 80015f2: 687b ldr r3, [r7, #4]
- 80015f4: 4a17 ldr r2, [pc, #92] ; (8001654 <LL_PLL_ConfigSystemClock_HSI+0x88>)
- 80015f6: 0019 movs r1, r3
- 80015f8: 0010 movs r0, r2
- 80015fa: f000 f8ab bl 8001754 <UTILS_GetPLLOutputFrequency>
- 80015fe: 0003 movs r3, r0
- 8001600: 60bb str r3, [r7, #8]
+ 80015ca: 687b ldr r3, [r7, #4]
+ 80015cc: 4a17 ldr r2, [pc, #92] ; (800162c <LL_PLL_ConfigSystemClock_HSI+0x88>)
+ 80015ce: 0019 movs r1, r3
+ 80015d0: 0010 movs r0, r2
+ 80015d2: f000 f8ab bl 800172c <UTILS_GetPLLOutputFrequency>
+ 80015d6: 0003 movs r3, r0
+ 80015d8: 60bb str r3, [r7, #8]
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
- 8001602: f7ff fec7 bl 8001394 <LL_RCC_HSI_IsReady>
- 8001606: 0003 movs r3, r0
- 8001608: 2b01 cmp r3, #1
- 800160a: d007 beq.n 800161c <LL_PLL_ConfigSystemClock_HSI+0x50>
+ 80015da: f7ff fec7 bl 800136c <LL_RCC_HSI_IsReady>
+ 80015de: 0003 movs r3, r0
+ 80015e0: 2b01 cmp r3, #1
+ 80015e2: d007 beq.n 80015f4 <LL_PLL_ConfigSystemClock_HSI+0x50>
{
LL_RCC_HSI_Enable();
- 800160c: f7ff feb4 bl 8001378 <LL_RCC_HSI_Enable>
+ 80015e4: f7ff feb4 bl 8001350 <LL_RCC_HSI_Enable>
while (LL_RCC_HSI_IsReady() != 1U)
- 8001610: 46c0 nop ; (mov r8, r8)
- 8001612: f7ff febf bl 8001394 <LL_RCC_HSI_IsReady>
- 8001616: 0003 movs r3, r0
- 8001618: 2b01 cmp r3, #1
- 800161a: d1fa bne.n 8001612 <LL_PLL_ConfigSystemClock_HSI+0x46>
+ 80015e8: 46c0 nop ; (mov r8, r8)
+ 80015ea: f7ff febf bl 800136c <LL_RCC_HSI_IsReady>
+ 80015ee: 0003 movs r3, r0
+ 80015f0: 2b01 cmp r3, #1
+ 80015f2: d1fa bne.n 80015ea <LL_PLL_ConfigSystemClock_HSI+0x46>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
- 800161c: 687b ldr r3, [r7, #4]
- 800161e: 681b ldr r3, [r3, #0]
- 8001620: 0019 movs r1, r3
- 8001622: 2000 movs r0, #0
- 8001624: f7ff ff32 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
+ 80015f4: 687b ldr r3, [r7, #4]
+ 80015f6: 681b ldr r3, [r3, #0]
+ 80015f8: 0019 movs r1, r3
+ 80015fa: 2000 movs r0, #0
+ 80015fc: f7ff ff32 bl 8001464 <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 8001628: 230f movs r3, #15
- 800162a: 18fc adds r4, r7, r3
- 800162c: 683a ldr r2, [r7, #0]
- 800162e: 68bb ldr r3, [r7, #8]
- 8001630: 0011 movs r1, r2
- 8001632: 0018 movs r0, r3
- 8001634: f000 f8be bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
- 8001638: 0003 movs r3, r0
- 800163a: 7023 strb r3, [r4, #0]
- 800163c: e003 b.n 8001646 <LL_PLL_ConfigSystemClock_HSI+0x7a>
+ 8001600: 230f movs r3, #15
+ 8001602: 18fc adds r4, r7, r3
+ 8001604: 683a ldr r2, [r7, #0]
+ 8001606: 68bb ldr r3, [r7, #8]
+ 8001608: 0011 movs r1, r2
+ 800160a: 0018 movs r0, r3
+ 800160c: f000 f8be bl 800178c <UTILS_EnablePLLAndSwitchSystem>
+ 8001610: 0003 movs r3, r0
+ 8001612: 7023 strb r3, [r4, #0]
+ 8001614: e003 b.n 800161e <LL_PLL_ConfigSystemClock_HSI+0x7a>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 800163e: 230f movs r3, #15
- 8001640: 18fb adds r3, r7, r3
- 8001642: 2200 movs r2, #0
- 8001644: 701a strb r2, [r3, #0]
+ 8001616: 230f movs r3, #15
+ 8001618: 18fb adds r3, r7, r3
+ 800161a: 2200 movs r2, #0
+ 800161c: 701a strb r2, [r3, #0]
}
return status;
- 8001646: 230f movs r3, #15
- 8001648: 18fb adds r3, r7, r3
- 800164a: 781b ldrb r3, [r3, #0]
+ 800161e: 230f movs r3, #15
+ 8001620: 18fb adds r3, r7, r3
+ 8001622: 781b ldrb r3, [r3, #0]
}
- 800164c: 0018 movs r0, r3
- 800164e: 46bd mov sp, r7
- 8001650: b005 add sp, #20
- 8001652: bd90 pop {r4, r7, pc}
- 8001654: 007a1200 .word 0x007a1200
+ 8001624: 0018 movs r0, r3
+ 8001626: 46bd mov sp, r7
+ 8001628: b005 add sp, #20
+ 800162a: bd90 pop {r4, r7, pc}
+ 800162c: 007a1200 .word 0x007a1200
-08001658 <LL_PLL_ConfigSystemClock_HSE>:
+08001630 <LL_PLL_ConfigSystemClock_HSE>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 8001658: b590 push {r4, r7, lr}
- 800165a: b087 sub sp, #28
- 800165c: af00 add r7, sp, #0
- 800165e: 60f8 str r0, [r7, #12]
- 8001660: 60b9 str r1, [r7, #8]
- 8001662: 607a str r2, [r7, #4]
- 8001664: 603b str r3, [r7, #0]
+ 8001630: b590 push {r4, r7, lr}
+ 8001632: b087 sub sp, #28
+ 8001634: af00 add r7, sp, #0
+ 8001636: 60f8 str r0, [r7, #12]
+ 8001638: 60b9 str r1, [r7, #8]
+ 800163a: 607a str r2, [r7, #4]
+ 800163c: 603b str r3, [r7, #0]
ErrorStatus status = SUCCESS;
- 8001666: 2317 movs r3, #23
- 8001668: 18fb adds r3, r7, r3
- 800166a: 2201 movs r2, #1
- 800166c: 701a strb r2, [r3, #0]
+ 800163e: 2317 movs r3, #23
+ 8001640: 18fb adds r3, r7, r3
+ 8001642: 2201 movs r2, #1
+ 8001644: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 800166e: 2300 movs r3, #0
- 8001670: 613b str r3, [r7, #16]
+ 8001646: 2300 movs r3, #0
+ 8001648: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 8001672: f000 f88c bl 800178e <UTILS_PLL_IsBusy>
- 8001676: 0003 movs r3, r0
- 8001678: 2b01 cmp r3, #1
- 800167a: d132 bne.n 80016e2 <LL_PLL_ConfigSystemClock_HSE+0x8a>
+ 800164a: f000 f88c bl 8001766 <UTILS_PLL_IsBusy>
+ 800164e: 0003 movs r3, r0
+ 8001650: 2b01 cmp r3, #1
+ 8001652: d132 bne.n 80016ba <LL_PLL_ConfigSystemClock_HSE+0x8a>
#else
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
- 800167c: 687a ldr r2, [r7, #4]
- 800167e: 68fb ldr r3, [r7, #12]
- 8001680: 0011 movs r1, r2
- 8001682: 0018 movs r0, r3
- 8001684: f000 f866 bl 8001754 <UTILS_GetPLLOutputFrequency>
- 8001688: 0003 movs r3, r0
- 800168a: 613b str r3, [r7, #16]
+ 8001654: 687a ldr r2, [r7, #4]
+ 8001656: 68fb ldr r3, [r7, #12]
+ 8001658: 0011 movs r1, r2
+ 800165a: 0018 movs r0, r3
+ 800165c: f000 f866 bl 800172c <UTILS_GetPLLOutputFrequency>
+ 8001660: 0003 movs r3, r0
+ 8001662: 613b str r3, [r7, #16]
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
- 800168c: f7ff fe60 bl 8001350 <LL_RCC_HSE_IsReady>
- 8001690: 0003 movs r3, r0
- 8001692: 2b01 cmp r3, #1
- 8001694: d00f beq.n 80016b6 <LL_PLL_ConfigSystemClock_HSE+0x5e>
+ 8001664: f7ff fe60 bl 8001328 <LL_RCC_HSE_IsReady>
+ 8001668: 0003 movs r3, r0
+ 800166a: 2b01 cmp r3, #1
+ 800166c: d00f beq.n 800168e <LL_PLL_ConfigSystemClock_HSE+0x5e>
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- 8001696: 68bb ldr r3, [r7, #8]
- 8001698: 2b01 cmp r3, #1
- 800169a: d102 bne.n 80016a2 <LL_PLL_ConfigSystemClock_HSE+0x4a>
+ 800166e: 68bb ldr r3, [r7, #8]
+ 8001670: 2b01 cmp r3, #1
+ 8001672: d102 bne.n 800167a <LL_PLL_ConfigSystemClock_HSE+0x4a>
{
LL_RCC_HSE_EnableBypass();
- 800169c: f7ff fe2c bl 80012f8 <LL_RCC_HSE_EnableBypass>
- 80016a0: e001 b.n 80016a6 <LL_PLL_ConfigSystemClock_HSE+0x4e>
+ 8001674: f7ff fe2c bl 80012d0 <LL_RCC_HSE_EnableBypass>
+ 8001678: e001 b.n 800167e <LL_PLL_ConfigSystemClock_HSE+0x4e>
}
else
{
LL_RCC_HSE_DisableBypass();
- 80016a2: f7ff fe37 bl 8001314 <LL_RCC_HSE_DisableBypass>
+ 800167a: f7ff fe37 bl 80012ec <LL_RCC_HSE_DisableBypass>
}
/* Enable HSE */
LL_RCC_HSE_Enable();
- 80016a6: f7ff fe45 bl 8001334 <LL_RCC_HSE_Enable>
+ 800167e: f7ff fe45 bl 800130c <LL_RCC_HSE_Enable>
while (LL_RCC_HSE_IsReady() != 1U)
- 80016aa: 46c0 nop ; (mov r8, r8)
- 80016ac: f7ff fe50 bl 8001350 <LL_RCC_HSE_IsReady>
- 80016b0: 0003 movs r3, r0
- 80016b2: 2b01 cmp r3, #1
- 80016b4: d1fa bne.n 80016ac <LL_PLL_ConfigSystemClock_HSE+0x54>
+ 8001682: 46c0 nop ; (mov r8, r8)
+ 8001684: f7ff fe50 bl 8001328 <LL_RCC_HSE_IsReady>
+ 8001688: 0003 movs r3, r0
+ 800168a: 2b01 cmp r3, #1
+ 800168c: d1fa bne.n 8001684 <LL_PLL_ConfigSystemClock_HSE+0x54>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
- 80016b6: 687b ldr r3, [r7, #4]
- 80016b8: 685b ldr r3, [r3, #4]
- 80016ba: 2280 movs r2, #128 ; 0x80
- 80016bc: 0252 lsls r2, r2, #9
- 80016be: 431a orrs r2, r3
- 80016c0: 687b ldr r3, [r7, #4]
- 80016c2: 681b ldr r3, [r3, #0]
- 80016c4: 0019 movs r1, r3
- 80016c6: 0010 movs r0, r2
- 80016c8: f7ff fee0 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
+ 800168e: 687b ldr r3, [r7, #4]
+ 8001690: 685b ldr r3, [r3, #4]
+ 8001692: 2280 movs r2, #128 ; 0x80
+ 8001694: 0252 lsls r2, r2, #9
+ 8001696: 431a orrs r2, r3
+ 8001698: 687b ldr r3, [r7, #4]
+ 800169a: 681b ldr r3, [r3, #0]
+ 800169c: 0019 movs r1, r3
+ 800169e: 0010 movs r0, r2
+ 80016a0: f7ff fee0 bl 8001464 <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 80016cc: 2317 movs r3, #23
- 80016ce: 18fc adds r4, r7, r3
- 80016d0: 683a ldr r2, [r7, #0]
- 80016d2: 693b ldr r3, [r7, #16]
- 80016d4: 0011 movs r1, r2
- 80016d6: 0018 movs r0, r3
- 80016d8: f000 f86c bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
- 80016dc: 0003 movs r3, r0
- 80016de: 7023 strb r3, [r4, #0]
- 80016e0: e003 b.n 80016ea <LL_PLL_ConfigSystemClock_HSE+0x92>
+ 80016a4: 2317 movs r3, #23
+ 80016a6: 18fc adds r4, r7, r3
+ 80016a8: 683a ldr r2, [r7, #0]
+ 80016aa: 693b ldr r3, [r7, #16]
+ 80016ac: 0011 movs r1, r2
+ 80016ae: 0018 movs r0, r3
+ 80016b0: f000 f86c bl 800178c <UTILS_EnablePLLAndSwitchSystem>
+ 80016b4: 0003 movs r3, r0
+ 80016b6: 7023 strb r3, [r4, #0]
+ 80016b8: e003 b.n 80016c2 <LL_PLL_ConfigSystemClock_HSE+0x92>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 80016e2: 2317 movs r3, #23
- 80016e4: 18fb adds r3, r7, r3
- 80016e6: 2200 movs r2, #0
- 80016e8: 701a strb r2, [r3, #0]
+ 80016ba: 2317 movs r3, #23
+ 80016bc: 18fb adds r3, r7, r3
+ 80016be: 2200 movs r2, #0
+ 80016c0: 701a strb r2, [r3, #0]
}
return status;
- 80016ea: 2317 movs r3, #23
- 80016ec: 18fb adds r3, r7, r3
- 80016ee: 781b ldrb r3, [r3, #0]
+ 80016c2: 2317 movs r3, #23
+ 80016c4: 18fb adds r3, r7, r3
+ 80016c6: 781b ldrb r3, [r3, #0]
}
- 80016f0: 0018 movs r0, r3
- 80016f2: 46bd mov sp, r7
- 80016f4: b007 add sp, #28
- 80016f6: bd90 pop {r4, r7, pc}
+ 80016c8: 0018 movs r0, r3
+ 80016ca: 46bd mov sp, r7
+ 80016cc: b007 add sp, #28
+ 80016ce: bd90 pop {r4, r7, pc}
-080016f8 <UTILS_SetFlashLatency>:
+080016d0 <UTILS_SetFlashLatency>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
- 80016f8: b580 push {r7, lr}
- 80016fa: b084 sub sp, #16
- 80016fc: af00 add r7, sp, #0
- 80016fe: 6078 str r0, [r7, #4]
+ 80016d0: b580 push {r7, lr}
+ 80016d2: b084 sub sp, #16
+ 80016d4: af00 add r7, sp, #0
+ 80016d6: 6078 str r0, [r7, #4]
ErrorStatus status = SUCCESS;
- 8001700: 210f movs r1, #15
- 8001702: 187b adds r3, r7, r1
- 8001704: 2201 movs r2, #1
- 8001706: 701a strb r2, [r3, #0]
+ 80016d8: 210f movs r1, #15
+ 80016da: 187b adds r3, r7, r1
+ 80016dc: 2201 movs r2, #1
+ 80016de: 701a strb r2, [r3, #0]
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
- 8001708: 2300 movs r3, #0
- 800170a: 60bb str r3, [r7, #8]
+ 80016e0: 2300 movs r3, #0
+ 80016e2: 60bb str r3, [r7, #8]
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
- 800170c: 687b ldr r3, [r7, #4]
- 800170e: 2b00 cmp r3, #0
- 8001710: d103 bne.n 800171a <UTILS_SetFlashLatency+0x22>
+ 80016e4: 687b ldr r3, [r7, #4]
+ 80016e6: 2b00 cmp r3, #0
+ 80016e8: d103 bne.n 80016f2 <UTILS_SetFlashLatency+0x22>
{
status = ERROR;
- 8001712: 187b adds r3, r7, r1
- 8001714: 2200 movs r2, #0
- 8001716: 701a strb r2, [r3, #0]
- 8001718: e013 b.n 8001742 <UTILS_SetFlashLatency+0x4a>
+ 80016ea: 187b adds r3, r7, r1
+ 80016ec: 2200 movs r2, #0
+ 80016ee: 701a strb r2, [r3, #0]
+ 80016f0: e013 b.n 800171a <UTILS_SetFlashLatency+0x4a>
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
- 800171a: 687b ldr r3, [r7, #4]
- 800171c: 4a0c ldr r2, [pc, #48] ; (8001750 <UTILS_SetFlashLatency+0x58>)
- 800171e: 4293 cmp r3, r2
- 8001720: d901 bls.n 8001726 <UTILS_SetFlashLatency+0x2e>
+ 80016f2: 687b ldr r3, [r7, #4]
+ 80016f4: 4a0c ldr r2, [pc, #48] ; (8001728 <UTILS_SetFlashLatency+0x58>)
+ 80016f6: 4293 cmp r3, r2
+ 80016f8: d901 bls.n 80016fe <UTILS_SetFlashLatency+0x2e>
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
- 8001722: 2301 movs r3, #1
- 8001724: 60bb str r3, [r7, #8]
+ 80016fa: 2301 movs r3, #1
+ 80016fc: 60bb str r3, [r7, #8]
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
LL_FLASH_SetLatency(latency);
- 8001726: 68bb ldr r3, [r7, #8]
- 8001728: 0018 movs r0, r3
- 800172a: f7ff feef bl 800150c <LL_FLASH_SetLatency>
+ 80016fe: 68bb ldr r3, [r7, #8]
+ 8001700: 0018 movs r0, r3
+ 8001702: f7ff feef bl 80014e4 <LL_FLASH_SetLatency>
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
- 800172e: f7ff ff01 bl 8001534 <LL_FLASH_GetLatency>
- 8001732: 0002 movs r2, r0
- 8001734: 68bb ldr r3, [r7, #8]
- 8001736: 4293 cmp r3, r2
- 8001738: d003 beq.n 8001742 <UTILS_SetFlashLatency+0x4a>
+ 8001706: f7ff ff01 bl 800150c <LL_FLASH_GetLatency>
+ 800170a: 0002 movs r2, r0
+ 800170c: 68bb ldr r3, [r7, #8]
+ 800170e: 4293 cmp r3, r2
+ 8001710: d003 beq.n 800171a <UTILS_SetFlashLatency+0x4a>
{
status = ERROR;
- 800173a: 230f movs r3, #15
- 800173c: 18fb adds r3, r7, r3
- 800173e: 2200 movs r2, #0
- 8001740: 701a strb r2, [r3, #0]
+ 8001712: 230f movs r3, #15
+ 8001714: 18fb adds r3, r7, r3
+ 8001716: 2200 movs r2, #0
+ 8001718: 701a strb r2, [r3, #0]
}
}
return status;
- 8001742: 230f movs r3, #15
- 8001744: 18fb adds r3, r7, r3
- 8001746: 781b ldrb r3, [r3, #0]
+ 800171a: 230f movs r3, #15
+ 800171c: 18fb adds r3, r7, r3
+ 800171e: 781b ldrb r3, [r3, #0]
}
- 8001748: 0018 movs r0, r3
- 800174a: 46bd mov sp, r7
- 800174c: b004 add sp, #16
- 800174e: bd80 pop {r7, pc}
- 8001750: 016e3600 .word 0x016e3600
+ 8001720: 0018 movs r0, r3
+ 8001722: 46bd mov sp, r7
+ 8001724: b004 add sp, #16
+ 8001726: bd80 pop {r7, pc}
+ 8001728: 016e3600 .word 0x016e3600
-08001754 <UTILS_GetPLLOutputFrequency>:
+0800172c <UTILS_GetPLLOutputFrequency>:
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
- 8001754: b580 push {r7, lr}
- 8001756: b084 sub sp, #16
- 8001758: af00 add r7, sp, #0
- 800175a: 6078 str r0, [r7, #4]
- 800175c: 6039 str r1, [r7, #0]
+ 800172c: b580 push {r7, lr}
+ 800172e: b084 sub sp, #16
+ 8001730: af00 add r7, sp, #0
+ 8001732: 6078 str r0, [r7, #4]
+ 8001734: 6039 str r1, [r7, #0]
uint32_t pllfreq = 0U;
- 800175e: 2300 movs r3, #0
- 8001760: 60fb str r3, [r7, #12]
+ 8001736: 2300 movs r3, #0
+ 8001738: 60fb str r3, [r7, #12]
/* The application software must set correctly the PLL multiplication factor to
be in the range 16-48MHz */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
- 8001762: 683b ldr r3, [r7, #0]
- 8001764: 685b ldr r3, [r3, #4]
- 8001766: 3301 adds r3, #1
- 8001768: 0019 movs r1, r3
- 800176a: 6878 ldr r0, [r7, #4]
- 800176c: f000 f8d0 bl 8001910 <__udivsi3>
- 8001770: 0003 movs r3, r0
- 8001772: 0019 movs r1, r3
- 8001774: 683b ldr r3, [r7, #0]
- 8001776: 681b ldr r3, [r3, #0]
- 8001778: 0c9b lsrs r3, r3, #18
- 800177a: 220f movs r2, #15
- 800177c: 4013 ands r3, r2
- 800177e: 3302 adds r3, #2
- 8001780: 434b muls r3, r1
- 8001782: 60fb str r3, [r7, #12]
+ 800173a: 683b ldr r3, [r7, #0]
+ 800173c: 685b ldr r3, [r3, #4]
+ 800173e: 3301 adds r3, #1
+ 8001740: 0019 movs r1, r3
+ 8001742: 6878 ldr r0, [r7, #4]
+ 8001744: f000 f8d0 bl 80018e8 <__udivsi3>
+ 8001748: 0003 movs r3, r0
+ 800174a: 0019 movs r1, r3
+ 800174c: 683b ldr r3, [r7, #0]
+ 800174e: 681b ldr r3, [r3, #0]
+ 8001750: 0c9b lsrs r3, r3, #18
+ 8001752: 220f movs r2, #15
+ 8001754: 4013 ands r3, r2
+ 8001756: 3302 adds r3, #2
+ 8001758: 434b muls r3, r1
+ 800175a: 60fb str r3, [r7, #12]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
- 8001784: 68fb ldr r3, [r7, #12]
+ 800175c: 68fb ldr r3, [r7, #12]
}
- 8001786: 0018 movs r0, r3
- 8001788: 46bd mov sp, r7
- 800178a: b004 add sp, #16
- 800178c: bd80 pop {r7, pc}
+ 800175e: 0018 movs r0, r3
+ 8001760: 46bd mov sp, r7
+ 8001762: b004 add sp, #16
+ 8001764: bd80 pop {r7, pc}
-0800178e <UTILS_PLL_IsBusy>:
+08001766 <UTILS_PLL_IsBusy>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
- 800178e: b580 push {r7, lr}
- 8001790: b082 sub sp, #8
- 8001792: af00 add r7, sp, #0
+ 8001766: b580 push {r7, lr}
+ 8001768: b082 sub sp, #8
+ 800176a: af00 add r7, sp, #0
ErrorStatus status = SUCCESS;
- 8001794: 1dfb adds r3, r7, #7
- 8001796: 2201 movs r2, #1
- 8001798: 701a strb r2, [r3, #0]
+ 800176c: 1dfb adds r3, r7, #7
+ 800176e: 2201 movs r2, #1
+ 8001770: 701a strb r2, [r3, #0]
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
- 800179a: f7ff fe63 bl 8001464 <LL_RCC_PLL_IsReady>
- 800179e: 1e03 subs r3, r0, #0
- 80017a0: d002 beq.n 80017a8 <UTILS_PLL_IsBusy+0x1a>
+ 8001772: f7ff fe63 bl 800143c <LL_RCC_PLL_IsReady>
+ 8001776: 1e03 subs r3, r0, #0
+ 8001778: d002 beq.n 8001780 <UTILS_PLL_IsBusy+0x1a>
{
/* PLL configuration cannot be modified */
status = ERROR;
- 80017a2: 1dfb adds r3, r7, #7
- 80017a4: 2200 movs r2, #0
- 80017a6: 701a strb r2, [r3, #0]
+ 800177a: 1dfb adds r3, r7, #7
+ 800177c: 2200 movs r2, #0
+ 800177e: 701a strb r2, [r3, #0]
}
return status;
- 80017a8: 1dfb adds r3, r7, #7
- 80017aa: 781b ldrb r3, [r3, #0]
+ 8001780: 1dfb adds r3, r7, #7
+ 8001782: 781b ldrb r3, [r3, #0]
}
- 80017ac: 0018 movs r0, r3
- 80017ae: 46bd mov sp, r7
- 80017b0: b002 add sp, #8
- 80017b2: bd80 pop {r7, pc}
+ 8001784: 0018 movs r0, r3
+ 8001786: 46bd mov sp, r7
+ 8001788: b002 add sp, #8
+ 800178a: bd80 pop {r7, pc}
-080017b4 <UTILS_EnablePLLAndSwitchSystem>:
+0800178c <UTILS_EnablePLLAndSwitchSystem>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 80017b4: b590 push {r4, r7, lr}
- 80017b6: b085 sub sp, #20
- 80017b8: af00 add r7, sp, #0
- 80017ba: 6078 str r0, [r7, #4]
- 80017bc: 6039 str r1, [r7, #0]
+ 800178c: b590 push {r4, r7, lr}
+ 800178e: b085 sub sp, #20
+ 8001790: af00 add r7, sp, #0
+ 8001792: 6078 str r0, [r7, #4]
+ 8001794: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 80017be: 200f movs r0, #15
- 80017c0: 183b adds r3, r7, r0
- 80017c2: 2201 movs r2, #1
- 80017c4: 701a strb r2, [r3, #0]
+ 8001796: 200f movs r0, #15
+ 8001798: 183b adds r3, r7, r0
+ 800179a: 2201 movs r2, #1
+ 800179c: 701a strb r2, [r3, #0]
uint32_t sysclk_frequency_current = 0U;
- 80017c6: 2300 movs r3, #0
- 80017c8: 60bb str r3, [r7, #8]
+ 800179e: 2300 movs r3, #0
+ 80017a0: 60bb str r3, [r7, #8]
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
- 80017ca: 4b2e ldr r3, [pc, #184] ; (8001884 <UTILS_EnablePLLAndSwitchSystem+0xd0>)
- 80017cc: 681a ldr r2, [r3, #0]
- 80017ce: 683b ldr r3, [r7, #0]
- 80017d0: 681b ldr r3, [r3, #0]
- 80017d2: 091b lsrs r3, r3, #4
- 80017d4: 210f movs r1, #15
- 80017d6: 400b ands r3, r1
- 80017d8: 492b ldr r1, [pc, #172] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 80017da: 5ccb ldrb r3, [r1, r3]
- 80017dc: 409a lsls r2, r3
- 80017de: 0013 movs r3, r2
- 80017e0: 60bb str r3, [r7, #8]
+ 80017a2: 4b2e ldr r3, [pc, #184] ; (800185c <UTILS_EnablePLLAndSwitchSystem+0xd0>)
+ 80017a4: 681a ldr r2, [r3, #0]
+ 80017a6: 683b ldr r3, [r7, #0]
+ 80017a8: 681b ldr r3, [r3, #0]
+ 80017aa: 091b lsrs r3, r3, #4
+ 80017ac: 210f movs r1, #15
+ 80017ae: 400b ands r3, r1
+ 80017b0: 492b ldr r1, [pc, #172] ; (8001860 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 80017b2: 5ccb ldrb r3, [r1, r3]
+ 80017b4: 409a lsls r2, r3
+ 80017b6: 0013 movs r3, r2
+ 80017b8: 60bb str r3, [r7, #8]
/* Increasing the number of wait states because of higher CPU frequency */
if (sysclk_frequency_current < SYSCLK_Frequency)
- 80017e2: 68ba ldr r2, [r7, #8]
- 80017e4: 687b ldr r3, [r7, #4]
- 80017e6: 429a cmp r2, r3
- 80017e8: d206 bcs.n 80017f8 <UTILS_EnablePLLAndSwitchSystem+0x44>
+ 80017ba: 68ba ldr r2, [r7, #8]
+ 80017bc: 687b ldr r3, [r7, #4]
+ 80017be: 429a cmp r2, r3
+ 80017c0: d206 bcs.n 80017d0 <UTILS_EnablePLLAndSwitchSystem+0x44>
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 80017ea: 183c adds r4, r7, r0
- 80017ec: 687b ldr r3, [r7, #4]
- 80017ee: 0018 movs r0, r3
- 80017f0: f7ff ff82 bl 80016f8 <UTILS_SetFlashLatency>
- 80017f4: 0003 movs r3, r0
- 80017f6: 7023 strb r3, [r4, #0]
+ 80017c2: 183c adds r4, r7, r0
+ 80017c4: 687b ldr r3, [r7, #4]
+ 80017c6: 0018 movs r0, r3
+ 80017c8: f7ff ff82 bl 80016d0 <UTILS_SetFlashLatency>
+ 80017cc: 0003 movs r3, r0
+ 80017ce: 7023 strb r3, [r4, #0]
}
/* Update system clock configuration */
if (status == SUCCESS)
- 80017f8: 230f movs r3, #15
- 80017fa: 18fb adds r3, r7, r3
- 80017fc: 781b ldrb r3, [r3, #0]
- 80017fe: 2b01 cmp r3, #1
- 8001800: d11a bne.n 8001838 <UTILS_EnablePLLAndSwitchSystem+0x84>
+ 80017d0: 230f movs r3, #15
+ 80017d2: 18fb adds r3, r7, r3
+ 80017d4: 781b ldrb r3, [r3, #0]
+ 80017d6: 2b01 cmp r3, #1
+ 80017d8: d11a bne.n 8001810 <UTILS_EnablePLLAndSwitchSystem+0x84>
{
/* Enable PLL */
LL_RCC_PLL_Enable();
- 8001802: f7ff fe21 bl 8001448 <LL_RCC_PLL_Enable>
+ 80017da: f7ff fe21 bl 8001420 <LL_RCC_PLL_Enable>
while (LL_RCC_PLL_IsReady() != 1U)
- 8001806: 46c0 nop ; (mov r8, r8)
- 8001808: f7ff fe2c bl 8001464 <LL_RCC_PLL_IsReady>
- 800180c: 0003 movs r3, r0
- 800180e: 2b01 cmp r3, #1
- 8001810: d1fa bne.n 8001808 <UTILS_EnablePLLAndSwitchSystem+0x54>
+ 80017de: 46c0 nop ; (mov r8, r8)
+ 80017e0: f7ff fe2c bl 800143c <LL_RCC_PLL_IsReady>
+ 80017e4: 0003 movs r3, r0
+ 80017e6: 2b01 cmp r3, #1
+ 80017e8: d1fa bne.n 80017e0 <UTILS_EnablePLLAndSwitchSystem+0x54>
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- 8001812: 683b ldr r3, [r7, #0]
- 8001814: 681b ldr r3, [r3, #0]
- 8001816: 0018 movs r0, r3
- 8001818: f7ff fdec bl 80013f4 <LL_RCC_SetAHBPrescaler>
+ 80017ea: 683b ldr r3, [r7, #0]
+ 80017ec: 681b ldr r3, [r3, #0]
+ 80017ee: 0018 movs r0, r3
+ 80017f0: f7ff fdec bl 80013cc <LL_RCC_SetAHBPrescaler>
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 800181c: 2002 movs r0, #2
- 800181e: f7ff fdc9 bl 80013b4 <LL_RCC_SetSysClkSource>
+ 80017f4: 2002 movs r0, #2
+ 80017f6: f7ff fdc9 bl 800138c <LL_RCC_SetSysClkSource>
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 8001822: 46c0 nop ; (mov r8, r8)
- 8001824: f7ff fdda bl 80013dc <LL_RCC_GetSysClkSource>
- 8001828: 0003 movs r3, r0
- 800182a: 2b08 cmp r3, #8
- 800182c: d1fa bne.n 8001824 <UTILS_EnablePLLAndSwitchSystem+0x70>
+ 80017fa: 46c0 nop ; (mov r8, r8)
+ 80017fc: f7ff fdda bl 80013b4 <LL_RCC_GetSysClkSource>
+ 8001800: 0003 movs r3, r0
+ 8001802: 2b08 cmp r3, #8
+ 8001804: d1fa bne.n 80017fc <UTILS_EnablePLLAndSwitchSystem+0x70>
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- 800182e: 683b ldr r3, [r7, #0]
- 8001830: 685b ldr r3, [r3, #4]
- 8001832: 0018 movs r0, r3
- 8001834: f7ff fdf2 bl 800141c <LL_RCC_SetAPB1Prescaler>
+ 8001806: 683b ldr r3, [r7, #0]
+ 8001808: 685b ldr r3, [r3, #4]
+ 800180a: 0018 movs r0, r3
+ 800180c: f7ff fdf2 bl 80013f4 <LL_RCC_SetAPB1Prescaler>
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (sysclk_frequency_current > SYSCLK_Frequency)
- 8001838: 68ba ldr r2, [r7, #8]
- 800183a: 687b ldr r3, [r7, #4]
- 800183c: 429a cmp r2, r3
- 800183e: d907 bls.n 8001850 <UTILS_EnablePLLAndSwitchSystem+0x9c>
+ 8001810: 68ba ldr r2, [r7, #8]
+ 8001812: 687b ldr r3, [r7, #4]
+ 8001814: 429a cmp r2, r3
+ 8001816: d907 bls.n 8001828 <UTILS_EnablePLLAndSwitchSystem+0x9c>
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 8001840: 230f movs r3, #15
- 8001842: 18fc adds r4, r7, r3
- 8001844: 687b ldr r3, [r7, #4]
- 8001846: 0018 movs r0, r3
- 8001848: f7ff ff56 bl 80016f8 <UTILS_SetFlashLatency>
- 800184c: 0003 movs r3, r0
- 800184e: 7023 strb r3, [r4, #0]
+ 8001818: 230f movs r3, #15
+ 800181a: 18fc adds r4, r7, r3
+ 800181c: 687b ldr r3, [r7, #4]
+ 800181e: 0018 movs r0, r3
+ 8001820: f7ff ff56 bl 80016d0 <UTILS_SetFlashLatency>
+ 8001824: 0003 movs r3, r0
+ 8001826: 7023 strb r3, [r4, #0]
}
/* Update SystemCoreClock variable */
if (status == SUCCESS)
- 8001850: 230f movs r3, #15
- 8001852: 18fb adds r3, r7, r3
- 8001854: 781b ldrb r3, [r3, #0]
- 8001856: 2b01 cmp r3, #1
- 8001858: d10c bne.n 8001874 <UTILS_EnablePLLAndSwitchSystem+0xc0>
+ 8001828: 230f movs r3, #15
+ 800182a: 18fb adds r3, r7, r3
+ 800182c: 781b ldrb r3, [r3, #0]
+ 800182e: 2b01 cmp r3, #1
+ 8001830: d10c bne.n 800184c <UTILS_EnablePLLAndSwitchSystem+0xc0>
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- 800185a: 683b ldr r3, [r7, #0]
- 800185c: 681b ldr r3, [r3, #0]
- 800185e: 091b lsrs r3, r3, #4
- 8001860: 220f movs r2, #15
- 8001862: 4013 ands r3, r2
- 8001864: 4a08 ldr r2, [pc, #32] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 8001866: 5cd3 ldrb r3, [r2, r3]
- 8001868: 001a movs r2, r3
- 800186a: 687b ldr r3, [r7, #4]
- 800186c: 40d3 lsrs r3, r2
- 800186e: 0018 movs r0, r3
- 8001870: f7ff fe9e bl 80015b0 <LL_SetSystemCoreClock>
+ 8001832: 683b ldr r3, [r7, #0]
+ 8001834: 681b ldr r3, [r3, #0]
+ 8001836: 091b lsrs r3, r3, #4
+ 8001838: 220f movs r2, #15
+ 800183a: 4013 ands r3, r2
+ 800183c: 4a08 ldr r2, [pc, #32] ; (8001860 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 800183e: 5cd3 ldrb r3, [r2, r3]
+ 8001840: 001a movs r2, r3
+ 8001842: 687b ldr r3, [r7, #4]
+ 8001844: 40d3 lsrs r3, r2
+ 8001846: 0018 movs r0, r3
+ 8001848: f7ff fe9e bl 8001588 <LL_SetSystemCoreClock>
}
return status;
- 8001874: 230f movs r3, #15
- 8001876: 18fb adds r3, r7, r3
- 8001878: 781b ldrb r3, [r3, #0]
+ 800184c: 230f movs r3, #15
+ 800184e: 18fb adds r3, r7, r3
+ 8001850: 781b ldrb r3, [r3, #0]
}
- 800187a: 0018 movs r0, r3
- 800187c: 46bd mov sp, r7
- 800187e: b005 add sp, #20
- 8001880: bd90 pop {r4, r7, pc}
- 8001882: 46c0 nop ; (mov r8, r8)
- 8001884: 20000000 .word 0x20000000
- 8001888: 08001c4c .word 0x08001c4c
-
-0800188c <__sinit>:
+ 8001852: 0018 movs r0, r3
+ 8001854: 46bd mov sp, r7
+ 8001856: b005 add sp, #20
+ 8001858: bd90 pop {r4, r7, pc}
+ 800185a: 46c0 nop ; (mov r8, r8)
+ 800185c: 20000000 .word 0x20000000
+ 8001860: 08001c24 .word 0x08001c24
+
+08001864 <__sinit>:
#include <stdbool.h>
int __errno = 0;
void *_impure_ptr = NULL;
void __sinit(void) {
- 800188c: b580 push {r7, lr}
- 800188e: af00 add r7, sp, #0
+ 8001864: b580 push {r7, lr}
+ 8001866: af00 add r7, sp, #0
}
- 8001890: 46c0 nop ; (mov r8, r8)
- 8001892: 46bd mov sp, r7
- 8001894: bd80 pop {r7, pc}
+ 8001868: 46c0 nop ; (mov r8, r8)
+ 800186a: 46bd mov sp, r7
+ 800186c: bd80 pop {r7, pc}
-08001896 <memset>:
+0800186e <memset>:
void *memset(void *s, int c, size_t n) {
- 8001896: b580 push {r7, lr}
- 8001898: b086 sub sp, #24
- 800189a: af00 add r7, sp, #0
- 800189c: 60f8 str r0, [r7, #12]
- 800189e: 60b9 str r1, [r7, #8]
- 80018a0: 607a str r2, [r7, #4]
+ 800186e: b580 push {r7, lr}
+ 8001870: b086 sub sp, #24
+ 8001872: af00 add r7, sp, #0
+ 8001874: 60f8 str r0, [r7, #12]
+ 8001876: 60b9 str r1, [r7, #8]
+ 8001878: 607a str r2, [r7, #4]
char *end = (char *)s + n;
- 80018a2: 68fa ldr r2, [r7, #12]
- 80018a4: 687b ldr r3, [r7, #4]
- 80018a6: 18d3 adds r3, r2, r3
- 80018a8: 613b str r3, [r7, #16]
+ 800187a: 68fa ldr r2, [r7, #12]
+ 800187c: 687b ldr r3, [r7, #4]
+ 800187e: 18d3 adds r3, r2, r3
+ 8001880: 613b str r3, [r7, #16]
for (char *p = (char *)s; p < end; p++)
- 80018aa: 68fb ldr r3, [r7, #12]
- 80018ac: 617b str r3, [r7, #20]
- 80018ae: e006 b.n 80018be <memset+0x28>
+ 8001882: 68fb ldr r3, [r7, #12]
+ 8001884: 617b str r3, [r7, #20]
+ 8001886: e006 b.n 8001896 <memset+0x28>
*p = (char)c;
- 80018b0: 68bb ldr r3, [r7, #8]
- 80018b2: b2da uxtb r2, r3
- 80018b4: 697b ldr r3, [r7, #20]
- 80018b6: 701a strb r2, [r3, #0]
+ 8001888: 68bb ldr r3, [r7, #8]
+ 800188a: b2da uxtb r2, r3
+ 800188c: 697b ldr r3, [r7, #20]
+ 800188e: 701a strb r2, [r3, #0]
for (char *p = (char *)s; p < end; p++)
- 80018b8: 697b ldr r3, [r7, #20]
- 80018ba: 3301 adds r3, #1
- 80018bc: 617b str r3, [r7, #20]
- 80018be: 697a ldr r2, [r7, #20]
- 80018c0: 693b ldr r3, [r7, #16]
- 80018c2: 429a cmp r2, r3
- 80018c4: d3f4 bcc.n 80018b0 <memset+0x1a>
+ 8001890: 697b ldr r3, [r7, #20]
+ 8001892: 3301 adds r3, #1
+ 8001894: 617b str r3, [r7, #20]
+ 8001896: 697a ldr r2, [r7, #20]
+ 8001898: 693b ldr r3, [r7, #16]
+ 800189a: 429a cmp r2, r3
+ 800189c: d3f4 bcc.n 8001888 <memset+0x1a>
return s;
- 80018c6: 68fb ldr r3, [r7, #12]
+ 800189e: 68fb ldr r3, [r7, #12]
}
- 80018c8: 0018 movs r0, r3
- 80018ca: 46bd mov sp, r7
- 80018cc: b006 add sp, #24
- 80018ce: bd80 pop {r7, pc}
+ 80018a0: 0018 movs r0, r3
+ 80018a2: 46bd mov sp, r7
+ 80018a4: b006 add sp, #24
+ 80018a6: bd80 pop {r7, pc}
-080018d0 <strlen>:
+080018a8 <strlen>:
size_t strlen(const char *s) {
- 80018d0: b580 push {r7, lr}
- 80018d2: b084 sub sp, #16
- 80018d4: af00 add r7, sp, #0
- 80018d6: 6078 str r0, [r7, #4]
+ 80018a8: b580 push {r7, lr}
+ 80018aa: b084 sub sp, #16
+ 80018ac: af00 add r7, sp, #0
+ 80018ae: 6078 str r0, [r7, #4]
const char *start = s;
- 80018d8: 687b ldr r3, [r7, #4]
- 80018da: 60fb str r3, [r7, #12]
+ 80018b0: 687b ldr r3, [r7, #4]
+ 80018b2: 60fb str r3, [r7, #12]
while (*s++);
- 80018dc: 46c0 nop ; (mov r8, r8)
- 80018de: 687b ldr r3, [r7, #4]
- 80018e0: 1c5a adds r2, r3, #1
- 80018e2: 607a str r2, [r7, #4]
- 80018e4: 781b ldrb r3, [r3, #0]
- 80018e6: 2b00 cmp r3, #0
- 80018e8: d1f9 bne.n 80018de <strlen+0xe>
+ 80018b4: 46c0 nop ; (mov r8, r8)
+ 80018b6: 687b ldr r3, [r7, #4]
+ 80018b8: 1c5a adds r2, r3, #1
+ 80018ba: 607a str r2, [r7, #4]
+ 80018bc: 781b ldrb r3, [r3, #0]
+ 80018be: 2b00 cmp r3, #0
+ 80018c0: d1f9 bne.n 80018b6 <strlen+0xe>
return s - start - 1;
- 80018ea: 687a ldr r2, [r7, #4]
- 80018ec: 68fb ldr r3, [r7, #12]
- 80018ee: 1ad3 subs r3, r2, r3
- 80018f0: 3b01 subs r3, #1
+ 80018c2: 687a ldr r2, [r7, #4]
+ 80018c4: 68fb ldr r3, [r7, #12]
+ 80018c6: 1ad3 subs r3, r2, r3
+ 80018c8: 3b01 subs r3, #1
}
- 80018f2: 0018 movs r0, r3
- 80018f4: 46bd mov sp, r7
- 80018f6: b004 add sp, #16
- 80018f8: bd80 pop {r7, pc}
+ 80018ca: 0018 movs r0, r3
+ 80018cc: 46bd mov sp, r7
+ 80018ce: b004 add sp, #16
+ 80018d0: bd80 pop {r7, pc}
-080018fa <__assert_func>:
+080018d2 <__assert_func>:
void __assert_func(bool value) {
- 80018fa: b580 push {r7, lr}
- 80018fc: b082 sub sp, #8
- 80018fe: af00 add r7, sp, #0
- 8001900: 0002 movs r2, r0
- 8001902: 1dfb adds r3, r7, #7
- 8001904: 701a strb r2, [r3, #0]
+ 80018d2: b580 push {r7, lr}
+ 80018d4: b082 sub sp, #8
+ 80018d6: af00 add r7, sp, #0
+ 80018d8: 0002 movs r2, r0
+ 80018da: 1dfb adds r3, r7, #7
+ 80018dc: 701a strb r2, [r3, #0]
}
- 8001906: 46c0 nop ; (mov r8, r8)
- 8001908: 46bd mov sp, r7
- 800190a: b002 add sp, #8
- 800190c: bd80 pop {r7, pc}
+ 80018de: 46c0 nop ; (mov r8, r8)
+ 80018e0: 46bd mov sp, r7
+ 80018e2: b002 add sp, #8
+ 80018e4: bd80 pop {r7, pc}
...
-08001910 <__udivsi3>:
- 8001910: 2200 movs r2, #0
- 8001912: 0843 lsrs r3, r0, #1
- 8001914: 428b cmp r3, r1
- 8001916: d374 bcc.n 8001a02 <__udivsi3+0xf2>
- 8001918: 0903 lsrs r3, r0, #4
- 800191a: 428b cmp r3, r1
- 800191c: d35f bcc.n 80019de <__udivsi3+0xce>
- 800191e: 0a03 lsrs r3, r0, #8
- 8001920: 428b cmp r3, r1
- 8001922: d344 bcc.n 80019ae <__udivsi3+0x9e>
- 8001924: 0b03 lsrs r3, r0, #12
+080018e8 <__udivsi3>:
+ 80018e8: 2200 movs r2, #0
+ 80018ea: 0843 lsrs r3, r0, #1
+ 80018ec: 428b cmp r3, r1
+ 80018ee: d374 bcc.n 80019da <__udivsi3+0xf2>
+ 80018f0: 0903 lsrs r3, r0, #4
+ 80018f2: 428b cmp r3, r1
+ 80018f4: d35f bcc.n 80019b6 <__udivsi3+0xce>
+ 80018f6: 0a03 lsrs r3, r0, #8
+ 80018f8: 428b cmp r3, r1
+ 80018fa: d344 bcc.n 8001986 <__udivsi3+0x9e>
+ 80018fc: 0b03 lsrs r3, r0, #12
+ 80018fe: 428b cmp r3, r1
+ 8001900: d328 bcc.n 8001954 <__udivsi3+0x6c>
+ 8001902: 0c03 lsrs r3, r0, #16
+ 8001904: 428b cmp r3, r1
+ 8001906: d30d bcc.n 8001924 <__udivsi3+0x3c>
+ 8001908: 22ff movs r2, #255 ; 0xff
+ 800190a: 0209 lsls r1, r1, #8
+ 800190c: ba12 rev r2, r2
+ 800190e: 0c03 lsrs r3, r0, #16
+ 8001910: 428b cmp r3, r1
+ 8001912: d302 bcc.n 800191a <__udivsi3+0x32>
+ 8001914: 1212 asrs r2, r2, #8
+ 8001916: 0209 lsls r1, r1, #8
+ 8001918: d065 beq.n 80019e6 <__udivsi3+0xfe>
+ 800191a: 0b03 lsrs r3, r0, #12
+ 800191c: 428b cmp r3, r1
+ 800191e: d319 bcc.n 8001954 <__udivsi3+0x6c>
+ 8001920: e000 b.n 8001924 <__udivsi3+0x3c>
+ 8001922: 0a09 lsrs r1, r1, #8
+ 8001924: 0bc3 lsrs r3, r0, #15
8001926: 428b cmp r3, r1
- 8001928: d328 bcc.n 800197c <__udivsi3+0x6c>
- 800192a: 0c03 lsrs r3, r0, #16
- 800192c: 428b cmp r3, r1
- 800192e: d30d bcc.n 800194c <__udivsi3+0x3c>
- 8001930: 22ff movs r2, #255 ; 0xff
- 8001932: 0209 lsls r1, r1, #8
- 8001934: ba12 rev r2, r2
- 8001936: 0c03 lsrs r3, r0, #16
- 8001938: 428b cmp r3, r1
- 800193a: d302 bcc.n 8001942 <__udivsi3+0x32>
- 800193c: 1212 asrs r2, r2, #8
- 800193e: 0209 lsls r1, r1, #8
- 8001940: d065 beq.n 8001a0e <__udivsi3+0xfe>
- 8001942: 0b03 lsrs r3, r0, #12
- 8001944: 428b cmp r3, r1
- 8001946: d319 bcc.n 800197c <__udivsi3+0x6c>
- 8001948: e000 b.n 800194c <__udivsi3+0x3c>
- 800194a: 0a09 lsrs r1, r1, #8
- 800194c: 0bc3 lsrs r3, r0, #15
- 800194e: 428b cmp r3, r1
- 8001950: d301 bcc.n 8001956 <__udivsi3+0x46>
- 8001952: 03cb lsls r3, r1, #15
- 8001954: 1ac0 subs r0, r0, r3
- 8001956: 4152 adcs r2, r2
- 8001958: 0b83 lsrs r3, r0, #14
- 800195a: 428b cmp r3, r1
- 800195c: d301 bcc.n 8001962 <__udivsi3+0x52>
- 800195e: 038b lsls r3, r1, #14
- 8001960: 1ac0 subs r0, r0, r3
- 8001962: 4152 adcs r2, r2
- 8001964: 0b43 lsrs r3, r0, #13
- 8001966: 428b cmp r3, r1
- 8001968: d301 bcc.n 800196e <__udivsi3+0x5e>
- 800196a: 034b lsls r3, r1, #13
- 800196c: 1ac0 subs r0, r0, r3
- 800196e: 4152 adcs r2, r2
- 8001970: 0b03 lsrs r3, r0, #12
- 8001972: 428b cmp r3, r1
- 8001974: d301 bcc.n 800197a <__udivsi3+0x6a>
- 8001976: 030b lsls r3, r1, #12
- 8001978: 1ac0 subs r0, r0, r3
- 800197a: 4152 adcs r2, r2
- 800197c: 0ac3 lsrs r3, r0, #11
- 800197e: 428b cmp r3, r1
- 8001980: d301 bcc.n 8001986 <__udivsi3+0x76>
- 8001982: 02cb lsls r3, r1, #11
- 8001984: 1ac0 subs r0, r0, r3
- 8001986: 4152 adcs r2, r2
- 8001988: 0a83 lsrs r3, r0, #10
- 800198a: 428b cmp r3, r1
- 800198c: d301 bcc.n 8001992 <__udivsi3+0x82>
- 800198e: 028b lsls r3, r1, #10
- 8001990: 1ac0 subs r0, r0, r3
- 8001992: 4152 adcs r2, r2
- 8001994: 0a43 lsrs r3, r0, #9
- 8001996: 428b cmp r3, r1
- 8001998: d301 bcc.n 800199e <__udivsi3+0x8e>
- 800199a: 024b lsls r3, r1, #9
- 800199c: 1ac0 subs r0, r0, r3
- 800199e: 4152 adcs r2, r2
- 80019a0: 0a03 lsrs r3, r0, #8
- 80019a2: 428b cmp r3, r1
- 80019a4: d301 bcc.n 80019aa <__udivsi3+0x9a>
- 80019a6: 020b lsls r3, r1, #8
- 80019a8: 1ac0 subs r0, r0, r3
- 80019aa: 4152 adcs r2, r2
- 80019ac: d2cd bcs.n 800194a <__udivsi3+0x3a>
- 80019ae: 09c3 lsrs r3, r0, #7
- 80019b0: 428b cmp r3, r1
- 80019b2: d301 bcc.n 80019b8 <__udivsi3+0xa8>
- 80019b4: 01cb lsls r3, r1, #7
- 80019b6: 1ac0 subs r0, r0, r3
- 80019b8: 4152 adcs r2, r2
- 80019ba: 0983 lsrs r3, r0, #6
- 80019bc: 428b cmp r3, r1
- 80019be: d301 bcc.n 80019c4 <__udivsi3+0xb4>
- 80019c0: 018b lsls r3, r1, #6
- 80019c2: 1ac0 subs r0, r0, r3
- 80019c4: 4152 adcs r2, r2
- 80019c6: 0943 lsrs r3, r0, #5
- 80019c8: 428b cmp r3, r1
- 80019ca: d301 bcc.n 80019d0 <__udivsi3+0xc0>
- 80019cc: 014b lsls r3, r1, #5
- 80019ce: 1ac0 subs r0, r0, r3
- 80019d0: 4152 adcs r2, r2
- 80019d2: 0903 lsrs r3, r0, #4
- 80019d4: 428b cmp r3, r1
- 80019d6: d301 bcc.n 80019dc <__udivsi3+0xcc>
- 80019d8: 010b lsls r3, r1, #4
- 80019da: 1ac0 subs r0, r0, r3
- 80019dc: 4152 adcs r2, r2
- 80019de: 08c3 lsrs r3, r0, #3
- 80019e0: 428b cmp r3, r1
- 80019e2: d301 bcc.n 80019e8 <__udivsi3+0xd8>
- 80019e4: 00cb lsls r3, r1, #3
- 80019e6: 1ac0 subs r0, r0, r3
- 80019e8: 4152 adcs r2, r2
- 80019ea: 0883 lsrs r3, r0, #2
- 80019ec: 428b cmp r3, r1
- 80019ee: d301 bcc.n 80019f4 <__udivsi3+0xe4>
- 80019f0: 008b lsls r3, r1, #2
- 80019f2: 1ac0 subs r0, r0, r3
- 80019f4: 4152 adcs r2, r2
- 80019f6: 0843 lsrs r3, r0, #1
- 80019f8: 428b cmp r3, r1
- 80019fa: d301 bcc.n 8001a00 <__udivsi3+0xf0>
- 80019fc: 004b lsls r3, r1, #1
- 80019fe: 1ac0 subs r0, r0, r3
- 8001a00: 4152 adcs r2, r2
- 8001a02: 1a41 subs r1, r0, r1
- 8001a04: d200 bcs.n 8001a08 <__udivsi3+0xf8>
- 8001a06: 4601 mov r1, r0
- 8001a08: 4152 adcs r2, r2
- 8001a0a: 4610 mov r0, r2
- 8001a0c: 4770 bx lr
- 8001a0e: e7ff b.n 8001a10 <__udivsi3+0x100>
- 8001a10: b501 push {r0, lr}
- 8001a12: 2000 movs r0, #0
- 8001a14: f000 f8f0 bl 8001bf8 <__aeabi_idiv0>
- 8001a18: bd02 pop {r1, pc}
- 8001a1a: 46c0 nop ; (mov r8, r8)
-
-08001a1c <__aeabi_uidivmod>:
- 8001a1c: 2900 cmp r1, #0
- 8001a1e: d0f7 beq.n 8001a10 <__udivsi3+0x100>
- 8001a20: e776 b.n 8001910 <__udivsi3>
- 8001a22: 4770 bx lr
-
-08001a24 <__divsi3>:
- 8001a24: 4603 mov r3, r0
- 8001a26: 430b orrs r3, r1
- 8001a28: d47f bmi.n 8001b2a <__divsi3+0x106>
- 8001a2a: 2200 movs r2, #0
- 8001a2c: 0843 lsrs r3, r0, #1
- 8001a2e: 428b cmp r3, r1
- 8001a30: d374 bcc.n 8001b1c <__divsi3+0xf8>
- 8001a32: 0903 lsrs r3, r0, #4
- 8001a34: 428b cmp r3, r1
- 8001a36: d35f bcc.n 8001af8 <__divsi3+0xd4>
- 8001a38: 0a03 lsrs r3, r0, #8
- 8001a3a: 428b cmp r3, r1
- 8001a3c: d344 bcc.n 8001ac8 <__divsi3+0xa4>
- 8001a3e: 0b03 lsrs r3, r0, #12
+ 8001928: d301 bcc.n 800192e <__udivsi3+0x46>
+ 800192a: 03cb lsls r3, r1, #15
+ 800192c: 1ac0 subs r0, r0, r3
+ 800192e: 4152 adcs r2, r2
+ 8001930: 0b83 lsrs r3, r0, #14
+ 8001932: 428b cmp r3, r1
+ 8001934: d301 bcc.n 800193a <__udivsi3+0x52>
+ 8001936: 038b lsls r3, r1, #14
+ 8001938: 1ac0 subs r0, r0, r3
+ 800193a: 4152 adcs r2, r2
+ 800193c: 0b43 lsrs r3, r0, #13
+ 800193e: 428b cmp r3, r1
+ 8001940: d301 bcc.n 8001946 <__udivsi3+0x5e>
+ 8001942: 034b lsls r3, r1, #13
+ 8001944: 1ac0 subs r0, r0, r3
+ 8001946: 4152 adcs r2, r2
+ 8001948: 0b03 lsrs r3, r0, #12
+ 800194a: 428b cmp r3, r1
+ 800194c: d301 bcc.n 8001952 <__udivsi3+0x6a>
+ 800194e: 030b lsls r3, r1, #12
+ 8001950: 1ac0 subs r0, r0, r3
+ 8001952: 4152 adcs r2, r2
+ 8001954: 0ac3 lsrs r3, r0, #11
+ 8001956: 428b cmp r3, r1
+ 8001958: d301 bcc.n 800195e <__udivsi3+0x76>
+ 800195a: 02cb lsls r3, r1, #11
+ 800195c: 1ac0 subs r0, r0, r3
+ 800195e: 4152 adcs r2, r2
+ 8001960: 0a83 lsrs r3, r0, #10
+ 8001962: 428b cmp r3, r1
+ 8001964: d301 bcc.n 800196a <__udivsi3+0x82>
+ 8001966: 028b lsls r3, r1, #10
+ 8001968: 1ac0 subs r0, r0, r3
+ 800196a: 4152 adcs r2, r2
+ 800196c: 0a43 lsrs r3, r0, #9
+ 800196e: 428b cmp r3, r1
+ 8001970: d301 bcc.n 8001976 <__udivsi3+0x8e>
+ 8001972: 024b lsls r3, r1, #9
+ 8001974: 1ac0 subs r0, r0, r3
+ 8001976: 4152 adcs r2, r2
+ 8001978: 0a03 lsrs r3, r0, #8
+ 800197a: 428b cmp r3, r1
+ 800197c: d301 bcc.n 8001982 <__udivsi3+0x9a>
+ 800197e: 020b lsls r3, r1, #8
+ 8001980: 1ac0 subs r0, r0, r3
+ 8001982: 4152 adcs r2, r2
+ 8001984: d2cd bcs.n 8001922 <__udivsi3+0x3a>
+ 8001986: 09c3 lsrs r3, r0, #7
+ 8001988: 428b cmp r3, r1
+ 800198a: d301 bcc.n 8001990 <__udivsi3+0xa8>
+ 800198c: 01cb lsls r3, r1, #7
+ 800198e: 1ac0 subs r0, r0, r3
+ 8001990: 4152 adcs r2, r2
+ 8001992: 0983 lsrs r3, r0, #6
+ 8001994: 428b cmp r3, r1
+ 8001996: d301 bcc.n 800199c <__udivsi3+0xb4>
+ 8001998: 018b lsls r3, r1, #6
+ 800199a: 1ac0 subs r0, r0, r3
+ 800199c: 4152 adcs r2, r2
+ 800199e: 0943 lsrs r3, r0, #5
+ 80019a0: 428b cmp r3, r1
+ 80019a2: d301 bcc.n 80019a8 <__udivsi3+0xc0>
+ 80019a4: 014b lsls r3, r1, #5
+ 80019a6: 1ac0 subs r0, r0, r3
+ 80019a8: 4152 adcs r2, r2
+ 80019aa: 0903 lsrs r3, r0, #4
+ 80019ac: 428b cmp r3, r1
+ 80019ae: d301 bcc.n 80019b4 <__udivsi3+0xcc>
+ 80019b0: 010b lsls r3, r1, #4
+ 80019b2: 1ac0 subs r0, r0, r3
+ 80019b4: 4152 adcs r2, r2
+ 80019b6: 08c3 lsrs r3, r0, #3
+ 80019b8: 428b cmp r3, r1
+ 80019ba: d301 bcc.n 80019c0 <__udivsi3+0xd8>
+ 80019bc: 00cb lsls r3, r1, #3
+ 80019be: 1ac0 subs r0, r0, r3
+ 80019c0: 4152 adcs r2, r2
+ 80019c2: 0883 lsrs r3, r0, #2
+ 80019c4: 428b cmp r3, r1
+ 80019c6: d301 bcc.n 80019cc <__udivsi3+0xe4>
+ 80019c8: 008b lsls r3, r1, #2
+ 80019ca: 1ac0 subs r0, r0, r3
+ 80019cc: 4152 adcs r2, r2
+ 80019ce: 0843 lsrs r3, r0, #1
+ 80019d0: 428b cmp r3, r1
+ 80019d2: d301 bcc.n 80019d8 <__udivsi3+0xf0>
+ 80019d4: 004b lsls r3, r1, #1
+ 80019d6: 1ac0 subs r0, r0, r3
+ 80019d8: 4152 adcs r2, r2
+ 80019da: 1a41 subs r1, r0, r1
+ 80019dc: d200 bcs.n 80019e0 <__udivsi3+0xf8>
+ 80019de: 4601 mov r1, r0
+ 80019e0: 4152 adcs r2, r2
+ 80019e2: 4610 mov r0, r2
+ 80019e4: 4770 bx lr
+ 80019e6: e7ff b.n 80019e8 <__udivsi3+0x100>
+ 80019e8: b501 push {r0, lr}
+ 80019ea: 2000 movs r0, #0
+ 80019ec: f000 f8f0 bl 8001bd0 <__aeabi_idiv0>
+ 80019f0: bd02 pop {r1, pc}
+ 80019f2: 46c0 nop ; (mov r8, r8)
+
+080019f4 <__aeabi_uidivmod>:
+ 80019f4: 2900 cmp r1, #0
+ 80019f6: d0f7 beq.n 80019e8 <__udivsi3+0x100>
+ 80019f8: e776 b.n 80018e8 <__udivsi3>
+ 80019fa: 4770 bx lr
+
+080019fc <__divsi3>:
+ 80019fc: 4603 mov r3, r0
+ 80019fe: 430b orrs r3, r1
+ 8001a00: d47f bmi.n 8001b02 <__divsi3+0x106>
+ 8001a02: 2200 movs r2, #0
+ 8001a04: 0843 lsrs r3, r0, #1
+ 8001a06: 428b cmp r3, r1
+ 8001a08: d374 bcc.n 8001af4 <__divsi3+0xf8>
+ 8001a0a: 0903 lsrs r3, r0, #4
+ 8001a0c: 428b cmp r3, r1
+ 8001a0e: d35f bcc.n 8001ad0 <__divsi3+0xd4>
+ 8001a10: 0a03 lsrs r3, r0, #8
+ 8001a12: 428b cmp r3, r1
+ 8001a14: d344 bcc.n 8001aa0 <__divsi3+0xa4>
+ 8001a16: 0b03 lsrs r3, r0, #12
+ 8001a18: 428b cmp r3, r1
+ 8001a1a: d328 bcc.n 8001a6e <__divsi3+0x72>
+ 8001a1c: 0c03 lsrs r3, r0, #16
+ 8001a1e: 428b cmp r3, r1
+ 8001a20: d30d bcc.n 8001a3e <__divsi3+0x42>
+ 8001a22: 22ff movs r2, #255 ; 0xff
+ 8001a24: 0209 lsls r1, r1, #8
+ 8001a26: ba12 rev r2, r2
+ 8001a28: 0c03 lsrs r3, r0, #16
+ 8001a2a: 428b cmp r3, r1
+ 8001a2c: d302 bcc.n 8001a34 <__divsi3+0x38>
+ 8001a2e: 1212 asrs r2, r2, #8
+ 8001a30: 0209 lsls r1, r1, #8
+ 8001a32: d065 beq.n 8001b00 <__divsi3+0x104>
+ 8001a34: 0b03 lsrs r3, r0, #12
+ 8001a36: 428b cmp r3, r1
+ 8001a38: d319 bcc.n 8001a6e <__divsi3+0x72>
+ 8001a3a: e000 b.n 8001a3e <__divsi3+0x42>
+ 8001a3c: 0a09 lsrs r1, r1, #8
+ 8001a3e: 0bc3 lsrs r3, r0, #15
8001a40: 428b cmp r3, r1
- 8001a42: d328 bcc.n 8001a96 <__divsi3+0x72>
- 8001a44: 0c03 lsrs r3, r0, #16
- 8001a46: 428b cmp r3, r1
- 8001a48: d30d bcc.n 8001a66 <__divsi3+0x42>
- 8001a4a: 22ff movs r2, #255 ; 0xff
- 8001a4c: 0209 lsls r1, r1, #8
- 8001a4e: ba12 rev r2, r2
- 8001a50: 0c03 lsrs r3, r0, #16
- 8001a52: 428b cmp r3, r1
- 8001a54: d302 bcc.n 8001a5c <__divsi3+0x38>
- 8001a56: 1212 asrs r2, r2, #8
- 8001a58: 0209 lsls r1, r1, #8
- 8001a5a: d065 beq.n 8001b28 <__divsi3+0x104>
- 8001a5c: 0b03 lsrs r3, r0, #12
- 8001a5e: 428b cmp r3, r1
- 8001a60: d319 bcc.n 8001a96 <__divsi3+0x72>
- 8001a62: e000 b.n 8001a66 <__divsi3+0x42>
- 8001a64: 0a09 lsrs r1, r1, #8
- 8001a66: 0bc3 lsrs r3, r0, #15
- 8001a68: 428b cmp r3, r1
- 8001a6a: d301 bcc.n 8001a70 <__divsi3+0x4c>
- 8001a6c: 03cb lsls r3, r1, #15
- 8001a6e: 1ac0 subs r0, r0, r3
- 8001a70: 4152 adcs r2, r2
- 8001a72: 0b83 lsrs r3, r0, #14
- 8001a74: 428b cmp r3, r1
- 8001a76: d301 bcc.n 8001a7c <__divsi3+0x58>
- 8001a78: 038b lsls r3, r1, #14
- 8001a7a: 1ac0 subs r0, r0, r3
- 8001a7c: 4152 adcs r2, r2
- 8001a7e: 0b43 lsrs r3, r0, #13
- 8001a80: 428b cmp r3, r1
- 8001a82: d301 bcc.n 8001a88 <__divsi3+0x64>
- 8001a84: 034b lsls r3, r1, #13
- 8001a86: 1ac0 subs r0, r0, r3
- 8001a88: 4152 adcs r2, r2
- 8001a8a: 0b03 lsrs r3, r0, #12
- 8001a8c: 428b cmp r3, r1
- 8001a8e: d301 bcc.n 8001a94 <__divsi3+0x70>
- 8001a90: 030b lsls r3, r1, #12
- 8001a92: 1ac0 subs r0, r0, r3
- 8001a94: 4152 adcs r2, r2
- 8001a96: 0ac3 lsrs r3, r0, #11
- 8001a98: 428b cmp r3, r1
- 8001a9a: d301 bcc.n 8001aa0 <__divsi3+0x7c>
- 8001a9c: 02cb lsls r3, r1, #11
- 8001a9e: 1ac0 subs r0, r0, r3
- 8001aa0: 4152 adcs r2, r2
- 8001aa2: 0a83 lsrs r3, r0, #10
- 8001aa4: 428b cmp r3, r1
- 8001aa6: d301 bcc.n 8001aac <__divsi3+0x88>
- 8001aa8: 028b lsls r3, r1, #10
- 8001aaa: 1ac0 subs r0, r0, r3
- 8001aac: 4152 adcs r2, r2
- 8001aae: 0a43 lsrs r3, r0, #9
- 8001ab0: 428b cmp r3, r1
- 8001ab2: d301 bcc.n 8001ab8 <__divsi3+0x94>
- 8001ab4: 024b lsls r3, r1, #9
- 8001ab6: 1ac0 subs r0, r0, r3
- 8001ab8: 4152 adcs r2, r2
- 8001aba: 0a03 lsrs r3, r0, #8
- 8001abc: 428b cmp r3, r1
- 8001abe: d301 bcc.n 8001ac4 <__divsi3+0xa0>
- 8001ac0: 020b lsls r3, r1, #8
- 8001ac2: 1ac0 subs r0, r0, r3
- 8001ac4: 4152 adcs r2, r2
- 8001ac6: d2cd bcs.n 8001a64 <__divsi3+0x40>
- 8001ac8: 09c3 lsrs r3, r0, #7
- 8001aca: 428b cmp r3, r1
- 8001acc: d301 bcc.n 8001ad2 <__divsi3+0xae>
- 8001ace: 01cb lsls r3, r1, #7
- 8001ad0: 1ac0 subs r0, r0, r3
- 8001ad2: 4152 adcs r2, r2
- 8001ad4: 0983 lsrs r3, r0, #6
- 8001ad6: 428b cmp r3, r1
- 8001ad8: d301 bcc.n 8001ade <__divsi3+0xba>
- 8001ada: 018b lsls r3, r1, #6
- 8001adc: 1ac0 subs r0, r0, r3
- 8001ade: 4152 adcs r2, r2
- 8001ae0: 0943 lsrs r3, r0, #5
- 8001ae2: 428b cmp r3, r1
- 8001ae4: d301 bcc.n 8001aea <__divsi3+0xc6>
- 8001ae6: 014b lsls r3, r1, #5
- 8001ae8: 1ac0 subs r0, r0, r3
- 8001aea: 4152 adcs r2, r2
- 8001aec: 0903 lsrs r3, r0, #4
- 8001aee: 428b cmp r3, r1
- 8001af0: d301 bcc.n 8001af6 <__divsi3+0xd2>
- 8001af2: 010b lsls r3, r1, #4
- 8001af4: 1ac0 subs r0, r0, r3
- 8001af6: 4152 adcs r2, r2
- 8001af8: 08c3 lsrs r3, r0, #3
- 8001afa: 428b cmp r3, r1
- 8001afc: d301 bcc.n 8001b02 <__divsi3+0xde>
- 8001afe: 00cb lsls r3, r1, #3
- 8001b00: 1ac0 subs r0, r0, r3
- 8001b02: 4152 adcs r2, r2
- 8001b04: 0883 lsrs r3, r0, #2
- 8001b06: 428b cmp r3, r1
- 8001b08: d301 bcc.n 8001b0e <__divsi3+0xea>
- 8001b0a: 008b lsls r3, r1, #2
- 8001b0c: 1ac0 subs r0, r0, r3
- 8001b0e: 4152 adcs r2, r2
- 8001b10: 0843 lsrs r3, r0, #1
- 8001b12: 428b cmp r3, r1
- 8001b14: d301 bcc.n 8001b1a <__divsi3+0xf6>
- 8001b16: 004b lsls r3, r1, #1
- 8001b18: 1ac0 subs r0, r0, r3
- 8001b1a: 4152 adcs r2, r2
- 8001b1c: 1a41 subs r1, r0, r1
- 8001b1e: d200 bcs.n 8001b22 <__divsi3+0xfe>
- 8001b20: 4601 mov r1, r0
- 8001b22: 4152 adcs r2, r2
- 8001b24: 4610 mov r0, r2
- 8001b26: 4770 bx lr
- 8001b28: e05d b.n 8001be6 <__divsi3+0x1c2>
- 8001b2a: 0fca lsrs r2, r1, #31
- 8001b2c: d000 beq.n 8001b30 <__divsi3+0x10c>
- 8001b2e: 4249 negs r1, r1
- 8001b30: 1003 asrs r3, r0, #32
- 8001b32: d300 bcc.n 8001b36 <__divsi3+0x112>
- 8001b34: 4240 negs r0, r0
- 8001b36: 4053 eors r3, r2
- 8001b38: 2200 movs r2, #0
- 8001b3a: 469c mov ip, r3
- 8001b3c: 0903 lsrs r3, r0, #4
- 8001b3e: 428b cmp r3, r1
- 8001b40: d32d bcc.n 8001b9e <__divsi3+0x17a>
- 8001b42: 0a03 lsrs r3, r0, #8
- 8001b44: 428b cmp r3, r1
- 8001b46: d312 bcc.n 8001b6e <__divsi3+0x14a>
- 8001b48: 22fc movs r2, #252 ; 0xfc
- 8001b4a: 0189 lsls r1, r1, #6
- 8001b4c: ba12 rev r2, r2
- 8001b4e: 0a03 lsrs r3, r0, #8
- 8001b50: 428b cmp r3, r1
- 8001b52: d30c bcc.n 8001b6e <__divsi3+0x14a>
- 8001b54: 0189 lsls r1, r1, #6
- 8001b56: 1192 asrs r2, r2, #6
- 8001b58: 428b cmp r3, r1
- 8001b5a: d308 bcc.n 8001b6e <__divsi3+0x14a>
- 8001b5c: 0189 lsls r1, r1, #6
- 8001b5e: 1192 asrs r2, r2, #6
+ 8001a42: d301 bcc.n 8001a48 <__divsi3+0x4c>
+ 8001a44: 03cb lsls r3, r1, #15
+ 8001a46: 1ac0 subs r0, r0, r3
+ 8001a48: 4152 adcs r2, r2
+ 8001a4a: 0b83 lsrs r3, r0, #14
+ 8001a4c: 428b cmp r3, r1
+ 8001a4e: d301 bcc.n 8001a54 <__divsi3+0x58>
+ 8001a50: 038b lsls r3, r1, #14
+ 8001a52: 1ac0 subs r0, r0, r3
+ 8001a54: 4152 adcs r2, r2
+ 8001a56: 0b43 lsrs r3, r0, #13
+ 8001a58: 428b cmp r3, r1
+ 8001a5a: d301 bcc.n 8001a60 <__divsi3+0x64>
+ 8001a5c: 034b lsls r3, r1, #13
+ 8001a5e: 1ac0 subs r0, r0, r3
+ 8001a60: 4152 adcs r2, r2
+ 8001a62: 0b03 lsrs r3, r0, #12
+ 8001a64: 428b cmp r3, r1
+ 8001a66: d301 bcc.n 8001a6c <__divsi3+0x70>
+ 8001a68: 030b lsls r3, r1, #12
+ 8001a6a: 1ac0 subs r0, r0, r3
+ 8001a6c: 4152 adcs r2, r2
+ 8001a6e: 0ac3 lsrs r3, r0, #11
+ 8001a70: 428b cmp r3, r1
+ 8001a72: d301 bcc.n 8001a78 <__divsi3+0x7c>
+ 8001a74: 02cb lsls r3, r1, #11
+ 8001a76: 1ac0 subs r0, r0, r3
+ 8001a78: 4152 adcs r2, r2
+ 8001a7a: 0a83 lsrs r3, r0, #10
+ 8001a7c: 428b cmp r3, r1
+ 8001a7e: d301 bcc.n 8001a84 <__divsi3+0x88>
+ 8001a80: 028b lsls r3, r1, #10
+ 8001a82: 1ac0 subs r0, r0, r3
+ 8001a84: 4152 adcs r2, r2
+ 8001a86: 0a43 lsrs r3, r0, #9
+ 8001a88: 428b cmp r3, r1
+ 8001a8a: d301 bcc.n 8001a90 <__divsi3+0x94>
+ 8001a8c: 024b lsls r3, r1, #9
+ 8001a8e: 1ac0 subs r0, r0, r3
+ 8001a90: 4152 adcs r2, r2
+ 8001a92: 0a03 lsrs r3, r0, #8
+ 8001a94: 428b cmp r3, r1
+ 8001a96: d301 bcc.n 8001a9c <__divsi3+0xa0>
+ 8001a98: 020b lsls r3, r1, #8
+ 8001a9a: 1ac0 subs r0, r0, r3
+ 8001a9c: 4152 adcs r2, r2
+ 8001a9e: d2cd bcs.n 8001a3c <__divsi3+0x40>
+ 8001aa0: 09c3 lsrs r3, r0, #7
+ 8001aa2: 428b cmp r3, r1
+ 8001aa4: d301 bcc.n 8001aaa <__divsi3+0xae>
+ 8001aa6: 01cb lsls r3, r1, #7
+ 8001aa8: 1ac0 subs r0, r0, r3
+ 8001aaa: 4152 adcs r2, r2
+ 8001aac: 0983 lsrs r3, r0, #6
+ 8001aae: 428b cmp r3, r1
+ 8001ab0: d301 bcc.n 8001ab6 <__divsi3+0xba>
+ 8001ab2: 018b lsls r3, r1, #6
+ 8001ab4: 1ac0 subs r0, r0, r3
+ 8001ab6: 4152 adcs r2, r2
+ 8001ab8: 0943 lsrs r3, r0, #5
+ 8001aba: 428b cmp r3, r1
+ 8001abc: d301 bcc.n 8001ac2 <__divsi3+0xc6>
+ 8001abe: 014b lsls r3, r1, #5
+ 8001ac0: 1ac0 subs r0, r0, r3
+ 8001ac2: 4152 adcs r2, r2
+ 8001ac4: 0903 lsrs r3, r0, #4
+ 8001ac6: 428b cmp r3, r1
+ 8001ac8: d301 bcc.n 8001ace <__divsi3+0xd2>
+ 8001aca: 010b lsls r3, r1, #4
+ 8001acc: 1ac0 subs r0, r0, r3
+ 8001ace: 4152 adcs r2, r2
+ 8001ad0: 08c3 lsrs r3, r0, #3
+ 8001ad2: 428b cmp r3, r1
+ 8001ad4: d301 bcc.n 8001ada <__divsi3+0xde>
+ 8001ad6: 00cb lsls r3, r1, #3
+ 8001ad8: 1ac0 subs r0, r0, r3
+ 8001ada: 4152 adcs r2, r2
+ 8001adc: 0883 lsrs r3, r0, #2
+ 8001ade: 428b cmp r3, r1
+ 8001ae0: d301 bcc.n 8001ae6 <__divsi3+0xea>
+ 8001ae2: 008b lsls r3, r1, #2
+ 8001ae4: 1ac0 subs r0, r0, r3
+ 8001ae6: 4152 adcs r2, r2
+ 8001ae8: 0843 lsrs r3, r0, #1
+ 8001aea: 428b cmp r3, r1
+ 8001aec: d301 bcc.n 8001af2 <__divsi3+0xf6>
+ 8001aee: 004b lsls r3, r1, #1
+ 8001af0: 1ac0 subs r0, r0, r3
+ 8001af2: 4152 adcs r2, r2
+ 8001af4: 1a41 subs r1, r0, r1
+ 8001af6: d200 bcs.n 8001afa <__divsi3+0xfe>
+ 8001af8: 4601 mov r1, r0
+ 8001afa: 4152 adcs r2, r2
+ 8001afc: 4610 mov r0, r2
+ 8001afe: 4770 bx lr
+ 8001b00: e05d b.n 8001bbe <__divsi3+0x1c2>
+ 8001b02: 0fca lsrs r2, r1, #31
+ 8001b04: d000 beq.n 8001b08 <__divsi3+0x10c>
+ 8001b06: 4249 negs r1, r1
+ 8001b08: 1003 asrs r3, r0, #32
+ 8001b0a: d300 bcc.n 8001b0e <__divsi3+0x112>
+ 8001b0c: 4240 negs r0, r0
+ 8001b0e: 4053 eors r3, r2
+ 8001b10: 2200 movs r2, #0
+ 8001b12: 469c mov ip, r3
+ 8001b14: 0903 lsrs r3, r0, #4
+ 8001b16: 428b cmp r3, r1
+ 8001b18: d32d bcc.n 8001b76 <__divsi3+0x17a>
+ 8001b1a: 0a03 lsrs r3, r0, #8
+ 8001b1c: 428b cmp r3, r1
+ 8001b1e: d312 bcc.n 8001b46 <__divsi3+0x14a>
+ 8001b20: 22fc movs r2, #252 ; 0xfc
+ 8001b22: 0189 lsls r1, r1, #6
+ 8001b24: ba12 rev r2, r2
+ 8001b26: 0a03 lsrs r3, r0, #8
+ 8001b28: 428b cmp r3, r1
+ 8001b2a: d30c bcc.n 8001b46 <__divsi3+0x14a>
+ 8001b2c: 0189 lsls r1, r1, #6
+ 8001b2e: 1192 asrs r2, r2, #6
+ 8001b30: 428b cmp r3, r1
+ 8001b32: d308 bcc.n 8001b46 <__divsi3+0x14a>
+ 8001b34: 0189 lsls r1, r1, #6
+ 8001b36: 1192 asrs r2, r2, #6
+ 8001b38: 428b cmp r3, r1
+ 8001b3a: d304 bcc.n 8001b46 <__divsi3+0x14a>
+ 8001b3c: 0189 lsls r1, r1, #6
+ 8001b3e: d03a beq.n 8001bb6 <__divsi3+0x1ba>
+ 8001b40: 1192 asrs r2, r2, #6
+ 8001b42: e000 b.n 8001b46 <__divsi3+0x14a>
+ 8001b44: 0989 lsrs r1, r1, #6
+ 8001b46: 09c3 lsrs r3, r0, #7
+ 8001b48: 428b cmp r3, r1
+ 8001b4a: d301 bcc.n 8001b50 <__divsi3+0x154>
+ 8001b4c: 01cb lsls r3, r1, #7
+ 8001b4e: 1ac0 subs r0, r0, r3
+ 8001b50: 4152 adcs r2, r2
+ 8001b52: 0983 lsrs r3, r0, #6
+ 8001b54: 428b cmp r3, r1
+ 8001b56: d301 bcc.n 8001b5c <__divsi3+0x160>
+ 8001b58: 018b lsls r3, r1, #6
+ 8001b5a: 1ac0 subs r0, r0, r3
+ 8001b5c: 4152 adcs r2, r2
+ 8001b5e: 0943 lsrs r3, r0, #5
8001b60: 428b cmp r3, r1
- 8001b62: d304 bcc.n 8001b6e <__divsi3+0x14a>
- 8001b64: 0189 lsls r1, r1, #6
- 8001b66: d03a beq.n 8001bde <__divsi3+0x1ba>
- 8001b68: 1192 asrs r2, r2, #6
- 8001b6a: e000 b.n 8001b6e <__divsi3+0x14a>
- 8001b6c: 0989 lsrs r1, r1, #6
- 8001b6e: 09c3 lsrs r3, r0, #7
- 8001b70: 428b cmp r3, r1
- 8001b72: d301 bcc.n 8001b78 <__divsi3+0x154>
- 8001b74: 01cb lsls r3, r1, #7
- 8001b76: 1ac0 subs r0, r0, r3
- 8001b78: 4152 adcs r2, r2
- 8001b7a: 0983 lsrs r3, r0, #6
- 8001b7c: 428b cmp r3, r1
- 8001b7e: d301 bcc.n 8001b84 <__divsi3+0x160>
- 8001b80: 018b lsls r3, r1, #6
- 8001b82: 1ac0 subs r0, r0, r3
- 8001b84: 4152 adcs r2, r2
- 8001b86: 0943 lsrs r3, r0, #5
- 8001b88: 428b cmp r3, r1
- 8001b8a: d301 bcc.n 8001b90 <__divsi3+0x16c>
- 8001b8c: 014b lsls r3, r1, #5
- 8001b8e: 1ac0 subs r0, r0, r3
- 8001b90: 4152 adcs r2, r2
- 8001b92: 0903 lsrs r3, r0, #4
- 8001b94: 428b cmp r3, r1
- 8001b96: d301 bcc.n 8001b9c <__divsi3+0x178>
- 8001b98: 010b lsls r3, r1, #4
- 8001b9a: 1ac0 subs r0, r0, r3
- 8001b9c: 4152 adcs r2, r2
- 8001b9e: 08c3 lsrs r3, r0, #3
- 8001ba0: 428b cmp r3, r1
- 8001ba2: d301 bcc.n 8001ba8 <__divsi3+0x184>
- 8001ba4: 00cb lsls r3, r1, #3
- 8001ba6: 1ac0 subs r0, r0, r3
- 8001ba8: 4152 adcs r2, r2
- 8001baa: 0883 lsrs r3, r0, #2
- 8001bac: 428b cmp r3, r1
- 8001bae: d301 bcc.n 8001bb4 <__divsi3+0x190>
- 8001bb0: 008b lsls r3, r1, #2
- 8001bb2: 1ac0 subs r0, r0, r3
- 8001bb4: 4152 adcs r2, r2
- 8001bb6: d2d9 bcs.n 8001b6c <__divsi3+0x148>
- 8001bb8: 0843 lsrs r3, r0, #1
- 8001bba: 428b cmp r3, r1
- 8001bbc: d301 bcc.n 8001bc2 <__divsi3+0x19e>
- 8001bbe: 004b lsls r3, r1, #1
- 8001bc0: 1ac0 subs r0, r0, r3
- 8001bc2: 4152 adcs r2, r2
- 8001bc4: 1a41 subs r1, r0, r1
- 8001bc6: d200 bcs.n 8001bca <__divsi3+0x1a6>
- 8001bc8: 4601 mov r1, r0
- 8001bca: 4663 mov r3, ip
- 8001bcc: 4152 adcs r2, r2
- 8001bce: 105b asrs r3, r3, #1
- 8001bd0: 4610 mov r0, r2
- 8001bd2: d301 bcc.n 8001bd8 <__divsi3+0x1b4>
- 8001bd4: 4240 negs r0, r0
- 8001bd6: 2b00 cmp r3, #0
- 8001bd8: d500 bpl.n 8001bdc <__divsi3+0x1b8>
- 8001bda: 4249 negs r1, r1
- 8001bdc: 4770 bx lr
- 8001bde: 4663 mov r3, ip
- 8001be0: 105b asrs r3, r3, #1
- 8001be2: d300 bcc.n 8001be6 <__divsi3+0x1c2>
- 8001be4: 4240 negs r0, r0
- 8001be6: b501 push {r0, lr}
- 8001be8: 2000 movs r0, #0
- 8001bea: f000 f805 bl 8001bf8 <__aeabi_idiv0>
- 8001bee: bd02 pop {r1, pc}
-
-08001bf0 <__aeabi_idivmod>:
- 8001bf0: 2900 cmp r1, #0
- 8001bf2: d0f8 beq.n 8001be6 <__divsi3+0x1c2>
- 8001bf4: e716 b.n 8001a24 <__divsi3>
- 8001bf6: 4770 bx lr
-
-08001bf8 <__aeabi_idiv0>:
- 8001bf8: 4770 bx lr
- 8001bfa: 46c0 nop ; (mov r8, r8)
-
-08001bfc <Reset_Handler>:
+ 8001b62: d301 bcc.n 8001b68 <__divsi3+0x16c>
+ 8001b64: 014b lsls r3, r1, #5
+ 8001b66: 1ac0 subs r0, r0, r3
+ 8001b68: 4152 adcs r2, r2
+ 8001b6a: 0903 lsrs r3, r0, #4
+ 8001b6c: 428b cmp r3, r1
+ 8001b6e: d301 bcc.n 8001b74 <__divsi3+0x178>
+ 8001b70: 010b lsls r3, r1, #4
+ 8001b72: 1ac0 subs r0, r0, r3
+ 8001b74: 4152 adcs r2, r2
+ 8001b76: 08c3 lsrs r3, r0, #3
+ 8001b78: 428b cmp r3, r1
+ 8001b7a: d301 bcc.n 8001b80 <__divsi3+0x184>
+ 8001b7c: 00cb lsls r3, r1, #3
+ 8001b7e: 1ac0 subs r0, r0, r3
+ 8001b80: 4152 adcs r2, r2
+ 8001b82: 0883 lsrs r3, r0, #2
+ 8001b84: 428b cmp r3, r1
+ 8001b86: d301 bcc.n 8001b8c <__divsi3+0x190>
+ 8001b88: 008b lsls r3, r1, #2
+ 8001b8a: 1ac0 subs r0, r0, r3
+ 8001b8c: 4152 adcs r2, r2
+ 8001b8e: d2d9 bcs.n 8001b44 <__divsi3+0x148>
+ 8001b90: 0843 lsrs r3, r0, #1
+ 8001b92: 428b cmp r3, r1
+ 8001b94: d301 bcc.n 8001b9a <__divsi3+0x19e>
+ 8001b96: 004b lsls r3, r1, #1
+ 8001b98: 1ac0 subs r0, r0, r3
+ 8001b9a: 4152 adcs r2, r2
+ 8001b9c: 1a41 subs r1, r0, r1
+ 8001b9e: d200 bcs.n 8001ba2 <__divsi3+0x1a6>
+ 8001ba0: 4601 mov r1, r0
+ 8001ba2: 4663 mov r3, ip
+ 8001ba4: 4152 adcs r2, r2
+ 8001ba6: 105b asrs r3, r3, #1
+ 8001ba8: 4610 mov r0, r2
+ 8001baa: d301 bcc.n 8001bb0 <__divsi3+0x1b4>
+ 8001bac: 4240 negs r0, r0
+ 8001bae: 2b00 cmp r3, #0
+ 8001bb0: d500 bpl.n 8001bb4 <__divsi3+0x1b8>
+ 8001bb2: 4249 negs r1, r1
+ 8001bb4: 4770 bx lr
+ 8001bb6: 4663 mov r3, ip
+ 8001bb8: 105b asrs r3, r3, #1
+ 8001bba: d300 bcc.n 8001bbe <__divsi3+0x1c2>
+ 8001bbc: 4240 negs r0, r0
+ 8001bbe: b501 push {r0, lr}
+ 8001bc0: 2000 movs r0, #0
+ 8001bc2: f000 f805 bl 8001bd0 <__aeabi_idiv0>
+ 8001bc6: bd02 pop {r1, pc}
+
+08001bc8 <__aeabi_idivmod>:
+ 8001bc8: 2900 cmp r1, #0
+ 8001bca: d0f8 beq.n 8001bbe <__divsi3+0x1c2>
+ 8001bcc: e716 b.n 80019fc <__divsi3>
+ 8001bce: 4770 bx lr
+
+08001bd0 <__aeabi_idiv0>:
+ 8001bd0: 4770 bx lr
+ 8001bd2: 46c0 nop ; (mov r8, r8)
+
+08001bd4 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
- 8001bfc: 480c ldr r0, [pc, #48] ; (8001c30 <LoopForever+0x2>)
+ 8001bd4: 480c ldr r0, [pc, #48] ; (8001c08 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
- 8001bfe: 4685 mov sp, r0
+ 8001bd6: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 8001c00: 2100 movs r1, #0
+ 8001bd8: 2100 movs r1, #0
b LoopCopyDataInit
- 8001c02: e003 b.n 8001c0c <LoopCopyDataInit>
+ 8001bda: e003 b.n 8001be4 <LoopCopyDataInit>
-08001c04 <CopyDataInit>:
+08001bdc <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 8001c04: 4b0b ldr r3, [pc, #44] ; (8001c34 <LoopForever+0x6>)
+ 8001bdc: 4b0b ldr r3, [pc, #44] ; (8001c0c <LoopForever+0x6>)
ldr r3, [r3, r1]
- 8001c06: 585b ldr r3, [r3, r1]
+ 8001bde: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 8001c08: 5043 str r3, [r0, r1]
+ 8001be0: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 8001c0a: 3104 adds r1, #4
+ 8001be2: 3104 adds r1, #4
-08001c0c <LoopCopyDataInit>:
+08001be4 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 8001c0c: 480a ldr r0, [pc, #40] ; (8001c38 <LoopForever+0xa>)
+ 8001be4: 480a ldr r0, [pc, #40] ; (8001c10 <LoopForever+0xa>)
ldr r3, =_edata
- 8001c0e: 4b0b ldr r3, [pc, #44] ; (8001c3c <LoopForever+0xe>)
+ 8001be6: 4b0b ldr r3, [pc, #44] ; (8001c14 <LoopForever+0xe>)
adds r2, r0, r1
- 8001c10: 1842 adds r2, r0, r1
+ 8001be8: 1842 adds r2, r0, r1
cmp r2, r3
- 8001c12: 429a cmp r2, r3
+ 8001bea: 429a cmp r2, r3
bcc CopyDataInit
- 8001c14: d3f6 bcc.n 8001c04 <CopyDataInit>
+ 8001bec: d3f6 bcc.n 8001bdc <CopyDataInit>
ldr r2, =_sbss
- 8001c16: 4a0a ldr r2, [pc, #40] ; (8001c40 <LoopForever+0x12>)
+ 8001bee: 4a0a ldr r2, [pc, #40] ; (8001c18 <LoopForever+0x12>)
b LoopFillZerobss
- 8001c18: e002 b.n 8001c20 <LoopFillZerobss>
+ 8001bf0: e002 b.n 8001bf8 <LoopFillZerobss>
-08001c1a <FillZerobss>:
+08001bf2 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 8001c1a: 2300 movs r3, #0
+ 8001bf2: 2300 movs r3, #0
str r3, [r2]
- 8001c1c: 6013 str r3, [r2, #0]
+ 8001bf4: 6013 str r3, [r2, #0]
adds r2, r2, #4
- 8001c1e: 3204 adds r2, #4
+ 8001bf6: 3204 adds r2, #4
-08001c20 <LoopFillZerobss>:
+08001bf8 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 8001c20: 4b08 ldr r3, [pc, #32] ; (8001c44 <LoopForever+0x16>)
+ 8001bf8: 4b08 ldr r3, [pc, #32] ; (8001c1c <LoopForever+0x16>)
cmp r2, r3
- 8001c22: 429a cmp r2, r3
+ 8001bfa: 429a cmp r2, r3
bcc FillZerobss
- 8001c24: d3f9 bcc.n 8001c1a <FillZerobss>
+ 8001bfc: d3f9 bcc.n 8001bf2 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
- 8001c26: f7ff faad bl 8001184 <SystemInit>
+ 8001bfe: f7ff faad bl 800115c <SystemInit>
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/
bl main
- 8001c2a: f7fe faf6 bl 800021a <main>
+ 8001c02: f7fe fb0a bl 800021a <main>
-08001c2e <LoopForever>:
+08001c06 <LoopForever>:
LoopForever:
b LoopForever
- 8001c2e: e7fe b.n 8001c2e <LoopForever>
+ 8001c06: e7fe b.n 8001c06 <LoopForever>
ldr r0, =_estack
- 8001c30: 20001000 .word 0x20001000
+ 8001c08: 20001000 .word 0x20001000
ldr r3, =_sidata
- 8001c34: 08001c64 .word 0x08001c64
+ 8001c0c: 08001c3c .word 0x08001c3c
ldr r0, =_sdata
- 8001c38: 20000000 .word 0x20000000
+ 8001c10: 20000000 .word 0x20000000
ldr r3, =_edata
- 8001c3c: 20000094 .word 0x20000094
+ 8001c14: 20000094 .word 0x20000094
ldr r2, =_sbss
- 8001c40: 20000094 .word 0x20000094
+ 8001c18: 20000094 .word 0x20000094
ldr r3, = _ebss
- 8001c44: 200003b8 .word 0x200003b8
+ 8001c1c: 200003d4 .word 0x200003d4
-08001c48 <ADC1_IRQHandler>:
+08001c20 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 8001c48: e7fe b.n 8001c48 <ADC1_IRQHandler>
+ 8001c20: e7fe b.n 8001c20 <ADC1_IRQHandler>
...
-08001c4c <AHBPrescTable>:
+08001c24 <AHBPrescTable>:
...
- 8001c54: 0201 0403 0706 0908 ........
+ 8001c2c: 0201 0403 0706 0908 ........
-08001c5c <APBPrescTable>:
- 8001c5c: 0000 0000 0201 0403 ........
+08001c34 <APBPrescTable>:
+ 8001c34: 0000 0000 0201 0403 ........
diff --git a/gm_platform/fw/main.map b/gm_platform/fw/main.map
index 3260f49..7147bfe 100644
--- a/gm_platform/fw/main.map
+++ b/gm_platform/fw/main.map
@@ -1,17 +1,17 @@
Archive member included to satisfy reference by file (symbol)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- /tmp/ccy8OCeb.o (__aeabi_uidiv)
+ /tmp/cce3buMD.o (__aeabi_uidiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- /tmp/cc6Un0Q5.o (__aeabi_idiv)
+ /tmp/ccC4L2qX.o (__aeabi_idiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
Allocating common symbols
Common symbol size file
-usart_tx_buf 0x220 /tmp/ccRRCPG0.o
-leds 0x20 /tmp/ccy8OCeb.o
+usart_tx_buf 0x23c /tmp/ccTkGJkh.o
+leds 0x20 /tmp/cce3buMD.o
Memory Configuration
@@ -24,29 +24,29 @@ RAM 0x0000000020000000 0x0000000000001000 xrw
Linker script and memory map
LOAD /home/user/resource/STM32CubeF0/Drivers/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
-LOAD /tmp/ccy8OCeb.o
-LOAD /tmp/cc6Un0Q5.o
-LOAD /tmp/ccRRCPG0.o
-LOAD /tmp/ccWI4kHV.o
-LOAD /tmp/ccjaIjJQ.o
-LOAD /tmp/cceYjaVL.o
-LOAD /tmp/ccsXJViH.o
-LOAD /tmp/ccGz0VMC.o
-LOAD /tmp/ccy5lZmy.o
+LOAD /tmp/cce3buMD.o
+LOAD /tmp/ccC4L2qX.o
+LOAD /tmp/ccTkGJkh.o
+LOAD /tmp/ccLc8YqB.o
+LOAD /tmp/ccNO0bzV.o
+LOAD /tmp/ccyL94Of.o
+LOAD /tmp/ccHrpyiA.o
+LOAD /tmp/ccek4wTU.o
+LOAD /tmp/ccm7EkDf.o
LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020001000 _estack = 0x20001000
.isr_vector 0x0000000008000000 0xc0
0x0000000008000000 . = ALIGN (0x4)
*(.isr_vector)
- .isr_vector 0x0000000008000000 0xc0 /tmp/ccjaIjJQ.o
+ .isr_vector 0x0000000008000000 0xc0 /tmp/ccNO0bzV.o
0x0000000008000000 g_pfnVectors
0x00000000080000c0 . = ALIGN (0x4)
-.text 0x00000000080000c0 0x1ba4
+.text 0x00000000080000c0 0x1b7c
0x00000000080000c0 . = ALIGN (0x4)
*(.text)
- .text 0x00000000080000c0 0x428 /tmp/ccy8OCeb.o
+ .text 0x00000000080000c0 0x428 /tmp/cce3buMD.o
0x0000000008000210 update_leds
0x000000000800021a main
0x000000000800039c SPI1_IRQHandler
@@ -56,118 +56,118 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000008000494 SVC_Handler
0x00000000080004a0 PendSV_Handler
0x00000000080004ac SysTick_Handler
- .text 0x00000000080004e8 0x334 /tmp/cc6Un0Q5.o
+ .text 0x00000000080004e8 0x334 /tmp/ccC4L2qX.o
0x00000000080005f0 adc_configure_scope_mode
0x000000000800079a DMA1_Channel1_IRQHandler
- .text 0x000000000800081c 0x6c0 /tmp/ccRRCPG0.o
+ .text 0x000000000800081c 0x698 /tmp/ccTkGJkh.o
0x0000000008000954 usart_dma_init
- 0x0000000008000a28 USART1_IRQHandler
- 0x0000000008000bc4 usart_ack_packet
- 0x0000000008000c00 usart_dma_fifo_push
- 0x0000000008000c78 usart_putc
- 0x0000000008000cd0 DMA1_Channel2_3_IRQHandler
- 0x0000000008000dbc usart_send_packet_nonblocking
- .text 0x0000000008000edc 0x292 /tmp/ccWI4kHV.o
- 0x0000000008000edc cobs_encode_usart
- 0x0000000008000f9a cobs_decode
- 0x0000000008001070 cobs_decode_incremental_initialize
- 0x000000000800108c cobs_decode_incremental
- .text 0x000000000800116e 0x14 /tmp/ccjaIjJQ.o
- *fill* 0x0000000008001182 0x2
- .text 0x0000000008001184 0x174 /tmp/cceYjaVL.o
- 0x0000000008001184 SystemInit
- 0x000000000800120c SystemCoreClockUpdate
- .text 0x00000000080012f8 0x594 /tmp/ccsXJViH.o
- 0x000000000800154c LL_Init1msTick
- 0x000000000800156a LL_mDelay
- 0x00000000080015b0 LL_SetSystemCoreClock
- 0x00000000080015cc LL_PLL_ConfigSystemClock_HSI
- 0x0000000008001658 LL_PLL_ConfigSystemClock_HSE
- .text 0x000000000800188c 0x82 /tmp/ccGz0VMC.o
- 0x000000000800188c __sinit
- 0x0000000008001896 memset
- 0x00000000080018d0 strlen
- 0x00000000080018fa __assert_func
- .text 0x000000000800190e 0x0 /tmp/ccy5lZmy.o
- *fill* 0x000000000800190e 0x2
- .text 0x0000000008001910 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- 0x0000000008001910 __udivsi3
- 0x0000000008001910 __aeabi_uidiv
- 0x0000000008001a1c __aeabi_uidivmod
- .text 0x0000000008001a24 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- 0x0000000008001a24 __aeabi_idiv
- 0x0000000008001a24 __divsi3
- 0x0000000008001bf0 __aeabi_idivmod
- .text 0x0000000008001bf8 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
- 0x0000000008001bf8 __aeabi_ldiv0
- 0x0000000008001bf8 __aeabi_idiv0
+ 0x0000000008000a40 USART1_IRQHandler
+ 0x0000000008000c38 usart_ack_packet
+ 0x0000000008000c98 usart_dma_fifo_push
+ 0x0000000008000cf4 usart_putc
+ 0x0000000008000d4c DMA1_Channel2_3_IRQHandler
+ 0x0000000008000d90 usart_send_packet_nonblocking
+ .text 0x0000000008000eb4 0x292 /tmp/ccLc8YqB.o
+ 0x0000000008000eb4 cobs_encode_usart
+ 0x0000000008000f72 cobs_decode
+ 0x0000000008001048 cobs_decode_incremental_initialize
+ 0x0000000008001064 cobs_decode_incremental
+ .text 0x0000000008001146 0x14 /tmp/ccNO0bzV.o
+ *fill* 0x000000000800115a 0x2
+ .text 0x000000000800115c 0x174 /tmp/ccyL94Of.o
+ 0x000000000800115c SystemInit
+ 0x00000000080011e4 SystemCoreClockUpdate
+ .text 0x00000000080012d0 0x594 /tmp/ccHrpyiA.o
+ 0x0000000008001524 LL_Init1msTick
+ 0x0000000008001542 LL_mDelay
+ 0x0000000008001588 LL_SetSystemCoreClock
+ 0x00000000080015a4 LL_PLL_ConfigSystemClock_HSI
+ 0x0000000008001630 LL_PLL_ConfigSystemClock_HSE
+ .text 0x0000000008001864 0x82 /tmp/ccek4wTU.o
+ 0x0000000008001864 __sinit
+ 0x000000000800186e memset
+ 0x00000000080018a8 strlen
+ 0x00000000080018d2 __assert_func
+ .text 0x00000000080018e6 0x0 /tmp/ccm7EkDf.o
+ *fill* 0x00000000080018e6 0x2
+ .text 0x00000000080018e8 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ 0x00000000080018e8 __udivsi3
+ 0x00000000080018e8 __aeabi_uidiv
+ 0x00000000080019f4 __aeabi_uidivmod
+ .text 0x00000000080019fc 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ 0x00000000080019fc __aeabi_idiv
+ 0x00000000080019fc __divsi3
+ 0x0000000008001bc8 __aeabi_idivmod
+ .text 0x0000000008001bd0 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ 0x0000000008001bd0 __aeabi_ldiv0
+ 0x0000000008001bd0 __aeabi_idiv0
*(.text.*)
.text.Reset_Handler
- 0x0000000008001bfc 0x4c /tmp/ccjaIjJQ.o
- 0x0000000008001bfc Reset_Handler
+ 0x0000000008001bd4 0x4c /tmp/ccNO0bzV.o
+ 0x0000000008001bd4 Reset_Handler
.text.Default_Handler
- 0x0000000008001c48 0x2 /tmp/ccjaIjJQ.o
- 0x0000000008001c48 TIM1_CC_IRQHandler
- 0x0000000008001c48 I2C1_IRQHandler
- 0x0000000008001c48 EXTI2_3_IRQHandler
- 0x0000000008001c48 ADC1_IRQHandler
- 0x0000000008001c48 TIM17_IRQHandler
- 0x0000000008001c48 RTC_IRQHandler
- 0x0000000008001c48 TIM3_IRQHandler
- 0x0000000008001c48 EXTI4_15_IRQHandler
- 0x0000000008001c48 RCC_IRQHandler
- 0x0000000008001c48 Default_Handler
- 0x0000000008001c48 TIM14_IRQHandler
- 0x0000000008001c48 DMA1_Channel4_5_IRQHandler
- 0x0000000008001c48 EXTI0_1_IRQHandler
- 0x0000000008001c48 WWDG_IRQHandler
- 0x0000000008001c48 FLASH_IRQHandler
- 0x0000000008001c48 TIM1_BRK_UP_TRG_COM_IRQHandler
+ 0x0000000008001c20 0x2 /tmp/ccNO0bzV.o
+ 0x0000000008001c20 TIM1_CC_IRQHandler
+ 0x0000000008001c20 I2C1_IRQHandler
+ 0x0000000008001c20 EXTI2_3_IRQHandler
+ 0x0000000008001c20 ADC1_IRQHandler
+ 0x0000000008001c20 TIM17_IRQHandler
+ 0x0000000008001c20 RTC_IRQHandler
+ 0x0000000008001c20 TIM3_IRQHandler
+ 0x0000000008001c20 EXTI4_15_IRQHandler
+ 0x0000000008001c20 RCC_IRQHandler
+ 0x0000000008001c20 Default_Handler
+ 0x0000000008001c20 TIM14_IRQHandler
+ 0x0000000008001c20 DMA1_Channel4_5_IRQHandler
+ 0x0000000008001c20 EXTI0_1_IRQHandler
+ 0x0000000008001c20 WWDG_IRQHandler
+ 0x0000000008001c20 FLASH_IRQHandler
+ 0x0000000008001c20 TIM1_BRK_UP_TRG_COM_IRQHandler
*(.rodata)
- *fill* 0x0000000008001c4a 0x2
- .rodata 0x0000000008001c4c 0x18 /tmp/cceYjaVL.o
- 0x0000000008001c4c AHBPrescTable
- 0x0000000008001c5c APBPrescTable
+ *fill* 0x0000000008001c22 0x2
+ .rodata 0x0000000008001c24 0x18 /tmp/ccyL94Of.o
+ 0x0000000008001c24 AHBPrescTable
+ 0x0000000008001c34 APBPrescTable
*(.rodata*)
*(.glue_7)
- .glue_7 0x0000000008001c64 0x0 linker stubs
+ .glue_7 0x0000000008001c3c 0x0 linker stubs
*(.glue_7t)
- .glue_7t 0x0000000008001c64 0x0 linker stubs
+ .glue_7t 0x0000000008001c3c 0x0 linker stubs
*(.source_tarball)
*(.init)
*(.fini)
*(.source_tarball)
- 0x0000000008001c64 . = ALIGN (0x4)
- 0x0000000008001c64 _etext = .
- 0x0000000008001c64 _sidata = _etext
+ 0x0000000008001c3c . = ALIGN (0x4)
+ 0x0000000008001c3c _etext = .
+ 0x0000000008001c3c _sidata = _etext
-.vfp11_veneer 0x0000000008001c64 0x0
- .vfp11_veneer 0x0000000008001c64 0x0 linker stubs
+.vfp11_veneer 0x0000000008001c3c 0x0
+ .vfp11_veneer 0x0000000008001c3c 0x0 linker stubs
-.v4_bx 0x0000000008001c64 0x0
- .v4_bx 0x0000000008001c64 0x0 linker stubs
+.v4_bx 0x0000000008001c3c 0x0
+ .v4_bx 0x0000000008001c3c 0x0 linker stubs
-.iplt 0x0000000008001c64 0x0
- .iplt 0x0000000008001c64 0x0 /tmp/ccy8OCeb.o
+.iplt 0x0000000008001c3c 0x0
+ .iplt 0x0000000008001c3c 0x0 /tmp/cce3buMD.o
-.rel.dyn 0x0000000008001c64 0x0
- .rel.iplt 0x0000000008001c64 0x0 /tmp/ccy8OCeb.o
+.rel.dyn 0x0000000008001c3c 0x0
+ .rel.iplt 0x0000000008001c3c 0x0 /tmp/cce3buMD.o
-.data 0x0000000020000000 0x94 load address 0x0000000008001c64
+.data 0x0000000020000000 0x94 load address 0x0000000008001c3c
0x0000000020000000 . = ALIGN (0x4)
0x0000000020000000 _sdata = .
0x0000000020000000 _data = .
*(.data)
- .data 0x0000000020000000 0x0 /tmp/ccy8OCeb.o
- .data 0x0000000020000000 0x0 /tmp/cc6Un0Q5.o
- .data 0x0000000020000000 0x0 /tmp/ccRRCPG0.o
- .data 0x0000000020000000 0x0 /tmp/ccWI4kHV.o
- .data 0x0000000020000000 0x0 /tmp/ccjaIjJQ.o
- .data 0x0000000020000000 0x4 /tmp/cceYjaVL.o
+ .data 0x0000000020000000 0x0 /tmp/cce3buMD.o
+ .data 0x0000000020000000 0x0 /tmp/ccC4L2qX.o
+ .data 0x0000000020000000 0x0 /tmp/ccTkGJkh.o
+ .data 0x0000000020000000 0x0 /tmp/ccLc8YqB.o
+ .data 0x0000000020000000 0x0 /tmp/ccNO0bzV.o
+ .data 0x0000000020000000 0x4 /tmp/ccyL94Of.o
0x0000000020000000 SystemCoreClock
- .data 0x0000000020000004 0x0 /tmp/ccsXJViH.o
- .data 0x0000000020000004 0x0 /tmp/ccGz0VMC.o
- .data 0x0000000020000004 0x90 /tmp/ccy5lZmy.o
+ .data 0x0000000020000004 0x0 /tmp/ccHrpyiA.o
+ .data 0x0000000020000004 0x0 /tmp/ccek4wTU.o
+ .data 0x0000000020000004 0x90 /tmp/ccm7EkDf.o
0x0000000020000004 tim3
0x0000000020000008 tim14
0x000000002000000c rtc
@@ -212,41 +212,41 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _edata = .
-.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001cf8
- .igot.plt 0x0000000020000094 0x0 /tmp/ccy8OCeb.o
+.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001cd0
+ .igot.plt 0x0000000020000094 0x0 /tmp/cce3buMD.o
-.bss 0x0000000020000094 0x324 load address 0x0000000008001cf8
+.bss 0x0000000020000094 0x340 load address 0x0000000008001cd0
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _sbss = .
0x0000000020000094 _bss = .
*(.bss)
- .bss 0x0000000020000094 0xc /tmp/ccy8OCeb.o
+ .bss 0x0000000020000094 0xc /tmp/cce3buMD.o
0x0000000020000094 sys_time_seconds
- .bss 0x00000000200000a0 0x98 /tmp/cc6Un0Q5.o
- .bss 0x0000000020000138 0x38 /tmp/ccRRCPG0.o
- .bss 0x0000000020000170 0x0 /tmp/ccWI4kHV.o
- .bss 0x0000000020000170 0x0 /tmp/ccjaIjJQ.o
- .bss 0x0000000020000170 0x0 /tmp/cceYjaVL.o
- .bss 0x0000000020000170 0x0 /tmp/ccsXJViH.o
- .bss 0x0000000020000170 0x8 /tmp/ccGz0VMC.o
+ .bss 0x00000000200000a0 0x98 /tmp/ccC4L2qX.o
+ .bss 0x0000000020000138 0x38 /tmp/ccTkGJkh.o
+ .bss 0x0000000020000170 0x0 /tmp/ccLc8YqB.o
+ .bss 0x0000000020000170 0x0 /tmp/ccNO0bzV.o
+ .bss 0x0000000020000170 0x0 /tmp/ccyL94Of.o
+ .bss 0x0000000020000170 0x0 /tmp/ccHrpyiA.o
+ .bss 0x0000000020000170 0x8 /tmp/ccek4wTU.o
0x0000000020000170 __errno
0x0000000020000174 _impure_ptr
- .bss 0x0000000020000178 0x0 /tmp/ccy5lZmy.o
+ .bss 0x0000000020000178 0x0 /tmp/ccm7EkDf.o
.bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
.bss 0x0000000020000178 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
*(.bss.*)
*(COMMON)
- COMMON 0x0000000020000178 0x20 /tmp/ccy8OCeb.o
+ COMMON 0x0000000020000178 0x20 /tmp/cce3buMD.o
0x0000000020000178 leds
- COMMON 0x0000000020000198 0x220 /tmp/ccRRCPG0.o
+ COMMON 0x0000000020000198 0x23c /tmp/ccTkGJkh.o
0x0000000020000198 usart_tx_buf
- 0x00000000200003b8 . = ALIGN (0x4)
- 0x00000000200003b8 _ebss = .
+ 0x00000000200003d4 . = ALIGN (0x4)
+ 0x00000000200003d4 _ebss = .
[!provide] PROVIDE (end = _ebss)
[!provide] PROVIDE (_end = _ebss)
- 0x00000000200003b8 __exidx_start = .
- 0x00000000200003b8 __exidx_end = .
+ 0x00000000200003d4 __exidx_start = .
+ 0x00000000200003d4 __exidx_end = .
.stab
*(.stab)
@@ -268,36 +268,36 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.comment 0x0000000000000000 0x21
*(.comment)
- .comment 0x0000000000000000 0x21 /tmp/ccy8OCeb.o
+ .comment 0x0000000000000000 0x21 /tmp/cce3buMD.o
0x22 (size before relaxing)
- .comment 0x0000000000000021 0x22 /tmp/cc6Un0Q5.o
- .comment 0x0000000000000021 0x22 /tmp/ccRRCPG0.o
- .comment 0x0000000000000021 0x22 /tmp/ccWI4kHV.o
- .comment 0x0000000000000021 0x22 /tmp/cceYjaVL.o
- .comment 0x0000000000000021 0x22 /tmp/ccsXJViH.o
- .comment 0x0000000000000021 0x22 /tmp/ccGz0VMC.o
- .comment 0x0000000000000021 0x22 /tmp/ccy5lZmy.o
+ .comment 0x0000000000000021 0x22 /tmp/ccC4L2qX.o
+ .comment 0x0000000000000021 0x22 /tmp/ccTkGJkh.o
+ .comment 0x0000000000000021 0x22 /tmp/ccLc8YqB.o
+ .comment 0x0000000000000021 0x22 /tmp/ccyL94Of.o
+ .comment 0x0000000000000021 0x22 /tmp/ccHrpyiA.o
+ .comment 0x0000000000000021 0x22 /tmp/ccek4wTU.o
+ .comment 0x0000000000000021 0x22 /tmp/ccm7EkDf.o
.ARM.attributes
0x0000000000000000 0x2f
.ARM.attributes
- 0x0000000000000000 0x2b /tmp/ccy8OCeb.o
+ 0x0000000000000000 0x2b /tmp/cce3buMD.o
.ARM.attributes
- 0x000000000000002b 0x2b /tmp/cc6Un0Q5.o
+ 0x000000000000002b 0x2b /tmp/ccC4L2qX.o
.ARM.attributes
- 0x0000000000000056 0x2b /tmp/ccRRCPG0.o
+ 0x0000000000000056 0x2b /tmp/ccTkGJkh.o
.ARM.attributes
- 0x0000000000000081 0x2b /tmp/ccWI4kHV.o
+ 0x0000000000000081 0x2b /tmp/ccLc8YqB.o
.ARM.attributes
- 0x00000000000000ac 0x21 /tmp/ccjaIjJQ.o
+ 0x00000000000000ac 0x21 /tmp/ccNO0bzV.o
.ARM.attributes
- 0x00000000000000cd 0x2b /tmp/cceYjaVL.o
+ 0x00000000000000cd 0x2b /tmp/ccyL94Of.o
.ARM.attributes
- 0x00000000000000f8 0x2b /tmp/ccsXJViH.o
+ 0x00000000000000f8 0x2b /tmp/ccHrpyiA.o
.ARM.attributes
- 0x0000000000000123 0x2b /tmp/ccGz0VMC.o
+ 0x0000000000000123 0x2b /tmp/ccek4wTU.o
.ARM.attributes
- 0x000000000000014e 0x31 /tmp/ccy5lZmy.o
+ 0x000000000000014e 0x31 /tmp/ccm7EkDf.o
.ARM.attributes
0x000000000000017f 0x1e /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.ARM.attributes
@@ -320,23 +320,23 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_aranges 0x0000000000000000 0x180
*(.debug_aranges)
.debug_aranges
- 0x0000000000000000 0x20 /tmp/ccy8OCeb.o
+ 0x0000000000000000 0x20 /tmp/cce3buMD.o
.debug_aranges
- 0x0000000000000020 0x20 /tmp/cc6Un0Q5.o
+ 0x0000000000000020 0x20 /tmp/ccC4L2qX.o
.debug_aranges
- 0x0000000000000040 0x20 /tmp/ccRRCPG0.o
+ 0x0000000000000040 0x20 /tmp/ccTkGJkh.o
.debug_aranges
- 0x0000000000000060 0x20 /tmp/ccWI4kHV.o
+ 0x0000000000000060 0x20 /tmp/ccLc8YqB.o
.debug_aranges
- 0x0000000000000080 0x28 /tmp/ccjaIjJQ.o
+ 0x0000000000000080 0x28 /tmp/ccNO0bzV.o
.debug_aranges
- 0x00000000000000a8 0x20 /tmp/cceYjaVL.o
+ 0x00000000000000a8 0x20 /tmp/ccyL94Of.o
.debug_aranges
- 0x00000000000000c8 0x20 /tmp/ccsXJViH.o
+ 0x00000000000000c8 0x20 /tmp/ccHrpyiA.o
.debug_aranges
- 0x00000000000000e8 0x20 /tmp/ccGz0VMC.o
+ 0x00000000000000e8 0x20 /tmp/ccek4wTU.o
.debug_aranges
- 0x0000000000000108 0x18 /tmp/ccy5lZmy.o
+ 0x0000000000000108 0x18 /tmp/ccm7EkDf.o
.debug_aranges
0x0000000000000120 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.debug_aranges
@@ -347,87 +347,87 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_pubnames
*(.debug_pubnames)
-.debug_info 0x0000000000000000 0x62e5
+.debug_info 0x0000000000000000 0x633c
*(.debug_info .gnu.linkonce.wi.*)
- .debug_info 0x0000000000000000 0x132d /tmp/ccy8OCeb.o
- .debug_info 0x000000000000132d 0x11f5 /tmp/cc6Un0Q5.o
- .debug_info 0x0000000000002522 0x13c6 /tmp/ccRRCPG0.o
- .debug_info 0x00000000000038e8 0xd07 /tmp/ccWI4kHV.o
- .debug_info 0x00000000000045ef 0x22 /tmp/ccjaIjJQ.o
- .debug_info 0x0000000000004611 0x263 /tmp/cceYjaVL.o
- .debug_info 0x0000000000004874 0x795 /tmp/ccsXJViH.o
- .debug_info 0x0000000000005009 0x1e9 /tmp/ccGz0VMC.o
- .debug_info 0x00000000000051f2 0x1081 /tmp/ccy5lZmy.o
- .debug_info 0x0000000000006273 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_info 0x0000000000006299 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_info 0x00000000000062bf 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_abbrev 0x0000000000000000 0x12ad
+ .debug_info 0x0000000000000000 0x1361 /tmp/cce3buMD.o
+ .debug_info 0x0000000000001361 0x1229 /tmp/ccC4L2qX.o
+ .debug_info 0x000000000000258a 0x1381 /tmp/ccTkGJkh.o
+ .debug_info 0x000000000000390b 0xd3b /tmp/ccLc8YqB.o
+ .debug_info 0x0000000000004646 0x22 /tmp/ccNO0bzV.o
+ .debug_info 0x0000000000004668 0x263 /tmp/ccyL94Of.o
+ .debug_info 0x00000000000048cb 0x795 /tmp/ccHrpyiA.o
+ .debug_info 0x0000000000005060 0x1e9 /tmp/ccek4wTU.o
+ .debug_info 0x0000000000005249 0x1081 /tmp/ccm7EkDf.o
+ .debug_info 0x00000000000062ca 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_info 0x00000000000062f0 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_info 0x0000000000006316 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_abbrev 0x0000000000000000 0x126f
*(.debug_abbrev)
- .debug_abbrev 0x0000000000000000 0x34c /tmp/ccy8OCeb.o
- .debug_abbrev 0x000000000000034c 0x314 /tmp/cc6Un0Q5.o
- .debug_abbrev 0x0000000000000660 0x3ec /tmp/ccRRCPG0.o
- .debug_abbrev 0x0000000000000a4c 0x274 /tmp/ccWI4kHV.o
- .debug_abbrev 0x0000000000000cc0 0x12 /tmp/ccjaIjJQ.o
- .debug_abbrev 0x0000000000000cd2 0x113 /tmp/cceYjaVL.o
- .debug_abbrev 0x0000000000000de5 0x23c /tmp/ccsXJViH.o
- .debug_abbrev 0x0000000000001021 0x117 /tmp/ccGz0VMC.o
- .debug_abbrev 0x0000000000001138 0x139 /tmp/ccy5lZmy.o
- .debug_abbrev 0x0000000000001271 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_abbrev 0x0000000000001285 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_abbrev 0x0000000000001299 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_line 0x0000000000000000 0x198f
+ .debug_abbrev 0x0000000000000000 0x34c /tmp/cce3buMD.o
+ .debug_abbrev 0x000000000000034c 0x314 /tmp/ccC4L2qX.o
+ .debug_abbrev 0x0000000000000660 0x3ae /tmp/ccTkGJkh.o
+ .debug_abbrev 0x0000000000000a0e 0x274 /tmp/ccLc8YqB.o
+ .debug_abbrev 0x0000000000000c82 0x12 /tmp/ccNO0bzV.o
+ .debug_abbrev 0x0000000000000c94 0x113 /tmp/ccyL94Of.o
+ .debug_abbrev 0x0000000000000da7 0x23c /tmp/ccHrpyiA.o
+ .debug_abbrev 0x0000000000000fe3 0x117 /tmp/ccek4wTU.o
+ .debug_abbrev 0x00000000000010fa 0x139 /tmp/ccm7EkDf.o
+ .debug_abbrev 0x0000000000001233 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_abbrev 0x0000000000001247 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_abbrev 0x000000000000125b 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_line 0x0000000000000000 0x19ac
*(.debug_line)
- .debug_line 0x0000000000000000 0x3d6 /tmp/ccy8OCeb.o
- .debug_line 0x00000000000003d6 0x37f /tmp/cc6Un0Q5.o
- .debug_line 0x0000000000000755 0x51f /tmp/ccRRCPG0.o
- .debug_line 0x0000000000000c74 0x2fa /tmp/ccWI4kHV.o
- .debug_line 0x0000000000000f6e 0x77 /tmp/ccjaIjJQ.o
- .debug_line 0x0000000000000fe5 0x1ab /tmp/cceYjaVL.o
- .debug_line 0x0000000000001190 0x466 /tmp/ccsXJViH.o
- .debug_line 0x00000000000015f6 0xf4 /tmp/ccGz0VMC.o
- .debug_line 0x00000000000016ea 0x148 /tmp/ccy5lZmy.o
- .debug_line 0x0000000000001832 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_line 0x00000000000018a8 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_line 0x0000000000001925 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_frame 0x0000000000000000 0x8c4
+ .debug_line 0x0000000000000000 0x3d6 /tmp/cce3buMD.o
+ .debug_line 0x00000000000003d6 0x37f /tmp/ccC4L2qX.o
+ .debug_line 0x0000000000000755 0x53c /tmp/ccTkGJkh.o
+ .debug_line 0x0000000000000c91 0x2fa /tmp/ccLc8YqB.o
+ .debug_line 0x0000000000000f8b 0x77 /tmp/ccNO0bzV.o
+ .debug_line 0x0000000000001002 0x1ab /tmp/ccyL94Of.o
+ .debug_line 0x00000000000011ad 0x466 /tmp/ccHrpyiA.o
+ .debug_line 0x0000000000001613 0xf4 /tmp/ccek4wTU.o
+ .debug_line 0x0000000000001707 0x148 /tmp/ccm7EkDf.o
+ .debug_line 0x000000000000184f 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_line 0x00000000000018c5 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_line 0x0000000000001942 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_frame 0x0000000000000000 0x8a4
*(.debug_frame)
- .debug_frame 0x0000000000000000 0x164 /tmp/ccy8OCeb.o
- .debug_frame 0x0000000000000164 0x104 /tmp/cc6Un0Q5.o
- .debug_frame 0x0000000000000268 0x1ac /tmp/ccRRCPG0.o
- .debug_frame 0x0000000000000414 0x90 /tmp/ccWI4kHV.o
- .debug_frame 0x00000000000004a4 0x4c /tmp/cceYjaVL.o
- .debug_frame 0x00000000000004f0 0x308 /tmp/ccsXJViH.o
- .debug_frame 0x00000000000007f8 0x8c /tmp/ccGz0VMC.o
- .debug_frame 0x0000000000000884 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_frame 0x00000000000008a4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
-
-.debug_str 0x0000000000000000 0x1404
+ .debug_frame 0x0000000000000000 0x164 /tmp/cce3buMD.o
+ .debug_frame 0x0000000000000164 0x104 /tmp/ccC4L2qX.o
+ .debug_frame 0x0000000000000268 0x18c /tmp/ccTkGJkh.o
+ .debug_frame 0x00000000000003f4 0x90 /tmp/ccLc8YqB.o
+ .debug_frame 0x0000000000000484 0x4c /tmp/ccyL94Of.o
+ .debug_frame 0x00000000000004d0 0x308 /tmp/ccHrpyiA.o
+ .debug_frame 0x00000000000007d8 0x8c /tmp/ccek4wTU.o
+ .debug_frame 0x0000000000000864 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame 0x0000000000000884 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+
+.debug_str 0x0000000000000000 0x141f
*(.debug_str)
- .debug_str 0x0000000000000000 0x968 /tmp/ccy8OCeb.o
- 0xa13 (size before relaxing)
- .debug_str 0x0000000000000968 0x125 /tmp/cc6Un0Q5.o
- 0x9a9 (size before relaxing)
- .debug_str 0x0000000000000a8d 0x1e1 /tmp/ccRRCPG0.o
- 0xa79 (size before relaxing)
- .debug_str 0x0000000000000c6e 0x82 /tmp/ccWI4kHV.o
- 0x6ba (size before relaxing)
- .debug_str 0x0000000000000cf0 0x22 /tmp/ccjaIjJQ.o
+ .debug_str 0x0000000000000000 0x991 /tmp/cce3buMD.o
+ 0xa3c (size before relaxing)
+ .debug_str 0x0000000000000991 0x125 /tmp/ccC4L2qX.o
+ 0x9d2 (size before relaxing)
+ .debug_str 0x0000000000000ab6 0x1d3 /tmp/ccTkGJkh.o
+ 0xa8e (size before relaxing)
+ .debug_str 0x0000000000000c89 0x82 /tmp/ccLc8YqB.o
+ 0x6e3 (size before relaxing)
+ .debug_str 0x0000000000000d0b 0x22 /tmp/ccNO0bzV.o
0x57 (size before relaxing)
- .debug_str 0x0000000000000d12 0x53 /tmp/cceYjaVL.o
+ .debug_str 0x0000000000000d2d 0x53 /tmp/ccyL94Of.o
0x219 (size before relaxing)
- .debug_str 0x0000000000000d65 0x3ae /tmp/ccsXJViH.o
+ .debug_str 0x0000000000000d80 0x3ae /tmp/ccHrpyiA.o
0x5bf (size before relaxing)
- .debug_str 0x0000000000001113 0x39 /tmp/ccGz0VMC.o
+ .debug_str 0x000000000000112e 0x39 /tmp/ccek4wTU.o
0x1b7 (size before relaxing)
- .debug_str 0x000000000000114c 0x216 /tmp/ccy5lZmy.o
+ .debug_str 0x0000000000001167 0x216 /tmp/ccm7EkDf.o
0x5ca (size before relaxing)
- .debug_str 0x0000000000001362 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_str 0x000000000000137d 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
0xae (size before relaxing)
- .debug_str 0x0000000000001404 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_str 0x0000000000001404 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .debug_str 0x000000000000141f 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_str 0x000000000000141f 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
.debug_loc
*(.debug_loc)
@@ -449,5 +449,5 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
OUTPUT(main.elf elf32-littlearm)
.debug_ranges 0x0000000000000000 0x38
- .debug_ranges 0x0000000000000000 0x18 /tmp/ccWI4kHV.o
- .debug_ranges 0x0000000000000018 0x20 /tmp/ccjaIjJQ.o
+ .debug_ranges 0x0000000000000000 0x18 /tmp/ccLc8YqB.o
+ .debug_ranges 0x0000000000000018 0x20 /tmp/ccNO0bzV.o
diff --git a/gm_platform/fw/serial.c b/gm_platform/fw/serial.c
index 178d6f9..5a6009c 100644
--- a/gm_platform/fw/serial.c
+++ b/gm_platform/fw/serial.c
@@ -41,15 +41,18 @@ static volatile uint8_t rx_buf[32];
static void usart_schedule_dma(void);
static int usart_putc_nonblocking(uint8_t c);
-static int usart_retransmit_packet(uint8_t idx);
void usart_dma_init() {
usart_tx_buf.xfr_start = -1;
usart_tx_buf.xfr_end = 0;
usart_tx_buf.wr_pos = 0;
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- usart_tx_buf.packet_start[i] = -1;
+ usart_tx_buf.wr_idx = 0;
+ usart_tx_buf.cur_packet = -1;
+ usart_tx_buf.retransmit_rq = 0;
+ usart_tx_buf.wraparound = 0;
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ usart_tx_buf.packet_end[i] = -1;
cobs_decode_incremental_initialize(&cobs_state);
@@ -134,8 +137,8 @@ void USART1_IRQHandler() {
switch (pkt->type) {
case CTRL_PKT_RESET:
- for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
- usart_tx_buf.packet_start[i] = -1;
+ for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
+ usart_tx_buf.packet_end[i] = -1;
break;
case CTRL_PKT_ACK:
@@ -144,8 +147,9 @@ void USART1_IRQHandler() {
break;
case CTRL_PKT_RETRANSMIT:
- if (usart_retransmit_packet(pkt->orig_id))
- rx_protocol_errors++;
+ usart_tx_buf.retransmit_rq = 1;
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ usart_schedule_dma();
break;
default:
@@ -161,26 +165,56 @@ void usart_schedule_dma() {
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
- ssize_t xfr_len, xfr_start = buf->xfr_end;
- if (buf->wr_pos > xfr_start) /* no wraparound */
- xfr_len = buf->wr_pos - xfr_start;
+ ssize_t next_start, next_idx;
+ if (buf->wraparound) {
+ buf->wraparound = 0;
+ next_idx = buf->cur_packet;
+ next_start = 0;
+
+ } else if (buf->retransmit_rq) {
+ buf->retransmit_rq = 0;
+ next_idx = buf->cur_packet;
+ next_start = buf->xfr_start;
+
+ } else {
+ next_idx = (buf->cur_packet + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
+ next_start = buf->xfr_end;
+ }
+
+ ssize_t next_end = buf->packet_end[next_idx];
+
+ /* Nothing to trasnmit */
+ if (next_end == -1)
+ return;
+
+ ssize_t xfr_len;
+ if (next_end > next_start) /* no wraparound */
+ xfr_len = next_end - next_start;
else /* wraparound */
- xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */
+ xfr_len = sizeof(buf->data) - next_start; /* schedule transfer until end of buffer */
- buf->xfr_start = xfr_start;
- buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
+ buf->xfr_start = next_start;
+ buf->xfr_end = (next_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
+ buf->cur_packet = next_idx;
/* initiate transmission of new buffer */
- DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start);
+ DMA1_Channel2->CMAR = (uint32_t)(buf->data + next_start);
DMA1_Channel2->CNDTR = xfr_len;
DMA1_Channel2->CCR |= DMA_CCR_EN;
}
int usart_ack_packet(uint8_t idx) {
- if (idx > ARRAY_LEN(usart_tx_buf.packet_start))
+ if (idx > ARRAY_LEN(usart_tx_buf.packet_end))
return -EINVAL;
- usart_tx_buf.packet_start[idx] = -1;
+ if (idx != usart_tx_buf.cur_packet)
+ return -EINVAL;
+
+ usart_tx_buf.packet_end[idx] = -1;
+
+ /* If the DMA stream is idle right now, schedule the next transfer */
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ usart_schedule_dma();
return 0;
}
@@ -188,16 +222,11 @@ int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
- /* If the write pointer hit any unacknowledged packet start position we can't advance it.
- * Packet start positions are unordered and we have to scan here. */
- for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
- if (buf->wr_pos == buf->packet_start[i]) {
- NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- return -EBUSY;
- }
+ if (buf->wr_pos == buf->xfr_start) {
+ NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ return -EBUSY;
}
- /* write byte, then increment to avoid racing the DMA ISR reading wr_pos */
buf->data[buf->wr_pos] = c;
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
@@ -223,55 +252,20 @@ void DMA1_Channel2_3_IRQHandler(void) {
DMA1->IFCR |= DMA_IFCR_CTCIF2;
DMA1_Channel2->CCR &= ~DMA_CCR_EN;
- if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */
+ if (usart_tx_buf.retransmit_rq || usart_tx_buf.wraparound)
usart_schedule_dma();
}
-int usart_retransmit_packet(uint8_t idx) {
- /* Disable ADC DMA IRQ to prevent write races */
- NVIC_DisableIRQ(DMA1_Channel1_IRQn);
-
- ssize_t i = usart_tx_buf.packet_start[idx];
- ssize_t start = i;
-
- /* Copy packet */
- uint8_t c;
- while ((c = usart_tx_buf.data[i++])) {
- if (usart_putc_nonblocking(c)) {
- tx_overruns++;
- return -EBUSY;
- }
- }
+/* len is the packet length including headers */
+int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
- /* Terminating null byte */
- if (usart_putc_nonblocking(0)) {
+ if (usart_tx_buf.packet_end[usart_tx_buf.wr_idx] != -1) {
+ /* Find a free slot for this packet */
tx_overruns++;
return -EBUSY;
}
- /* Update start index */
- usart_tx_buf.packet_start[idx] = start;
-
- NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- return 0;
-}
-
-/* len is the packet length including headers */
-int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
-
- ssize_t start = usart_tx_buf.wr_pos;
- /* Find a free slot for this packet */
- size_t packet_idx = 0;
- do {
- if (usart_tx_buf.packet_start[packet_idx] == -1)
- goto success;
- } while (++packet_idx <ARRAY_LEN(usart_tx_buf.packet_start));
-
- tx_overruns++;
- return -EBUSY;
-
-success:
- pkt->pid = packet_idx;
+ pkt->pid = usart_tx_buf.wr_idx;
pkt->_pad = 0;
/* make the value this wonky-ass CRC implementation produces match zlib etc. */
@@ -280,19 +274,14 @@ success:
CRC->DR = ((uint8_t *)pkt)[i];
pkt->crc32 = ~CRC->DR;
+
int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
if (rc)
return rc;
- /* Checkpoint packet start index to prevent overwriting before ack */
- usart_tx_buf.packet_start[packet_idx] = start;
- /* FIXME debug code
- static uint8_t x = 0;
- for (size_t i=0; i<351; i++)
- usart_putc_nonblocking(x++);
- */
+ usart_tx_buf.packet_end[usart_tx_buf.wr_idx] = usart_tx_buf.wr_pos;
+ usart_tx_buf.wr_idx = (usart_tx_buf.wr_idx + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
- /* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
usart_schedule_dma();
return 0;
diff --git a/gm_platform/fw/serial.h b/gm_platform/fw/serial.h
index 39ffd18..61ac4eb 100644
--- a/gm_platform/fw/serial.h
+++ b/gm_platform/fw/serial.h
@@ -33,11 +33,14 @@ struct dma_tx_buf {
/* The following fields are accessed only from DMA ISR */
ssize_t xfr_start; /* Start index of running DMA transfer */
ssize_t xfr_end; /* End index of running DMA transfer plus one */
- uint8_t cur_packet;
+ ssize_t cur_packet;
+ int retransmit_rq;
+ int wraparound;
/* The following fields are written only from non-interrupt code */
ssize_t wr_pos; /* Next index to be written */
- ssize_t packet_start[8];
+ ssize_t wr_idx;
+ ssize_t packet_end[8];
/* The following may be accessed by anything */
uint8_t data[512];
generated by cgit (git 2.34.1) at 2024-11-21 17:46:46 +0000