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author | jaseg <git@jaseg.net> | 2020-01-25 11:53:44 +0100 |
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committer | jaseg <git@jaseg.net> | 2020-01-25 11:53:44 +0100 |
commit | 966f104597275b29f41c06c4574d1bbe9ecde401 (patch) | |
tree | 56224782459e8b7983df5605809c7269539a7cb1 /gm_platform/fw/adc.c | |
parent | 410e38651052038e34843b17269d61e75720f0ba (diff) | |
download | master-thesis-966f104597275b29f41c06c4574d1bbe9ecde401.tar.gz master-thesis-966f104597275b29f41c06c4574d1bbe9ecde401.tar.bz2 master-thesis-966f104597275b29f41c06c4574d1bbe9ecde401.zip |
serial wip
Diffstat (limited to 'gm_platform/fw/adc.c')
-rw-r--r-- | gm_platform/fw/adc.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/gm_platform/fw/adc.c b/gm_platform/fw/adc.c index 547089b..2a33171 100644 --- a/gm_platform/fw/adc.c +++ b/gm_platform/fw/adc.c @@ -16,11 +16,14 @@ */ #include "adc.h" +#include "serial.h" #include <stdbool.h> #include <stdlib.h> +#include <assert.h> -volatile uint16_t adc_buf[ADC_BUFSIZE]; +volatile uint16_t adc_buf[100]; /* 100ms worth of data */ +uint32_t usart_overruns = 0; static void adc_dma_init(int burstlen); static void adc_timer_init(int psc, int ivl); @@ -56,9 +59,6 @@ void adc_configure_scope_mode(int sampling_interval_ns) { adc_timer_init(12/*250ns/tick*/, cycles); } -/* FIXME figure out the proper place to configure this. */ -#define ADC_TIMER_INTERVAL_US 20 - static void adc_dma_init(int burstlen) { /* Configure DMA 1 Channel 1 to get rid of all the data */ DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR; @@ -70,11 +70,12 @@ static void adc_dma_init(int burstlen) { | (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */ | (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */ | DMA_CCR_MINC + | DMA_CCR_HTIE /* Enable half-transfer interrupt. */ | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ - /* triggered on transfer completion. We use this to process the ADC data */ + /* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */ NVIC_EnableIRQ(DMA1_Channel1_IRQn); - NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5); + NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5); DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */ } @@ -99,9 +100,21 @@ static void gdb_dump(void) { } void DMA1_Channel1_IRQHandler(void) { + uint32_t isr = DMA1->ISR; /* Clear the interrupt flag */ DMA1->IFCR |= DMA_IFCR_CGIF1; + gdb_dump(); + static_assert(ARRAY_LEN(adc_buf) % 2 == 0, "ADC_BUFSIZE must be even for half-transfer uart tx logic to work"); + + int rc; + if (isr & DMA_ISR_HTIF2) /* half-transfer */ + rc = usart_send_packet_nonblocking((uint8_t *)adc_buf, sizeof(adc_buf)/2); + else /* end of transfer */ + rc = usart_send_packet_nonblocking((uint8_t *)adc_buf + ARRAY_LEN(adc_buf)/2, sizeof(adc_buf)/2); + + if (rc) + usart_overruns++; /* static int debug_buf_pos = 0; |