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| author | jaseg <git-bigdata-wsl-arch@jaseg.de> | 2020-03-13 18:19:02 +0100 |
|---|---|---|
| committer | jaseg <git-bigdata-wsl-arch@jaseg.de> | 2020-03-13 18:19:02 +0100 |
| commit | 1b7ae0aeefb4ccb2913c3bd8a2f5ac1c84b0a75d (patch) | |
| tree | 820c2f3f174a57e363885bf0ededfb9efb48a4ed /controller/fw/src/adc.c | |
| parent | 838eb6b26e4acc53cda47abaca6ed6392ae31ffc (diff) | |
| download | master-thesis-1b7ae0aeefb4ccb2913c3bd8a2f5ac1c84b0a75d.tar.gz master-thesis-1b7ae0aeefb4ccb2913c3bd8a2f5ac1c84b0a75d.tar.bz2 master-thesis-1b7ae0aeefb4ccb2913c3bd8a2f5ac1c84b0a75d.zip | |
having problems with dma m2m mode
Diffstat (limited to 'controller/fw/src/adc.c')
| -rw-r--r-- | controller/fw/src/adc.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/controller/fw/src/adc.c b/controller/fw/src/adc.c index 4801525..fba2420 100644 --- a/controller/fw/src/adc.c +++ b/controller/fw/src/adc.c @@ -37,29 +37,30 @@ void adc_init() { while (adc_stream->CR & DMA_SxCR_EN) ; /* wait for stream to become available */ adc_stream->NDTR = FMEAS_FFT_LEN/2; - adc_stream->PAR = ADC1->DR; + adc_stream->PAR = &(ADC1->DR); adc_stream->M0AR = (uint32_t) (adc_fft_buf[0] + FMEAS_FFT_LEN/2); adc_stream->M1AR = (uint32_t) (adc_fft_buf[1] + FMEAS_FFT_LEN/2); adc_stream->CR = (dma_adc_channel<<DMA_SxCR_CHSEL_Pos) | DMA_SxCR_DBM | (1<<DMA_SxCR_MSIZE_Pos) - | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_PFCTRL - | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE | DMA_SxCR_EN; + | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | (2<<DMA_SxCR_PL_Pos) + | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE; adc_stream->CR |= DMA_SxCR_EN; NVIC_EnableIRQ(DMA2_Stream0_IRQn); NVIC_SetPriority(DMA2_Stream0_IRQn, 128); ADC1->CR1 = (0<<ADC_CR1_RES_Pos) | (0<<ADC_CR1_DISCNUM_Pos) | ADC_CR1_DISCEN | (0<<ADC_CR1_AWDCH_Pos); - ADC1->CR2 = ADC_CR2_EXTEN | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS; + ADC1->CR2 = (1<<ADC_CR2_EXTEN_Pos) | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS; ADC1->SQR3 = (adc_channel<<ADC_SQR3_SQ3_Pos); ADC1->SQR1 = (0<<ADC_SQR1_L_Pos); TIM1->CR2 = (2<<TIM_CR2_MMS_Pos); /* Enable update event on TRGO to provide a 1ms reference to rest of system */ - TIM1->CR1 = TIM_CR1_CEN; TIM1->CCMR1 = (6<<TIM_CCMR1_OC1M_Pos) | (0<<TIM_CCMR1_CC1S_Pos); TIM1->CCER = TIM_CCER_CC1E; TIM1->PSC = 84-1; /* 1us ticks @ f_APB2=84MHz */ TIM1->ARR = 1000-1; /* 1ms period */ - TIM1->CCR1 = 1; + TIM1->CCR1 = 500-1; + TIM1->BDTR = TIM_BDTR_MOE; + TIM1->CR1 = TIM_CR1_CEN; TIM1->EGR = TIM_EGR_UG; } @@ -75,14 +76,16 @@ void DMA2_Stream0_IRQHandler(void) { if (mem_stream->CR & DMA_SxCR_EN) panic(); /* We should be long done by now. */ + adc_dma->LIFCR = 0x3d<<DMA_LISR_FEIF1_Pos; mem_stream->NDTR = FMEAS_FFT_LEN/2; int ct = !!(adc_stream->CR & DMA_SxCR_CT); /* back half of old buffer (that was just written) */ - mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct]); + mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct] + FMEAS_FFT_LEN/2); /* front half of current buffer (whose back half is being written now) */ mem_stream->M0AR = (uint32_t) (adc_fft_buf[ct] + 0); + mem_stream->CR = (1<<DMA_SxCR_MSIZE_Pos) | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_PINC - | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE; + | (0<<DMA_SxCR_PL_Pos) | (2<<DMA_SxCR_DIR_Pos); mem_stream->CR |= DMA_SxCR_EN; /* Kickoff FFT */ |