From f14b83d06412aad735d985a6d7cd4595d20f83b8 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Tue, 13 Jul 2021 13:25:03 +0200
Subject: Work on changes letter

---
 paper/ihsm_paper.tex | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

(limited to 'paper/ihsm_paper.tex')

diff --git a/paper/ihsm_paper.tex b/paper/ihsm_paper.tex
index de94ea2..024ca1f 100644
--- a/paper/ihsm_paper.tex
+++ b/paper/ihsm_paper.tex
@@ -771,8 +771,27 @@ tamper status to the static monitoring circuit at least once every $T_\text{tx}
 $\SI{100}{\kilo\baud}$, a transmission of a one-byte message in standard UART framing would take
 $\SI{100}{\micro\second}$ and yield an $\SI{1}{\percent}$ duty cycle. If we assume an optical or RF transmitter that
 requires $\SI{10}{\milli\ampere}$ of active current, this yields an average operating current of
-$\SI{100}{\micro\ampere}$. Reserving another $\SI{100}{\micro\ampere}$ for the monitoring circuit itself we arrive at an
-energy consumption of $\SI{1.7}{\ampere\hour}$ per year.
+$\SI{100}{\micro\ampere}$.  This value is comparable to a reasonable estimation of the current consumption of the
+monitoring cirucit itself. In our prototype we used ST Microelectronics STM32 Series ARM Cortex-M microcontrollers. To
+get an estimate on the current consumption of an energy-optimized design we will refer to the datasheet of the
+\texttt{STM32L486JG}\footnote{\url{https://www.st.com/resource/en/datasheet/stm32l486jg.pdf}}, a representative member
+of ST's \texttt{STM32L4} low-power sub-family that provides hardware acceleration for AES256. A good target for an
+implementation of a secure cryptographic channel on this device would be the noise protocol framework~\cite{perrin2018}.
+While the initial handshake for key establishment uses elliptic-curve cryptography and may take several hundred
+milliseconds~\cite{tschofenig2015}, the following payload data transfer messages require only symmetric cryptographic
+primitives. The \texttt{STM32L486JG} datasheet lists the microcontroller's typical operating current at around
+$\SI{8}{\milli\ampere}$ at $\SI{48}{\mega\hertz}$ clock speed, and lists a sleep current of less than
+$\SI{1}{\micro\ampere}$ in low-power standby mode with RTC enabled. The AES peripheral is listed with less than
+$\SI{2}{\micro\ampere\per\mega\hertz}$ typical current consumption. A typical high-$g$ accelerometer for an IHSM
+application would be ST Microelectronics' \texttt{H3LIS331DL}. Its
+datasheet\footnote{\url{https://www.st.com/resource/en/datasheet/h3lis331dl.pdf}} lists a typical current consumption
+between $\SI{10}{\micro\ampere}$ in low-power mode with output sampling rate up to $\SI{10}{\hertz}$ and
+$\SI{300}{\micro\ampere}$ in normal operating mode with output sampling rate up to $\SI{1}{\kilo\hertz}$.  Given the low
+amount of data (hundreds of bytes per second) that has to be processed in our application, if we assume a duty cycle of
+$\SI{1}{\percent}$ of active data processing vs.\ sleep mode at the given clock speed we arrive at a total estimated
+current consumption of our microcontroller of less than $\SI{100}{\micro\ampere}$.  Thus, reserving
+$\SI{100}{\micro\ampere}$ for the monitoring circuit on top of the $\SI{100}{\micro\ampere}$ for the transceiver circuit
+we arrive at an energy consumption of $\SI{1.7}{\ampere\hour}$ per year.
 
 This annual energy consumption is close to the capacity of a single CR123A lithium primary cell. Thus, by either using
 several such cells or by optimizing power consumption several years of battery life could easily be reached.  In our
-- 
cgit 

