summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2020-10-08TCC scenario performance: WIPjaseg1-0/+0
2020-10-07Merge HW dev and orga reposjaseg68-29/+4734
2020-10-07Add missing docsjaseg7-0/+2918
2020-10-02base schematic done, PCB WIPjaseg4-3098/+8540
2020-10-02schematic WIPjaseg3-19/+2636
2020-10-01Add images, translate FC -> KiCADjaseg17-85/+83114
2020-09-30Initial FC mech -> KiCAD PCB edge exportjaseg11-36/+216
2020-09-30Initial commitjaseg47-0/+2819
2020-09-18Finish first rough draftjaseg2-7/+191
2020-09-18Add prior art and engineering constraintsjaseg1-7/+121
2020-09-17Add contributions sectionjaseg1-1/+15
2020-09-16Initial commitjaseg4-0/+268