Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-10-08 | TCC scenario performance: WIP | jaseg | 1 | -0/+0 |
2020-10-07 | Merge HW dev and orga repos | jaseg | 68 | -29/+4734 |
2020-10-07 | Add missing docs | jaseg | 7 | -0/+2918 |
2020-10-02 | base schematic done, PCB WIP | jaseg | 4 | -3098/+8540 |
2020-10-02 | schematic WIP | jaseg | 3 | -19/+2636 |
2020-10-01 | Add images, translate FC -> KiCAD | jaseg | 17 | -85/+83114 |
2020-09-30 | Initial FC mech -> KiCAD PCB edge export | jaseg | 11 | -36/+216 |
2020-09-30 | Initial commit | jaseg | 47 | -0/+2819 |
2020-09-18 | Finish first rough draft | jaseg | 2 | -7/+191 |
2020-09-18 | Add prior art and engineering constraints | jaseg | 1 | -7/+121 |
2020-09-17 | Add contributions section | jaseg | 1 | -1/+15 |
2020-09-16 | Initial commit | jaseg | 4 | -0/+268 |