From be8371c7bc21abe12db49f9dd38dac4513a64886 Mon Sep 17 00:00:00 2001 From: jaseg Date: Wed, 6 Nov 2024 14:49:50 +0100 Subject: Improve allegro/orcad import --- gerbonara/tests/test_layers.py | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'gerbonara/tests') diff --git a/gerbonara/tests/test_layers.py b/gerbonara/tests/test_layers.py index a5103de..b473f91 100644 --- a/gerbonara/tests/test_layers.py +++ b/gerbonara/tests/test_layers.py @@ -302,7 +302,21 @@ REFERENCE_DIRS = { 'Drill/8seg_Driver__routed_Drill_thru_plt.fdr/8seg_Driver__routed_Drill_thru_plt.fdl': None, 'Drill/8seg_Driver__routed_Drill_thru_plt.fdr/8seg_Driver__routed_Drill_thru_plt.fdr': 'drill plated', 'Drill/8seg_Driver__routed_Drill_thru_nplt.fdr': 'drill nonplated', - } + }, + 'orcad': { + 'Assembly.art': None, + 'BOTTOM.art': 'bottom copper', + 'GND2.art': 'inner_3 copper', + 'LAYER_1.art': 'inner_2 copper', + 'LAYER_2.art': 'inner_4 copper', + 'PWR.art': 'inner_2 copper', + 'Solder_Mask_Bottom.art': 'bottom mask', + 'Solder_Mask_Top.art': 'top mask', + 'TOP.art': 'top copper', + 'arena_12-12_v6_L1-L6.drl': 'drill plated', + 'silk_screen_bottom.art': 'bottom silk', + 'silk_screen_top.art': 'top silk', + }, } @filter_syntax_warnings -- cgit