From d0f836ecfadacbaea20fc6a3ceebd455e96e1307 Mon Sep 17 00:00:00 2001 From: jaseg Date: Sun, 13 Jun 2021 20:33:19 +0200 Subject: Port old pcb-tools-extension unit tests to pytest --- .../tests/panelize/expects/dxf_save_line.gtl | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 gerbonara/gerber/tests/panelize/expects/dxf_save_line.gtl (limited to 'gerbonara/gerber/tests/panelize/expects/dxf_save_line.gtl') diff --git a/gerbonara/gerber/tests/panelize/expects/dxf_save_line.gtl b/gerbonara/gerber/tests/panelize/expects/dxf_save_line.gtl new file mode 100644 index 0000000..b3ee8f1 --- /dev/null +++ b/gerbonara/gerber/tests/panelize/expects/dxf_save_line.gtl @@ -0,0 +1,93 @@ +%MOMM*% +%FSLAX34Y34*% +%IPPOS*% +%ADD10C,0.2*% +G75* +%LPD*% +D10* +G01* +X800000Y850000D02* +G75* +G01* +X800000Y350000D01* +G01* +X900000Y850000D02* +G75* +G01* +X900000Y350000D01* +G01* +X200000Y329390D02* +G75* +G01* +X325827Y329390D01* +G01* +X325827Y178443D01* +G01* +X400000Y0D02* +G75* +G01* +X100000Y0D01* +G02* +X0Y100000I0J100000D01* +G01* +X0Y400000D01* +G02* +X100000Y500000I100000J0D01* +G01* +X400000Y500000D01* +G02* +X500000Y400000I0J-100000D01* +G01* +X500000Y100000D01* +G02* +X400000Y0I-100000J0D01* +G01* +X742704Y750394D02* +G75* +G01* +X742704Y450394D01* +G02* +X642704Y350394I-100000J0D01* +G01* +X342704Y350394D01* +G02* +X242704Y450394I0J100000D01* +G01* +X242704Y750394D01* +G02* +X342704Y850394I100000J0D01* +G01* +X642704Y850394D01* +G02* +X742704Y750394I0J-100000D01* +G01* +X382038Y422062D02* +G75* +G01* +X134512Y422062D01* +G01* +X134512Y135960D01* +G01* +X382038Y135960D01* +G01* +X382038Y422062D01* +G01* +X927009Y126316D02* +G75* +G03* +X927009Y126316I-125463J0D01* +G01* +X602773Y650000D02* +G75* +G03* +X602773Y650000I-102773J0D01* +G01* +X500000Y650000D02* +G75* +G01* +X500000Y714592D01* +G03* +X562602Y634088I0J-64592D01* +G01* +X500000Y650000D01* +M02* -- cgit