From d0f836ecfadacbaea20fc6a3ceebd455e96e1307 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Sun, 13 Jun 2021 20:33:19 +0200
Subject: Port old pcb-tools-extension unit tests to pytest

---
 .../gerber/tests/panelize/expects/RS2724x_save.gtl | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 gerbonara/gerber/tests/panelize/expects/RS2724x_save.gtl

(limited to 'gerbonara/gerber/tests/panelize/expects/RS2724x_save.gtl')

diff --git a/gerbonara/gerber/tests/panelize/expects/RS2724x_save.gtl b/gerbonara/gerber/tests/panelize/expects/RS2724x_save.gtl
new file mode 100644
index 0000000..5053d99
--- /dev/null
+++ b/gerbonara/gerber/tests/panelize/expects/RS2724x_save.gtl
@@ -0,0 +1,78 @@
+%MOMM*%
+%FSLAX34Y34*%
+%IPPOS*%
+%AMCOMP*
+20,1,0.2,0,0.1,0.4,0.1,$1*
+21,1,0.4,0.2,-0.2,-0.1,$1*
+1,1,0.4,-1.2,0,$1*
+4,1,4,1.2,0,1.4,-0.2,1.2,-0.4,1,-0.2,1.2,0,$1*
+5,1,6,1.2,0.2,0.4,$1*
+6,-0.7,0,0.5,0.05,0.15,2,0.05,0.6,$1*
+7,0.7,0,0.6,0.5,0.15,$1*%
+%ADD10C,0.01*%
+%ADD11C,1X0.4*%
+%ADD12R,1X0.5X0.2*%
+%ADD13O,1X0.5X0.2*%
+%ADD14O,0.5X1X0.2*%
+%ADD15P,1X5X90X0.2*%
+%ADD16COMP,0*%
+%ADD17COMP,45*%
+%ADD18COMP,-45*%
+G75*
+%LPD*%
+D10*
+G01*
+X10000Y0D02*
+X90000Y0D01*
+G03*
+X100000Y10000I0J10000D01*
+G01*
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+M02*
-- 
cgit