From d0f836ecfadacbaea20fc6a3ceebd455e96e1307 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Sun, 13 Jun 2021 20:33:19 +0200
Subject: Port old pcb-tools-extension unit tests to pytest

---
 .../tests/panelize/expects/RS2724x_offset.gtl      | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 gerbonara/gerber/tests/panelize/expects/RS2724x_offset.gtl

(limited to 'gerbonara/gerber/tests/panelize/expects/RS2724x_offset.gtl')

diff --git a/gerbonara/gerber/tests/panelize/expects/RS2724x_offset.gtl b/gerbonara/gerber/tests/panelize/expects/RS2724x_offset.gtl
new file mode 100644
index 0000000..3dc3e6a
--- /dev/null
+++ b/gerbonara/gerber/tests/panelize/expects/RS2724x_offset.gtl
@@ -0,0 +1,78 @@
+%MOMM*%
+%FSLAX34Y34*%
+%IPPOS*%
+%AMCOMP*
+20,1,0.2,0,0.1,0.4,0.1,$1*
+21,1,0.4,0.2,-0.2,-0.1,$1*
+1,1,0.4,-1.2,0,$1*
+4,1,4,1.2,0,1.4,-0.2,1.2,-0.4,1,-0.2,1.2,0,$1*
+5,1,6,1.2,0.2,0.4,$1*
+6,-0.7,0,0.5,0.05,0.15,2,0.05,0.6,$1*
+7,0.7,0,0.6,0.5,0.15,$1*%
+%ADD10C,0.01*%
+%ADD11C,1X0.4*%
+%ADD12R,1X0.5X0.2*%
+%ADD13O,1X0.5X0.2*%
+%ADD14O,0.5X1X0.2*%
+%ADD15P,1X5X90X0.2*%
+%ADD16COMP,0*%
+%ADD17COMP,45*%
+%ADD18COMP,-45*%
+G75*
+%LPD*%
+D10*
+G01*
+X120000Y50000D02*
+X200000Y50000D01*
+G03*
+X210000Y60000I0J10000D01*
+G01*
+X210000Y140000D01*
+G03*
+X200000Y150000I-10000J0D01*
+G01*
+X120000Y150000D01*
+G03*
+X110000Y140000I0J-10000D01*
+G01*
+X110000Y60000D01*
+G03*
+X120000Y50000I10000J0D01*
+G01*
+G36*
+G01*
+X155000Y60000D02*
+X160000Y60000D01*
+G03*
+X165000Y65000I0J5000D01*
+G01*
+X165000Y135000D01*
+G03*
+X160000Y140000I-5000J0D01*
+G01*
+X155000Y140000D01*
+G03*
+X150000Y135000I0J-5000D01*
+G01*
+X150000Y65000D01*
+G03*
+X155000Y60000I5000J0D01*
+G01*
+G37*
+D11*
+X135000Y60000D03*
+D12*
+X135000Y80000D03*
+D13*
+X135000Y100000D03*
+D14*
+X135000Y120000D03*
+D15*
+X135000Y140000D03*
+D16*
+X185000Y100000D03*
+D17*
+X185000Y125000D03*
+D18*
+X185000Y75000D03*
+M02*
-- 
cgit