summaryrefslogtreecommitdiff
path: root/gerbonara
AgeCommit message (Collapse)AuthorFilesLines
2024-07-07protoboard: Improve layout packingjaseg1-2/+45
2024-07-07protoboard: Improve row/column numberingjaseg1-16/+42
2024-07-07protoboard: reduce hole keepout marginsjaseg1-1/+1
2024-07-07protoboard: improve border handlingjaseg1-29/+63
2024-07-07protoboard: fix column label alignmentjaseg2-3/+4
2024-07-07Fix THT flower proto areajaseg3-8/+30
2024-07-07Spiky proto also works nowjaseg3-5/+6
2024-07-07Protoboard: All layouts except for spiky proto workjaseg2-126/+140
2024-07-06Protoboard generator WIPjaseg3-30/+66
2024-05-28kicad_sch render: Fix nightly import and wire renderingjaseg4-6/+7
2023-11-14Bump version to v1.2.0v1.2.0jaseg1-1/+1
2023-11-14Make new test files passjaseg5-14/+139
2023-11-14Fix failing testsjaseg2-12/+21
2023-11-14Small bugfixjaseg1-2/+2
2023-11-14Calculate out all aperture macros by default.jaseg6-75/+65
There are just too many severely buggy implementations around. Today I ran into problems with both gerbv and with whatever JLC uses. You can still export macros with raw expressions by setting a flag in the export FileSettings.
2023-11-14aperture macros: work around gerbv/jlc wonkinessjaseg9-78/+216
2023-11-14Remove debug printjaseg1-1/+0
2023-11-14aperture macros: Add expression simplificationjaseg1-20/+3
2023-11-14Aperture macro expression simplification WIPjaseg3-16/+127
2023-11-14Make sure we asterisk-terminate all G0x commands.jaseg1-3/+3
While this is common in the wild, not terminating them violates the spec. It also breaks JLCPCB pretty badly. It seems their human review process uses a Gerber viewer that like most can handle this, and won't notice anything out of the ordinary, but then their photoplotter chokes on this and literally stops plotting the file, discarding anything that is after that line. This error is then apparently ignored and the resulting broken boards shipped to the customer.
2023-11-14Split CLI into pretty svg and layer export sub-commandsjaseg1-1/+34
2023-11-14pretty svg export: Mirror board bottom sidejaseg1-1/+7
2023-11-14Add JLCPCB KiCad Gerber X2/aperture macro test filesjaseg45-0/+45534
2023-11-14Add JLCPCB/FAB-3000 example gerbersjaseg11-0/+22631
2023-11-14Add P-CAD 2006 example gerbersjaseg13-0/+34535
2023-10-27Bump version to v1.1.0v1.1.0jaseg1-1/+1
2023-10-26Fix failing test casesjaseg9-51/+107
2023-10-26Fix all failing tests that don't involve kicad-clijaseg10-154/+78
2023-10-12Add coil test board genjaseg1-0/+1
2023-10-10Run more simsjaseg1-1/+1
2023-10-06Add missing simulation yamlsjaseg2-3/+19
2023-09-26WIPjaseg1-91/+42
2023-09-26cli: Add kicad schematic svg renderingjaseg6-42/+98
2023-09-22WIPjaseg5-119/+210
2023-09-22Trace connectivity WIPjaseg3-43/+135
2023-09-20coil gen: add kicad pcb exportjaseg2-7/+75
2023-09-19Multilayer coil WIPjaseg8-54/+211
2023-07-22Add line wonkifierjaseg2-21/+187
2023-07-22Add tmtheme supportjaseg5-9/+82
2023-07-22Made junctions smallerjaseg1-2/+2
2023-07-22Subsheet rendering works toojaseg2-14/+45
2023-07-22Rendering looks pretty goodjaseg1-0/+7
2023-07-21WIPjaseg4-25/+37
2023-07-21symbol pin rendering worksjaseg2-14/+61
2023-07-21WIPjaseg2-35/+26
2023-07-21WIPjaseg4-96/+69
2023-07-21WIPjaseg1-1/+5
2023-07-21WIPjaseg3-46/+89
2023-07-21Schematics WIPjaseg3-54/+123
2023-07-21Kicad schematic rendering WIPjaseg3-26/+82
generated by cgit (git 2.34.1) at 2024-12-12 11:35:50 +0000