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2023-11-14Bump version to v1.2.0v1.2.0jaseg1-1/+1
2023-11-14Make new test files passjaseg5-14/+139
2023-11-14Fix failing testsjaseg2-12/+21
2023-11-14Small bugfixjaseg1-2/+2
2023-11-14Calculate out all aperture macros by default.jaseg6-75/+65
There are just too many severely buggy implementations around. Today I ran into problems with both gerbv and with whatever JLC uses. You can still export macros with raw expressions by setting a flag in the export FileSettings.
2023-11-14aperture macros: work around gerbv/jlc wonkinessjaseg9-78/+216
2023-11-14Remove debug printjaseg1-1/+0
2023-11-14aperture macros: Add expression simplificationjaseg1-20/+3
2023-11-14Aperture macro expression simplification WIPjaseg3-16/+127
2023-11-14Make sure we asterisk-terminate all G0x commands.jaseg1-3/+3
While this is common in the wild, not terminating them violates the spec. It also breaks JLCPCB pretty badly. It seems their human review process uses a Gerber viewer that like most can handle this, and won't notice anything out of the ordinary, but then their photoplotter chokes on this and literally stops plotting the file, discarding anything that is after that line. This error is then apparently ignored and the resulting broken boards shipped to the customer.
2023-11-14Split CLI into pretty svg and layer export sub-commandsjaseg1-1/+34
2023-11-14pretty svg export: Mirror board bottom sidejaseg1-1/+7
2023-11-14Add JLCPCB KiCad Gerber X2/aperture macro test filesjaseg45-0/+45534
2023-11-14Add JLCPCB/FAB-3000 example gerbersjaseg11-0/+22631
2023-11-14Add P-CAD 2006 example gerbersjaseg13-0/+34535
2023-10-27Bump version to v1.1.0v1.1.0jaseg1-1/+1
2023-10-27ci: Disable tests for now, since upstream kicad-cli is broken.jaseg1-40/+42
2023-10-27Work around pip now requiring a new random feature switch to workjaseg1-5/+5
...for no good reason except to annoy anyone using it in a container.
2023-10-26Fix failing test casesjaseg9-51/+107
2023-10-26Move coil stuff to separate repojaseg15-4589/+0
2023-10-26Fix all failing tests that don't involve kicad-clijaseg10-154/+78
2023-10-20WIPjaseg4-81/+390
2023-10-20Update coil generator for the board house's latest fitjaseg1-118/+76
2023-10-20Test board fixesjaseg2-23/+27
2023-10-18Improve mouse bite spacing for JLCjaseg1-4/+5
2023-10-18Optimize coil model mesh precisionjaseg1-20/+95
2023-10-18WIPjaseg1-16/+19
2023-10-16Make coil test board more amenable to our favorite fabjaseg1-34/+129
2023-10-13Update sims & genjaseg4-69/+222
2023-10-12Fix trace orientationjaseg1-2/+2
2023-10-12Update gen scriptjaseg1-3/+3
2023-10-12Add coil test board genjaseg3-7/+388
2023-10-11Get self capacitance simulation to workjaseg4-2/+340
2023-10-10Give notebook a sensible namejaseg1-0/+0
2023-10-10Run more simsjaseg4-21/+824
2023-10-09Coupling sims workjaseg3-81/+348
2023-10-09magnetic sim agreees with calculations nowjaseg4-56/+96
2023-10-06Try to fix mesh exportjaseg1-17/+66
2023-10-06Try to fix mesh fragmentationjaseg1-8/+14
2023-10-06Mesh WIPjaseg2-4/+10
2023-10-06Add missing simulation yamlsjaseg5-3/+151
2023-10-04EM solver WIPjaseg1-2/+73
2023-09-29mag mesh gen looks goodjaseg1-18/+49
2023-09-29Add sim filesjaseg5-4/+632
2023-09-27mesh gen worksjaseg1-5/+11
2023-09-26WIPjaseg2-102/+178
2023-09-26cli: Add kicad schematic svg renderingjaseg6-42/+98
2023-09-22WiPjaseg3-0/+117
2023-09-22WIPjaseg6-119/+213
2023-09-22Trace connectivity WIPjaseg4-48/+146
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