Fix tests

5 files changed, 12 insertions, 9 deletions

diff --git a/gerbonara/tests/conftest.py b/gerbonara/tests/conftest.py
index 131ca28..b999027 100644
--- a/gerbonara/tests/conftest.py
+++ b/gerbonara/tests/conftest.py
@@ -3,7 +3,7 @@ from pathlib import Path
 
 import pytest
 
-from .image_support import ImageDifference
+from .image_support import ImageDifference, run_cargo_cmd
 
 def pytest_assertrepr_compare(op, left, right):
     if isinstance(left, ImageDifference) or isinstance(right, ImageDifference):
@@ -28,3 +28,8 @@ def pytest_sessionstart(session):
     # on coordinator
     for f in chain(fail_dir.glob('*.gbr'), fail_dir.glob('*.png')):
         f.unlink()
+
+    try:
+        run_cargo_cmd('resvg', '--help')
+    except FileNotFoundError:
+        pytest.exit('resvg binary not found, aborting test.', 2)
diff --git a/gerbonara/tests/image_support.py b/gerbonara/tests/image_support.py
index 8941f82..862baf5 100644
--- a/gerbonara/tests/image_support.py
+++ b/gerbonara/tests/image_support.py
@@ -104,6 +104,7 @@ def gerbv_export(in_gbr, out_svg, export_format='svg', origin=(0, 0), size=(6, 6
     cachefile = cachedir / f'{digest}.svg'
 
     if not cachefile.is_file():
+        print(f'Building cache for {Path(in_gbr).name}')
         # NOTE: gerbv seems to always export 'clear' polarity apertures as white, irrespective of --foreground, --background
         # and project file color settings.
         # TODO: File issue upstream.
@@ -138,6 +139,8 @@ def gerbv_export(in_gbr, out_svg, export_format='svg', origin=(0, 0), size=(6, 6
                 f'--foreground={fg}',
                 '-o', str(cachefile), '-p', f.name]
             subprocess.run(cmd, check=True, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
+    else:
+        print(f'Re-using cache for {Path(in_gbr).name}')
     shutil.copy(cachefile, out_svg)
 
 @contextmanager
diff --git a/gerbonara/tests/resources/example_coincident_hole.gbr b/gerbonara/tests/resources/example_coincident_hole.gbr
index 4f896ea..3adef36 100644
--- a/gerbonara/tests/resources/example_coincident_hole.gbr
+++ b/gerbonara/tests/resources/example_coincident_hole.gbr
@@ -1,7 +1,6 @@
 G04 ex2: overlapping*
 %FSLAX24Y24*%
 %MOMM*%
-%SRX1Y1I0.000J0.000*%
 %ADD10C,1.00000*%
 G01*
 %LPD*%
@@ -21,4 +20,4 @@ X10000Y50000D01*
 G04 second fully coincident linear segment*
 X0D01*
 G37*
-M02*
\ No newline at end of file
+M02*
diff --git a/gerbonara/tests/test_excellon.py b/gerbonara/tests/test_excellon.py
index 3221439..addf89e 100644
--- a/gerbonara/tests/test_excellon.py
+++ b/gerbonara/tests/test_excellon.py
@@ -31,8 +31,8 @@ from .utils import *
 from ..utils import Inch, MM
 
 REFERENCE_FILES = {
-        'easyeda/Gerber_Drill_NPTH.DRL': (None, None),
-        'easyeda/Gerber_Drill_PTH.DRL': (None, 'easyeda/Gerber_TopLayer.GTL'),
+        'easyeda/Gerber_Drill_NPTH.DRL': (('inch', 'leading', 4), None),
+        'easyeda/Gerber_Drill_PTH.DRL': (('inch', 'leading', 4), 'easyeda/Gerber_TopLayer.GTL'),
         # Altium uses an excellon format specification format that gerbv doesn't understand, so we have to fix that.
         'altium-composite-drill/NC Drill/LimeSDR-QPCIe_1v2-SlotHoles.TXT': (('mm', 'trailing', 4), None),
         'altium-composite-drill/NC Drill/LimeSDR-QPCIe_1v2-RoundHoles.TXT': (('mm', 'trailing', 4), 'altium-composite-drill/Gerber/LimeSDR-QPCIe_1v2.GTL'),
@@ -57,7 +57,6 @@ REFERENCE_FILES = {
 def test_round_trip(reference, tmpfile):
     reference, (unit_spec, _) = reference
     tmp = tmpfile('Output excellon', '.drl')
-    print('unit spec', unit_spec)
 
     f = ExcellonFile.open(reference)
     f.save(tmp)
@@ -79,7 +78,6 @@ def test_first_level_idempotence_svg(reference, tmpfile):
     tmp = tmpfile('Output excellon', '.drl')
     ref_svg = tmpfile('Reference SVG render', '.svg')
     out_svg = tmpfile('Output SVG render', '.svg')
-    print('unit spec', unit_spec)
 
     a = ExcellonFile.open(reference)
     a.save(tmp)
diff --git a/gerbonara/tests/test_rs274x.py b/gerbonara/tests/test_rs274x.py
index 04243a3..5111921 100644
--- a/gerbonara/tests/test_rs274x.py
+++ b/gerbonara/tests/test_rs274x.py
@@ -150,7 +150,6 @@ REFERENCE_FILES = [ l.strip() for l in '''
     pcb-rnd/power-art.gko
     pcb-rnd/power-art.ast
     pcb-rnd/power-art.gtl
-    pcb-rnd/power-art.lht
     pcb-rnd/power-art.gto
     pcb-rnd/power-art.gtp
     pcb-rnd/power-art.asb
@@ -206,7 +205,6 @@ REFERENCE_FILES = [ l.strip() for l in '''
     siemens-2/Gerber/SolderPasteBottom.gdo
     siemens-2/Gerber/SolderPasteTop.gdo
     siemens-2/Gerber/EtchLayerBottom.gdo
-    siemens-2/Gerber/GerberPlot.gpf
     siemens-2/Gerber/BoardOutlline.gdo
     upverter/design_export.gko
     upverter/design_export.gtl