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authorjaseg <git@jaseg.de>2023-10-12 20:44:52 +0200
committerjaseg <git@jaseg.de>2023-10-12 20:44:52 +0200
commit2a9c91b025ba0df04adb15950a9c086df14b20e7 (patch)
tree5e3e747ece2a837ec30b1514aed2d24e9a0aa1d8 /gerbonara/tests/resources/siemens-2/Gerber/BoardOutlline.gdo
parent2d4c40c0f79319a96cc68a484bf82059313b827b (diff)
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Add coil test board gen
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