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authorjaseg <git@jaseg.de>2022-06-21 14:17:08 +0200
committerjaseg <git@jaseg.de>2022-06-21 14:17:08 +0200
commit7bdbe66dc7caf3d27fd13b72a2603b7bca19762d (patch)
tree2fa0507a61b7acbdfa1fa39f2b70d9788e2d12f9 /gerbonara/tests/resources/pcb-rnd/power-art.gtl
parent71e996e8749e26dcc1385b03603344dede891782 (diff)
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Fix zip import/export and bounds for empty boardsv0.11.1
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