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authorjaseg <git-bigdata-wsl-arch@jaseg.de>2022-06-18 23:52:02 +0200
committerjaseg <git-bigdata-wsl-arch@jaseg.de>2022-06-18 23:52:02 +0200
commit4b38d0905e766e19e19103b86af1a6352c8e1bf9 (patch)
treebee4e6e8f7f80bda3b1e4bd781361d4cf76bba75 /gerbonara/gerber/tests/resources/pcb-rnd/power-art.gtl
parenta88364b7a98b6f8d8edd4f1616908ba8889485dd (diff)
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Add altium naming scheme, fix kicad scheme
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