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author | Paulo Henrique Silva <ph.silva@gmail.com> | 2019-11-25 23:50:28 -0300 |
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committer | GitHub <noreply@github.com> | 2019-11-25 23:50:28 -0300 |
commit | 281c26ec3768bf1220f042e640a41efee28f2954 (patch) | |
tree | 45716726e7d405fc70857be34d8d6d8715efa202 | |
parent | cee1fcff3ac8c15e8888dd0d4738c3c7f1db196d (diff) | |
parent | b75d2f8d90c867e1e8c5ec37ab8650ea00dc0012 (diff) | |
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Merge pull request #101 from chintal/outline
Add hook for outline layer to PCB class
-rw-r--r-- | gerber/pcb.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gerber/pcb.py b/gerber/pcb.py index ba15161..56deaa3 100644 --- a/gerber/pcb.py +++ b/gerber/pcb.py @@ -95,6 +95,12 @@ class PCB(object): ('top', 'bottom', 'internal')])) @property + def outline_layer(self): + for layer in self.layers: + if layer.layer_class == 'outline': + return layer + + @property def layer_count(self): """ Number of *COPPER* layers """ |