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| author | Paulo Henrique Silva <ph.silva@gmail.com> | 2019-11-25 23:50:28 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-25 23:50:28 -0300 |
| commit | 281c26ec3768bf1220f042e640a41efee28f2954 (patch) | |
| tree | 45716726e7d405fc70857be34d8d6d8715efa202 /.github/workflows/pcb-tools.yml | |
| parent | cee1fcff3ac8c15e8888dd0d4738c3c7f1db196d (diff) | |
| parent | b75d2f8d90c867e1e8c5ec37ab8650ea00dc0012 (diff) | |
| download | gerbonara-281c26ec3768bf1220f042e640a41efee28f2954.tar.gz gerbonara-281c26ec3768bf1220f042e640a41efee28f2954.tar.bz2 gerbonara-281c26ec3768bf1220f042e640a41efee28f2954.zip | |
Merge pull request #101 from chintal/outline
Add hook for outline layer to PCB class
Diffstat (limited to '.github/workflows/pcb-tools.yml')
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