blob: b766488a91281a5fe61eb95aac11473873cb79aa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
|
/* Megumin LED display firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "global.h"
#include "adc.h"
volatile unsigned int sys_time = 0;
volatile unsigned int sys_time_seconds = 0;
void TIM1_BRK_UP_TRG_COM_Handler() {
TIM1->SR &= ~TIM_SR_UIF_Msk;
}
int main(void) {
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR&RCC_CR_HSERDY));
RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR&RCC_CR_PLLRDY));
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
SystemCoreClockUpdate();
SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
/* Turn on lots of neat things */
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_FLITFEN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN| RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM1EN;;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
GPIOA->MODER |=
(3<<GPIO_MODER_MODER0_Pos) /* PA0 - Vmeas_A to ADC */
| (3<<GPIO_MODER_MODER1_Pos) /* PA1 - Vmeas_B to ADC */
| (1<<GPIO_MODER_MODER2_Pos) /* PA2 - LOAD */
| (1<<GPIO_MODER_MODER3_Pos) /* PA3 - CH0 */
| (1<<GPIO_MODER_MODER4_Pos) /* PA4 - CH3 */
| (0<<GPIO_MODER_MODER5_Pos) /* PA5 - TP1 */
| (1<<GPIO_MODER_MODER6_Pos) /* PA6 - CH2 */
| (1<<GPIO_MODER_MODER7_Pos) /* PA7 - CH1 */
| (0<<GPIO_MODER_MODER9_Pos) /* PA9 - TP2 */
| (0<<GPIO_MODER_MODER10_Pos);/* PA10 - TP3 */
/* Set shift register IO GPIO output speed */
GPIOA->OSPEEDR |=
(2<<GPIO_OSPEEDR_OSPEEDR2_Pos) /* LOAD */
| (2<<GPIO_OSPEEDR_OSPEEDR3_Pos) /* CH0 */
| (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* CH3 */
| (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* CH2 */
| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos); /* CH1 */
/* Setup CC1 and CC2. CC2 generates the LED drivers' STROBE, CC1 triggers the IRQ handler */
TIM1->BDTR = TIM_BDTR_MOE;
TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 */
TIM1->CCER = TIM_CCER_CC4E;
TIM1->CCR4 = 1;
TIM1->DIER = TIM_DIER_UIE;
TIM1->PSC = SystemCoreClock/1000000 - 1; /* 1.0us/tick */
TIM1->ARR = 20-1; /* 20us */
/* Preload all values */
TIM1->EGR |= TIM_EGR_UG;
TIM1->CR1 = TIM_CR1_ARPE;
/* And... go! */
TIM1->CR1 |= TIM_CR1_CEN;
void set_outputs(uint8_t val) {
int a=!!(val&1), b=!!(val&2), c=!!(val&4), d=!!(val&8);
GPIOA->ODR &= ~(!a<<3 | !b<<7 | c<<6 | d<<4);
GPIOA->ODR |= a<<3 | b<<7 | !c<<6 | !d<<4;
}
set_outputs(0);
adc_init();
uint8_t out_state = 0x01;
#define DEBOUNCE 100
int debounce_ctr = 0;
int val_last = 0;
int ctr = 0;
#define RESET 1000
int reset_ctr = 0;
while (42) {
#define FOO 500000
if (reset_ctr)
reset_ctr--;
else
set_outputs(0);
if (debounce_ctr) {
debounce_ctr--;
} else {
int val = !!(GPIOA->IDR & 1);
debounce_ctr = DEBOUNCE;
if (val != val_last) {
if (val)
set_outputs(out_state & 0xf);
else
set_outputs(out_state >> 4);
reset_ctr = RESET;
val_last = val;
ctr++;
if (ctr == 100) {
ctr = 0;
out_state = out_state<<1 | out_state>>7;
}
}
}
/*
for (int i=0; i<FOO; i++) ;
set_outputs(0x1);
for (int i=0; i<FOO; i++) ;
set_outputs(0x2);
for (int i=0; i<FOO; i++) ;
set_outputs(0x4);
for (int i=0; i<FOO; i++) ;
set_outputs(0x8);
*/
//for (int i=0; i<8*FOO; i++) ;
//GPIOA->ODR ^= 4;
}
}
void NMI_Handler(void) {
}
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
asm volatile ("bkpt");
}
void SVC_Handler(void) {
}
void PendSV_Handler(void) {
}
void SysTick_Handler(void) {
static int n = 0;
sys_time++;
if (n++ == 1000) {
n = 0;
sys_time_seconds++;
}
}
|
