From 5da6e46739689cab3827ca2c81e1651eeaf59d49 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.net>
Date: Wed, 9 Jan 2019 22:57:11 +0900
Subject: Fix up scope mode

---
 fw/adc.c       | 12 +++++++++---
 fw/main.c      |  4 +++-
 fw/openocd.cfg |  5 +++--
 3 files changed, 15 insertions(+), 6 deletions(-)

(limited to 'fw')

diff --git a/fw/adc.c b/fw/adc.c
index 1358e82..149b1a7 100644
--- a/fw/adc.c
+++ b/fw/adc.c
@@ -38,12 +38,12 @@ void adc_configure_scope_mode(uint8_t channel_mask, int sampling_interval_ns) {
 	/* First, disable trigger timer, DMA and ADC in case we're reconfiguring on the fly. */
     TIM1->CR1 &= ~TIM_CR1_CEN;
     ADC1->CR &= ~ADC_CR_ADSTART;
-    DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Enable channel */
+    DMA1_Channel1->CCR &= ~DMA_CCR_EN;
 
 	/* keep track of current mode in global variable */
 	st.adc_mode = ADC_SCOPE;
 
-	adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]), false);
+	adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]), true);
 
     /* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
     ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
@@ -59,7 +59,9 @@ void adc_configure_scope_mode(uint8_t channel_mask, int sampling_interval_ns) {
 	/* Perform self-calibration */
     ADC1->CR |= ADC_CR_ADCAL;
     while (ADC1->CR & ADC_CR_ADCAL)
+        ;
 	/* Enable conversion */
+    ADC1->CR |= ADC_CR_ADEN;
     ADC1->CR |= ADC_CR_ADSTART;
 
 	if (sampling_interval_ns == SAMPLE_FAST)
@@ -78,7 +80,7 @@ void adc_configure_monitor_mode(int oversampling, int ivl_us, int mean_aggregate
 	/* First, disable trigger timer, DMA and ADC in case we're reconfiguring on the fly. */
     TIM1->CR1 &= ~TIM_CR1_CEN;
     ADC1->CR &= ~ADC_CR_ADSTART;
-    DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Enable channel */
+    DMA1_Channel1->CCR &= ~DMA_CCR_EN;
 
 	/* keep track of current mode in global variable */
 	st.adc_mode = ADC_MONITOR;
@@ -162,6 +164,9 @@ static void adc_timer_init(int psc, int ivl) {
 void DMA1_Channel1_IRQHandler(void) {
     /* Clear the interrupt flag */
     DMA1->IFCR |= DMA_IFCR_CGIF1;
+    
+    if (st.adc_mode == ADC_SCOPE)
+        return;
 
     for (int i=0; i<NCH; i++)
         st.adc_aggregate[i] += adc_buf[i];
@@ -202,6 +207,7 @@ void DMA1_Channel1_IRQHandler(void) {
 		if (st.detector.len_ctr - st.detector.committed_len_ctr > st.detector.base_interval_cycles) {
 			st.detector.committed_len_ctr = st.detector.len_ctr;
 			st.detector.symbol = xfr_8b10b_feed_bit((struct state_8b10b_dec *)&st.detector.rx8b10b, st.detector.bit);
+            //if (st.detector.symbol != -DECODING_IN_PROGRESS)
 		}
 
 		if (st.detector.debounce_ctr == 0) {
diff --git a/fw/main.c b/fw/main.c
index 0f34f7e..d4bf44d 100644
--- a/fw/main.c
+++ b/fw/main.c
@@ -69,7 +69,9 @@ int main(void) {
     }
     set_outputs(0);
 
-	adc_configure_monitor_mode(0 /*no oversampling*/, 20 /*us*/, 10000/20 /*mean window size*/);
+    /* FIXME DEBUG */
+//	adc_configure_monitor_mode(0 /*no oversampling*/, 20 /*us*/, 10000/20 /*mean window size*/);
+    adc_configure_scope_mode(MASK_VMEAS_A, 10000);
 
     uint8_t out_state = 0x01;
 #define DEBOUNCE 100
diff --git a/fw/openocd.cfg b/fw/openocd.cfg
index 4c52fdc..ce164b7 100644
--- a/fw/openocd.cfg
+++ b/fw/openocd.cfg
@@ -1,5 +1,6 @@
-telnet_port 4444
-gdb_port 3333
+telnet_port 4445
+gdb_port 3334
+tcl_port 6667
 
 source [find interface/stlink-v2.cfg]
 #interface jlink
-- 
cgit