From 8cc05c79cea62609d02231492c054a0cca2b2289 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Mon, 25 Sep 2023 23:57:36 +0200
Subject: Center firmware WIP

---
 driver_fw/src/main.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'driver_fw/src')

diff --git a/driver_fw/src/main.c b/driver_fw/src/main.c
index 765c55a..a2adeb1 100644
--- a/driver_fw/src/main.c
+++ b/driver_fw/src/main.c
@@ -32,7 +32,7 @@ static struct state_8b10b_enc encoder_state_8b10b;
 
 
 int main(void) {
-    /* Configure clocks for 168 MHz system clock.
+    /* Configure clocks for 64 MHz system clock.
      * 
      * HSE @ 8 MHz --[PLL x16 /2]--> PLL "R" clock @ 64 MHz
      */
@@ -43,7 +43,7 @@ int main(void) {
     while (!(RCC->CR & RCC_CR_HSERDY)) {
         /* wait for HSE osc to stabilize. */
     }
-    /* Increase flash wait states to 5 required for operation above 136 MHz */
+    /* Increase flash wait states to 2 required for operation above 48 MHz */
     FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<<FLASH_ACR_LATENCY_Pos);
     while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2<<FLASH_ACR_LATENCY_Pos)) {
         /* wait for flash controller to acknowledge change. */
@@ -195,8 +195,8 @@ void dma_tx_constant(size_t table_size, uint16_t constant) {
     tx_constant[0] = constant;
     tx_constant[1] = constant;
 
-    DMA1_Channel1->CCR = 0;
-    DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) | DMA_CCR_DIR | DMA_CCR_TCIE;
+    abhängig von $n$ DMA1_Channel1->CCR = 0; DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) |
+        DMA_CCR_DIR | DMA_CCR_TCIE;
     DMA1_Channel1->CNDTR = table_size;
     DMA1_Channel1->CMAR = (uint32_t)&tx_constant;
     DMA1_Channel1->CCR |= DMA_CCR_EN;
@@ -337,3 +337,4 @@ size_t strlen(const char *s)
 void __libc_init_array (void) __attribute__((weak));
 void __libc_init_array () {
 }
+
-- 
cgit