From 8e42ca09787ab7698a068df71e37f388ca1b2e9f Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Mon, 2 Oct 2023 14:50:03 +0200
Subject: Transmission works including sync and whitening

---
 center_fw/.gdbinit         |  5 +++++
 center_fw/match_test.ipynb | 21 +++++++++++++++++++++
 center_fw/src/main.c       | 12 +++++++-----
 3 files changed, 33 insertions(+), 5 deletions(-)

(limited to 'center_fw')

diff --git a/center_fw/.gdbinit b/center_fw/.gdbinit
index d64d48e..766b39d 100644
--- a/center_fw/.gdbinit
+++ b/center_fw/.gdbinit
@@ -28,3 +28,8 @@ define jdump
         continue
     end
 end
+
+define reconnect
+    disconnect
+    target extended-remote 192.168.1.97:2022
+end
diff --git a/center_fw/match_test.ipynb b/center_fw/match_test.ipynb
index f23d127..9b5d9f2 100644
--- a/center_fw/match_test.ipynb
+++ b/center_fw/match_test.ipynb
@@ -1569,6 +1569,27 @@
     "1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0110001011 1000111010 0001011110 1000011001 0111001011 0010010111\n",
     "1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0110001011 1000111010 0001011110 1000011001 0111001011 1100000110"
    ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 221,
+   "id": "bfd80ba5-b943-4eaa-894c-f87c30ab7735",
+   "metadata": {},
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;3m00 0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;3m1 11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;2m00 \u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0 \u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;3m000\u001b[38;5;4m1111 \u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0"
+     ]
+    }
+   ],
+   "source": [
+    "bits = np.fromfile('/tmp/dump_bit.bin', dtype=np.uint8)\n",
+    "pos, = np.fromfile('/tmp/dump_bit_idx.bin', dtype=np.uint32)\n",
+    "bits = bits[:pos]\n",
+    "print_rl(*bits, break_groups={'00000', '11111'}, split_each=10, split_offset=0)"
+   ]
   }
  ],
  "metadata": {
diff --git a/center_fw/src/main.c b/center_fw/src/main.c
index a4f7d9e..68a787f 100644
--- a/center_fw/src/main.c
+++ b/center_fw/src/main.c
@@ -155,11 +155,15 @@ int main(void) {
         if (packet_received) {
             if (rng_reset) {
                 packet_rng_state = xorshift32(1);
+                rng_reset = false;
+                GPIOB->BSRR = (1<<7);
+            } else {
+                GPIOB->BRR = (1<<7);
             }
 
             for(size_t i=0; i<sizeof(rx_buf.packet); i++) {
                 packet_rng_state = xorshift32(packet_rng_state);
-                // rx_buf.bytes[i] ^= packet_rng_state; FIXME DEBUG
+                rx_buf.bytes[i] ^= packet_rng_state;
             }
 
             uint32_t crc_state = crc32_reset();
@@ -169,6 +173,7 @@ int main(void) {
             crc_state = crc32_finalize(crc_state);
 
             if (crc_state == rx_buf.packet.crc) {
+                GPIOA->BSRR = (1<<6);
                 /* good packet received */
                 int val = rx_buf.packet.brightness[CONFIG_MODULE_ADDRESS/2];
                 if (CONFIG_MODULE_ADDRESS & 1) {
@@ -178,6 +183,7 @@ int main(void) {
                 channel_mask = rx_buf.packet.channels[CONFIG_MODULE_ADDRESS];
 
             } else {
+                GPIOA->BRR = (1<<6);
                 errors.crc_errors++;
             }
 
@@ -203,7 +209,6 @@ void gdb_dump(void) {
 void ADC1_IRQHandler(void) {
     static int phase = 0;
     static int last_bit = 0;
-    GPIOB->BSRR = (1<<7);
 
     /* Read sample and apply threshold */
     int sample = ADC1->DR; /* resets the EOC interrupt flag */
@@ -300,11 +305,9 @@ void ADC1_IRQHandler(void) {
     if (phase == SAMPLES_PER_BAUD - LED_DEAD_TIME || bit != last_bit || bit_margin < MIN_RECTIFIER_MARGIN) { /* reset */
         GPIOA->BRR = (1<<11); /* RECT1 */
         GPIOC->BRR = (1<<15); /* RECT2 */
-        GPIOA->BRR = (1<<6);
 
     } else if (phase == LED_DEAD_TIME) { /* set */
         if (bit) {
-            GPIOA->BSRR = (1<<6);
 #ifndef DEBUG_DISABLE_DRIVERS
             GPIOC->BSRR = (1<<15); /* RECT2 */
 #endif
@@ -329,7 +332,6 @@ void ADC1_IRQHandler(void) {
     }
 
     last_bit = bit;
-    GPIOB->BRR = (1<<7);
 }
 
 void TIM14_IRQHandler(void) {
-- 
cgit