From 77549cbb2f155d465eb68297d75259a854989c7f Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Sat, 4 Nov 2023 18:09:55 +0100
Subject: WIP towards board order

---
 center_fw/src/main.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'center_fw/src')

diff --git a/center_fw/src/main.c b/center_fw/src/main.c
index 68a787f..c066297 100644
--- a/center_fw/src/main.c
+++ b/center_fw/src/main.c
@@ -35,7 +35,7 @@ static volatile struct state_8b10b_dec st_8b10b_dec;
 #define CONFIG_MODULE_ADDRESS 0
 #endif /* CONFIG_MODULE_ADDRESS */
 
-#define DEBUG_DISABLE_DRIVERS 1
+//define DEBUG_DISABLE_DRIVERS 1
 
 
 volatile union {
@@ -156,9 +156,6 @@ int main(void) {
             if (rng_reset) {
                 packet_rng_state = xorshift32(1);
                 rng_reset = false;
-                GPIOB->BSRR = (1<<7);
-            } else {
-                GPIOB->BRR = (1<<7);
             }
 
             for(size_t i=0; i<sizeof(rx_buf.packet); i++) {
@@ -179,7 +176,7 @@ int main(void) {
                 if (CONFIG_MODULE_ADDRESS & 1) {
                     val >>= 4;
                 }
-                global_brightness = val;
+                global_brightness = val&0x0f;
                 channel_mask = rx_buf.packet.channels[CONFIG_MODULE_ADDRESS];
 
             } else {
@@ -238,6 +235,7 @@ void ADC1_IRQHandler(void) {
 
     /* Trigger 8b10b sample */ 
     if (phase == SAMPLING_PHASE) {
+        GPIOB->BSRR = (1<<7);
         adc_dump[adc_dump_pos] |= 0x80;
 
         bit_dump[bit_dump_pos] = bit;
@@ -260,7 +258,9 @@ void ADC1_IRQHandler(void) {
             }
 
             if (rc < 0) {
-                if (rc == -K28_1) {
+                if (rc == -K23_7) {
+                    /* ignore. */
+                } else if (rc == -K28_1) {
                     rng_reset = true;
                     rx_pos = 0;
 
@@ -331,6 +331,7 @@ void ADC1_IRQHandler(void) {
         TIM14->CR1 |= TIM_CR1_CEN;
     }
 
+    GPIOB->BRR = (1<<7);
     last_bit = bit;
 }
 
-- 
cgit