From fec02919c34a00e8829fed788fea33debaae6884 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Thu, 25 May 2023 22:23:09 +0200
Subject: Driver Filter WIP

---
 center/center.kicad_pro | 53 +++++++++++++++++++++++++++++++++++--------------
 1 file changed, 38 insertions(+), 15 deletions(-)

(limited to 'center/center.kicad_pro')

diff --git a/center/center.kicad_pro b/center/center.kicad_pro
index f72e7e1..c1f3153 100644
--- a/center/center.kicad_pro
+++ b/center/center.kicad_pro
@@ -1,5 +1,6 @@
 {
   "board": {
+    "3dviewports": [],
     "design_settings": {
       "defaults": {
         "board_outline_line_width": 0.15,
@@ -455,7 +456,7 @@
   "net_settings": {
     "classes": [
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -469,10 +470,10 @@
         "track_width": 0.25,
         "via_diameter": 0.8,
         "via_drill": 0.4,
-        "wire_width": 6.0
+        "wire_width": 6
       },
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.6,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -481,27 +482,49 @@
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
         "name": "HV",
-        "nets": [
-          "+VSW",
-          "/Q0",
-          "/Q1",
-          "/Q2",
-          "/Q3",
-          "/VIN_A",
-          "/VIN_B"
-        ],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 0.25,
         "via_diameter": 0.8,
         "via_drill": 0.4,
-        "wire_width": 6.0
+        "wire_width": 6
       }
     ],
     "meta": {
-      "version": 2
+      "version": 3
     },
-    "net_colors": null
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
+      {
+        "netclass": "HV",
+        "pattern": "+VSW"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q0"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q1"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q2"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q3"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/VIN_A"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/VIN_B"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {
-- 
cgit