From 7e1d100f1b3ab2ce76015f333d10279f6eee6d37 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.net>
Date: Mon, 26 Nov 2018 14:28:04 +0900
Subject: PCB designs R01 finished (not reviewed yet)

---
 center/center-cache.lib | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'center/center-cache.lib')

diff --git a/center/center-cache.lib b/center/center-cache.lib
index aed4919..4817fa8 100644
--- a/center/center-cache.lib
+++ b/center/center-cache.lib
@@ -43,6 +43,23 @@ X Pin_4 4 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Connector_TestPoint
+#
+DEF Connector_TestPoint TP 0 30 N N 1 F N
+F0 "TP" 0 270 50 H V C CNN
+F1 "Connector_TestPoint" 0 200 50 H V C CNN
+F2 "" 200 0 50 H I C CNN
+F3 "" 200 0 50 H I C CNN
+$FPLIST
+ Pin*
+ Test*
+$ENDFPLIST
+DRAW
+C 0 130 30 0 1 0 N
+X 1 1 0 0 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # Device_CP_Small
 #
 DEF Device_CP_Small C 0 10 N N 1 F N
-- 
cgit