From fec02919c34a00e8829fed788fea33debaae6884 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Thu, 25 May 2023 22:23:09 +0200
Subject: Driver Filter WIP

---
 center-control/center.kicad_pro | 68 +++++++++++++++++++++++++----------------
 1 file changed, 42 insertions(+), 26 deletions(-)

(limited to 'center-control/center.kicad_pro')

diff --git a/center-control/center.kicad_pro b/center-control/center.kicad_pro
index d8c5259..ed0e0e4 100644
--- a/center-control/center.kicad_pro
+++ b/center-control/center.kicad_pro
@@ -1,5 +1,6 @@
 {
   "board": {
+    "3dviewports": [],
     "design_settings": {
       "defaults": {
         "board_outline_line_width": 0.15,
@@ -58,18 +59,8 @@
       "drc_exclusions": [
         "clearance|180095001|115440000|46b665bc-ec0c-494f-bc83-df770871abd3|bcb40fa3-b41b-411d-b561-9bd80d99e072",
         "clearance|180850000|115440000|bcb40fa3-b41b-411d-b561-9bd80d99e072|46b665bc-ec0c-494f-bc83-df770871abd3",
-        "clearance|180850000|115440000|e6629e01-bc20-4ee6-b773-723f548b3816|bcb40fa3-b41b-411d-b561-9bd80d99e072",
         "courtyards_overlap|195765866|108222151|00000000-0000-0000-0000-00005de7bda7|00000000-0000-0000-0000-00005de9b522",
-        "text_thickness|193350000|117925000|e1e8791b-f102-4509-9948-1986c49e1265|00000000-0000-0000-0000-000000000000",
-        "text_thickness|194150000|82775000|d9972955-3442-4947-bb4c-b7565fbe6bb7|00000000-0000-0000-0000-000000000000",
-        "track_dangling|160600000|94125000|265873b1-486e-477a-b6cf-ce1300359272|00000000-0000-0000-0000-000000000000",
-        "track_dangling|168700000|86225000|1b7d2820-9357-474d-8097-03ccbdacd975|00000000-0000-0000-0000-000000000000",
-        "track_dangling|168700000|86225000|d339ecce-3fd9-4e97-96f1-611260cda1c4|00000000-0000-0000-0000-000000000000",
-        "track_dangling|174325000|115225000|f1872d20-0bb0-4746-b8b5-e9be9708c74c|00000000-0000-0000-0000-000000000000",
-        "track_dangling|177400000|77400000|12b87ea1-4c32-4148-a860-bc0c28c9a20b|00000000-0000-0000-0000-000000000000",
-        "track_dangling|179362500|82312500|f8ba382a-588f-4da9-b278-dfa04215c18f|00000000-0000-0000-0000-000000000000",
-        "track_dangling|182975000|75575000|3ffd4088-d618-4ea4-bb0d-96c1f0c66d24|00000000-0000-0000-0000-000000000000",
-        "track_dangling|186857500|77625000|cc9ece8d-547f-40b0-add3-a0bd3d50fd8a|00000000-0000-0000-0000-000000000000"
+        "text_thickness|193350000|117925000|e1e8791b-f102-4509-9948-1986c49e1265|00000000-0000-0000-0000-000000000000"
       ],
       "meta": {
         "filename": "board_design_settings.json",
@@ -78,6 +69,7 @@
       "rule_severities": {
         "annular_width": "error",
         "clearance": "error",
+        "connection_width": "warning",
         "copper_edge_clearance": "error",
         "copper_sliver": "warning",
         "courtyards_overlap": "error",
@@ -86,6 +78,7 @@
         "drill_out_of_range": "error",
         "duplicate_footprints": "warning",
         "extra_footprint": "warning",
+        "footprint": "error",
         "footprint_type_mismatch": "ignore",
         "hole_clearance": "error",
         "hole_near_hole": "error",
@@ -129,6 +122,7 @@
         "allow_microvias": false,
         "max_error": 0.005,
         "min_clearance": 0.0,
+        "min_connection": 0.0,
         "min_copper_edge_clearance": 0.01,
         "min_hole_clearance": 0.0,
         "min_hole_to_hole": 0.25,
@@ -455,7 +449,7 @@
   "net_settings": {
     "classes": [
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -469,10 +463,10 @@
         "track_width": 0.25,
         "via_diameter": 0.8,
         "via_drill": 0.4,
-        "wire_width": 6.0
+        "wire_width": 6
       },
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.6,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -481,27 +475,49 @@
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
         "name": "HV",
-        "nets": [
-          "+VSW",
-          "/Q0",
-          "/Q1",
-          "/Q2",
-          "/Q3",
-          "/VIN_A",
-          "/VIN_B"
-        ],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 0.25,
         "via_diameter": 0.8,
         "via_drill": 0.4,
-        "wire_width": 6.0
+        "wire_width": 6
       }
     ],
     "meta": {
-      "version": 2
+      "version": 3
     },
-    "net_colors": null
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
+      {
+        "netclass": "HV",
+        "pattern": "+VSW"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q0"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q1"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q2"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/Q3"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/VIN_A"
+      },
+      {
+        "netclass": "HV",
+        "pattern": "/VIN_B"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {
-- 
cgit