| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-01-19 | driver: Fixup SWD header, swap driver outputs for VSW split, finish silk | jaseg | 3 | -1893/+2198 | |
| 2019-01-18 | driver: initial DRC done | jaseg | 1 | -94/+107 | |
| 2019-01-18 | driver: Finish initial routing | jaseg | 3 | -1532/+1769 | |
| 2019-01-18 | driver: Initial layout almost done | jaseg | 3 | -1677/+2168 | |
| 2019-01-17 | driver: Continue layout | jaseg | 3 | -2528/+3856 | |
| 2019-01-17 | driver: Initial layout | jaseg | 6 | -616/+8355 | |
| 2019-01-15 | Driver schematic progress | jaseg | 2 | -214/+1938 | |
| 2019-01-15 | Fix double edge issue with driver | jaseg | 1 | -9/+3 | |
| 2019-01-15 | Add initial driver schematic draft | jaseg | 7 | -0/+1581 | |
| 2019-01-13 | TIM3 working stably now | jaseg | 4 | -35/+872 | |
| 2019-01-13 | Basic timer-based blanking working | jaseg | 3 | -23/+54 | |
| 2019-01-12 | Make protocol unit tester count test cases | jaseg | 1 | -1/+6 | |
| 2019-01-12 | Protocol unit test working | jaseg | 1 | -3/+1 | |
| 2019-01-12 | bulk cmd test works | jaseg | 7 | -17/+241 | |
| 2019-01-12 | Split receiver into logical parts | jaseg | 8 | -148/+172 | |
| 2019-01-11 | Basic command comm works | jaseg | 7 | -225/+224 | |
| 2019-01-10 | Decoding and comma triggering works | jaseg | 4 | -32/+92 | |
| 2019-01-10 | Debug scope works nicely | jaseg | 5 | -30/+980 | |
| 2019-01-09 | Fix up scope mode | jaseg | 3 | -6/+15 | |
| 2018-12-24 | Initial detector logic draft | jaseg | 2 | -1/+48 | |
| 2018-12-24 | Pimp ADC measurements with voltage means | jaseg | 4 | -38/+69 | |
| 2018-12-24 | Add untested ADC mode switching code | jaseg | 5 | -37/+156 | |
| 2018-12-24 | Make center ADC work in "scope mode" | jaseg | 2 | -49/+7 | |
| 2018-12-23 | ADC working | jaseg | 15 | -46/+1898 | |
| 2018-12-22 | First AC/mux test working | jaseg | 15 | -25/+1343 | |
| 2018-12-20 | 8b10b encoder and decoder working | jaseg | 7 | -66/+272 | |
| Tested on all 24-bit inputs after sync and on ~500M of random input with and without intermediate sync | |||||
| 2018-12-20 | Add initial center firmware | jaseg | 14 | -0/+1381 | |
| 2018-11-27 | center: Add BOM | jaseg | 6 | -179/+1178 | |
| 2018-11-27 | Make geber zip filenames more descriptive | jaseg | 2 | -0/+0 | |
| 2018-11-27 | Add corner gerber exports | jaseg | 14 | -15/+4036 | |
| 2018-11-27 | Add center artwork | jaseg | 4 | -0/+80 | |
| 2018-11-27 | Add prettified gerber output | jaseg | 12 | -0/+177253 | |
| 2018-11-27 | Fix AO3400 pinout | jaseg | 17 | -1266/+17441 | |
| 2018-11-26 | center: improve silk | jaseg | 2 | -19/+109 | |
| 2018-11-26 | PCB designs R01 finished (not reviewed yet) | jaseg | 12 | -278/+10619 | |
| 2018-11-25 | center: initial schematic | jaseg | 6 | -0/+3445 | |
| 2018-11-24 | Initial commit | jaseg | 13 | -0/+3894 | |
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index : 8seg.git | |
| 8seg: Gigantic low-cost segmented alphanumeric display light installation | jaseg |
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