diff options
Diffstat (limited to 'driver_fw')
| -rw-r--r-- | driver_fw/Makefile | 6 | ||||
| -rw-r--r-- | driver_fw/main.c | 96 |
2 files changed, 70 insertions, 32 deletions
diff --git a/driver_fw/Makefile b/driver_fw/Makefile index de129d2..2d74acd 100644 --- a/driver_fw/Makefile +++ b/driver_fw/Makefile @@ -9,7 +9,7 @@ OBJCOPY := arm-none-eabi-objcopy OBJDUMP := arm-none-eabi-objdump SIZE := arm-none-eabi-size -CFLAGS = -g -Wall -std=gnu11 -O1 -fdump-rtl-expand +CFLAGS = -g -Wall -std=gnu11 -O1 -fdump-rtl-expand -Wno-discarded-qualifiers CFLAGS += -mlittle-endian -mcpu=cortex-m3 -mthumb #CFLAGS += -ffunction-sections -fdata-sections LDFLAGS = -nostartfiles @@ -22,7 +22,7 @@ LIBS = -lgcc CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000 LDFLAGS += -Tstm32_flash.ld -CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig +CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig -I../common #LDFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math ################################################### @@ -45,7 +45,7 @@ cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f103xb.h $(CMSIS_PATH)/Include/c %.dot: %.elf r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@ -main.elf: main.o startup_stm32f103xb.o system_stm32f1xx.o $(HAL_PATH)/Src/stm32f1xx_ll_utils.o cmsis_exports.o +main.elf: main.o startup_stm32f103xb.o system_stm32f1xx.o $(HAL_PATH)/Src/stm32f1xx_ll_utils.o cmsis_exports.o ../common/8b10b.o $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS) $(OBJCOPY) -O ihex $@ $(@:.elf=.hex) $(OBJCOPY) -O binary $@ $(@:.elf=.bin) diff --git a/driver_fw/main.c b/driver_fw/main.c index d814b0e..e4960c7 100644 --- a/driver_fw/main.c +++ b/driver_fw/main.c @@ -12,6 +12,8 @@ #include <string.h> #include <unistd.h> +#include <8b10b.h> + /* Part number: STM32F030F4C6 */ static volatile unsigned int sys_time; @@ -20,14 +22,23 @@ uint32_t get_tick() { return SysTick->VAL; } +static volatile struct { + int current_symbol, next_symbol; + struct state_8b10b_enc st; +} txstate; + +#define NO_SYMBOL (DECODER_RETURN_CODE_LAST + 1) + int main(void) { /* External crystal: 8MHz */ RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR&RCC_CR_HSERDY)); /* Sysclk = HCLK = 48MHz */ - RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMULL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE1_Msk & ~RCC_CFGR_PPRE2_Msk & ~RCC_CFGR_HPRE_Msk)) - | (10<<RCC_CFGR_PLLMULL_Pos) | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | (4<<RCC_CFGR_PPRE1_Pos) | (4<<RCC_CFGR_PPRE2_Pos); + RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMULL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE1_Msk & ~RCC_CFGR_PPRE2_Msk & + ~RCC_CFGR_HPRE_Msk)) + | (10<<RCC_CFGR_PLLMULL_Pos) | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | (4<<RCC_CFGR_PPRE1_Pos) | + (4<<RCC_CFGR_PPRE2_Pos); RCC->CR |= RCC_CR_PLLON; while (!(RCC->CR&RCC_CR_PLLRDY)); @@ -38,41 +49,68 @@ int main(void) { // | (4<<RCC_CFGR_PPRE1_Pos) | (4<<RCC_CFGR_PPRE2_Pos); SystemCoreClockUpdate(); - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN; + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_TIM1EN; - GPIOA->CRL = - (0<<GPIO_CRL_CNF6_Pos) | (1<<GPIO_CRL_MODE6_Pos) /* PA6 - Channel 1 low side */ - | (0<<GPIO_CRL_CNF7_Pos) | (1<<GPIO_CRL_MODE7_Pos); /* PA7 - Channel 2 low side */ + GPIOA->CRH = + (2<<GPIO_CRH_CNF8_Pos) | (1<<GPIO_CRH_MODE8_Pos); /* PA8 - low side */ - GPIOB->CRL = - (0<<GPIO_CRL_CNF0_Pos) | (1<<GPIO_CRL_MODE0_Pos) /* PB0 - Channel 1 high side */ - | (0<<GPIO_CRL_CNF1_Pos) | (1<<GPIO_CRL_MODE1_Pos); /* PB1 - Channel 2 high side */ + GPIOB->CRH = + (2<<GPIO_CRH_CNF13_Pos) | (1<<GPIO_CRH_MODE13_Pos); /* PB13 - high side */ GPIOC->CRH = (0<<GPIO_CRH_CNF13_Pos) | (1<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */ - /* Turn all outputs off */ - GPIOA->BRR |= 1<<6 | 1<<7; - GPIOB->BRR |= 1<<0 | 1<<1; - + /* TIM1 running off 24MHz APB2 clk, T=41.667ns */ + TIM1->CR1 = 0; /* Disable ARR preload (double-buffering) */ + TIM1->PSC = 24-1; /* Prescaler 24 -> f=1MHz/T=1us */ + TIM1->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */ + TIM1->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1 + preload */ + TIM1->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1E; /* Confiugre CH1 to complementary outputs */ + TIM1->BDTR = TIM_BDTR_MOE | 100<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load. + Set dead-time to 100us. */ + TIM1->CR1 |= TIM_CR1_CEN; + TIM1->ARR = 1000-1; /* Set f=1.0kHz/T=1.0ms */ + + xfr_8b10b_encode_reset(&txstate.st); + txstate.current_symbol = txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1) | 1<<10; + TIM1->EGR |= TIM_EGR_UG; + + NVIC_EnableIRQ(TIM1_UP_IRQn); + NVIC_SetPriority(TIM1_UP_IRQn, 3<<4); + + uint8_t txbuf[128]; + int txpos = -1; + /* FIXME test code */ + for (int i=0; i<sizeof(txbuf); i++) + txbuf[i] = i; + /* FIXME end test code */ while (42) { -#define FOO 100000 - for (int i=0; i<FOO; i++) ; - GPIOA->BRR |= 1<<6 | 1<<7; - GPIOB->BRR |= 1<<0 | 1<<1; - - GPIOA->BSRR |= 1<<6; - GPIOB->BSRR |= 1<<1; - - for (int i=0; i<FOO; i++) ; - GPIOA->BRR |= 1<<6 | 1<<7; - GPIOB->BRR |= 1<<0 | 1<<1; - - GPIOA->BSRR |= 1<<7; - GPIOB->BSRR |= 1<<0; + if (txstate.next_symbol == -NO_SYMBOL) { + if (txpos == -1) + txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1); + else + txstate.next_symbol = xfr_8b10b_encode(&txstate.st, txbuf[txpos]); + + txpos++; + if (txpos == sizeof(txbuf)) + txpos = -1; + } + } +} - GPIOC->ODR ^= 1<<13; +void TIM1_UP_IRQHandler() { + TIM1->SR &= ~TIM_SR_UIF; + int sym = txstate.current_symbol; + int bit = sym&1; + sym >>= 1; + if (sym == 1) { /* last bit shifted out */ + sym = txstate.next_symbol | 1<<10; + txstate.next_symbol = -NO_SYMBOL; } + txstate.current_symbol = sym; + + TIM1->CCR1 = bit ? 0xffff : 0x0000; } void NMI_Handler(void) { @@ -104,5 +142,5 @@ void MemManage_Handler() { void BusFault_Handler(void) __attribute__((naked)); void BusFault_Handler() { - asm volatile ("bkpt"); +asm volatile ("bkpt"); } |