diff options
| -rw-r--r-- | fw/adc.c | 31 | ||||
| -rw-r--r-- | fw/adc.h | 18 |
2 files changed, 48 insertions, 1 deletions
@@ -20,6 +20,7 @@ #include <stdbool.h> #include <stdlib.h> +#define DETECTOR_CHANNEL a volatile uint16_t adc_buf[ADC_BUFSIZE]; volatile struct adc_state adc_state = {0}; @@ -89,6 +90,12 @@ void adc_configure_monitor_mode(int oversampling, int ivl_us, int mean_aggregate st.mean_aggregator[0] = st.mean_aggregator[1] = st.mean_aggregator[2] = 0; st.mean_aggregate_ctr = 0; + st.detector.symbol = -1; + st.detector.bit = 0; + st.detector.base_interval_cycles = st.detector.committed_len_ctr = st.detector.len_ctr = 0; + st.detector.debounce_ctr = 0; + xfr_8b10b_reset((struct state_8b10b_dec *)&st.detector.rx8b10b); + adc_dma_init(NCH, true); /* Setup DMA and triggering: Trigger from Timer 1 Channel 4 */ @@ -190,6 +197,30 @@ void DMA1_Channel1_IRQHandler(void) { st.mean_aggregator[0] = st.mean_aggregator[1] = st.mean_aggregator[2] = 0; } + + st.detector.len_ctr++; + if (st.detector.len_ctr - st.detector.committed_len_ctr > st.detector.base_interval_cycles) { + st.detector.committed_len_ctr = st.detector.len_ctr; + st.detector.symbol = xfr_8b10b_feed_bit((struct state_8b10b_dec *)&st.detector.rx8b10b, st.detector.bit); + } + + if (st.detector.debounce_ctr == 0) { + int old_bit = st.detector.bit; + int new_bit = old_bit; + if (a < st.detector.threshold_mv - st.detector.hysteresis_mv/2) + new_bit = 0; + else if (a > st.detector.threshold_mv - st.detector.hysteresis_mv/2) + new_bit = 1; + + if (new_bit != old_bit) { + st.detector.bit = new_bit; + st.detector.debounce_ctr = st.detector.debounce_cycles; + st.detector.len_ctr = 0; + } + } else { + st.detector.debounce_ctr--; + } + st.ovs_count = 0; for (int i=0; i<NCH; i++) st.adc_aggregate[i] = 0; @@ -19,6 +19,7 @@ #define __ADC_H__ #include "global.h" +#include "8b10b.h" struct adc_measurements { int16_t adc_vcc_mv; @@ -46,7 +47,7 @@ enum sampling_mode { }; /* The weird order is to match the channels' order in the DMA buffer. Due to some configuration mistake I can't be -bothered to fix the DMA controller outputs ADC measurements off-by-one into the output buffer. */ +bothered to fix, the DMA controller outputs ADC measurements off-by-one into the output buffer. */ enum adc_channels { VREF_CH, VMEAS_A, @@ -59,6 +60,21 @@ struct adc_state { enum adc_mode adc_mode; int adc_oversampling; int mean_aggregate_len; + struct { + int threshold_mv; + int hysteresis_mv; + int debounce_cycles; + int symbol; + int base_interval_cycles; + /* private stuff */ + int bit; + int len_ctr; + int committed_len_ctr; + int debounce_ctr; + struct state_8b10b_dec rx8b10b; + } detector; + + /* private stuff */ int ovs_count; /* oversampling accumulator sample count */ uint32_t adc_aggregate[NCH]; /* oversampling accumulator */ uint32_t mean_aggregate_ctr; |