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author | jaseg <git@jaseg.net> | 2018-12-24 20:24:53 +0900 |
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committer | jaseg <git@jaseg.net> | 2018-12-24 20:24:53 +0900 |
commit | d3edf27c8933253fd7e3656fdead0f793a9a1195 (patch) | |
tree | fc41c8f9981244bd9b80a4f360a73b97d4e4914b /fw/adc.h | |
parent | c339384cbede3ddf3e88d27229baefd1d42daa86 (diff) | |
download | 8seg-d3edf27c8933253fd7e3656fdead0f793a9a1195.tar.gz 8seg-d3edf27c8933253fd7e3656fdead0f793a9a1195.tar.bz2 8seg-d3edf27c8933253fd7e3656fdead0f793a9a1195.zip |
Initial detector logic draft
Diffstat (limited to 'fw/adc.h')
-rw-r--r-- | fw/adc.h | 18 |
1 files changed, 17 insertions, 1 deletions
@@ -19,6 +19,7 @@ #define __ADC_H__ #include "global.h" +#include "8b10b.h" struct adc_measurements { int16_t adc_vcc_mv; @@ -46,7 +47,7 @@ enum sampling_mode { }; /* The weird order is to match the channels' order in the DMA buffer. Due to some configuration mistake I can't be -bothered to fix the DMA controller outputs ADC measurements off-by-one into the output buffer. */ +bothered to fix, the DMA controller outputs ADC measurements off-by-one into the output buffer. */ enum adc_channels { VREF_CH, VMEAS_A, @@ -59,6 +60,21 @@ struct adc_state { enum adc_mode adc_mode; int adc_oversampling; int mean_aggregate_len; + struct { + int threshold_mv; + int hysteresis_mv; + int debounce_cycles; + int symbol; + int base_interval_cycles; + /* private stuff */ + int bit; + int len_ctr; + int committed_len_ctr; + int debounce_ctr; + struct state_8b10b_dec rx8b10b; + } detector; + + /* private stuff */ int ovs_count; /* oversampling accumulator sample count */ uint32_t adc_aggregate[NCH]; /* oversampling accumulator */ uint32_t mean_aggregate_ctr; |