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author | jaseg <git-bigdata-wsl-arch@jaseg.de> | 2022-04-18 16:19:03 +0200 |
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committer | jaseg <git-bigdata-wsl-arch@jaseg.de> | 2022-05-08 16:47:48 +0200 |
commit | 3994a2576b073a1c3dc5dd85e95e63add8eb71a4 (patch) | |
tree | b0cf1f1f33f9057f4f39872f53d146a218b459d8 /center/components.lib | |
parent | 2e7724b9607223d84f2314c9d21cbd1111e017ec (diff) | |
download | 8seg-3994a2576b073a1c3dc5dd85e95e63add8eb71a4.tar.gz 8seg-3994a2576b073a1c3dc5dd85e95e63add8eb71a4.tar.bz2 8seg-3994a2576b073a1c3dc5dd85e95e63add8eb71a4.zip |
Update PCBs
Diffstat (limited to 'center/components.lib')
-rw-r--r-- | center/components.lib | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/center/components.lib b/center/components.lib new file mode 100644 index 0000000..1fbfcc4 --- /dev/null +++ b/center/components.lib @@ -0,0 +1,25 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# TX4138 +# +DEF TX4138 U 0 40 Y Y 1 F N +F0 "U" 0 0 50 H V C CNN +F1 "TX4138" 0 300 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -300 -400 300 600 0 1 0 f +X SW 1 500 300 200 L 50 50 1 1 I +X ILIM 2 -500 300 200 R 50 50 1 1 I +X VIN 3 -500 500 200 R 50 50 1 1 I +X GND 4 0 -600 200 U 50 50 1 1 I +X FB 5 500 100 200 L 50 50 1 1 I +X EN 6 -500 -100 200 R 50 50 1 1 I +X POK 7 500 -100 200 L 50 50 1 1 I +X BS 8 500 500 200 L 50 50 1 1 I +X ILIM 9 -500 200 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library |