driver/fw: Add missing startup and system file

2 files changed, 609 insertions, 0 deletions

diff --git a/driver_fw/startup_stm32f030x6.s b/driver_fw/startup_stm32f030x6.s
new file mode 100644
index 0000000..2f0eb42
--- /dev/null
+++ b/driver_fw/startup_stm32f030x6.s
@@ -0,0 +1,273 @@
+/**

+  ******************************************************************************

+  * @file      startup_stm32f030x6.s

+  * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc

+  * @author    MCD Application Team

+  * @version   V2.3.1

+  * @date      04-November-2016

+  * @brief     STM32F030x4/STM32F030x6 devices vector table for Atollic TrueSTUDIO toolchain.

+  *            This module performs:

+  *                - Set the initial SP

+  *                - Set the initial PC == Reset_Handler,

+  *                - Set the vector table entries with the exceptions ISR address

+  *                - Branches to main in the C library (which eventually

+  *                  calls main()).

+  *            After Reset the Cortex-M0 processor is in Thread mode,

+  *            priority is Privileged, and the Stack is set to Main.

+  ******************************************************************************

+  * 

+  * Redistribution and use in source and binary forms, with or without modification,

+  * are permitted provided that the following conditions are met:

+  *   1. Redistributions of source code must retain the above copyright notice,

+  *      this list of conditions and the following disclaimer.

+  *   2. Redistributions in binary form must reproduce the above copyright notice,

+  *      this list of conditions and the following disclaimer in the documentation

+  *      and/or other materials provided with the distribution.

+  *   3. Neither the name of STMicroelectronics nor the names of its contributors

+  *      may be used to endorse or promote products derived from this software

+  *      without specific prior written permission.

+  *

+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+  *

+  ******************************************************************************

+  */

+

+  .syntax unified

+  .cpu cortex-m0

+  .fpu softvfp

+  .thumb

+

+.global g_pfnVectors

+.global Default_Handler

+

+/* start address for the initialization values of the .data section.

+defined in linker script */

+.word _sidata

+/* start address for the .data section. defined in linker script */

+.word _sdata

+/* end address for the .data section. defined in linker script */

+.word _edata

+/* start address for the .bss section. defined in linker script */

+.word _sbss

+/* end address for the .bss section. defined in linker script */

+.word _ebss

+

+  .section .text.Reset_Handler

+  .weak Reset_Handler

+  .type Reset_Handler, %function

+Reset_Handler:

+  ldr   r0, =_estack

+  mov   sp, r0          /* set stack pointer */

+

+/* Copy the data segment initializers from flash to SRAM */

+  movs r1, #0

+  b LoopCopyDataInit

+

+CopyDataInit:

+  ldr r3, =_sidata

+  ldr r3, [r3, r1]

+  str r3, [r0, r1]

+  adds r1, r1, #4

+

+LoopCopyDataInit:

+  ldr r0, =_sdata

+  ldr r3, =_edata

+  adds r2, r0, r1

+  cmp r2, r3

+  bcc CopyDataInit

+  ldr r2, =_sbss

+  b LoopFillZerobss

+/* Zero fill the bss segment. */

+FillZerobss:

+  movs r3, #0

+  str  r3, [r2]

+  adds r2, r2, #4

+

+

+LoopFillZerobss:

+  ldr r3, = _ebss

+  cmp r2, r3

+  bcc FillZerobss

+

+/* Call the clock system intitialization function.*/

+  bl  SystemInit

+/* Call static constructors */

+//  bl __libc_init_array

+/* Call the application's entry point.*/

+  bl main

+

+LoopForever:

+    b LoopForever

+

+

+.size Reset_Handler, .-Reset_Handler

+

+/**

+ * @brief  This is the code that gets called when the processor receives an

+ *         unexpected interrupt.  This simply enters an infinite loop, preserving

+ *         the system state for examination by a debugger.

+ *

+ * @param  None

+ * @retval : None

+*/

+    .section .text.Default_Handler,"ax",%progbits

+Default_Handler:

+Infinite_Loop:

+  b Infinite_Loop

+  .size Default_Handler, .-Default_Handler

+/******************************************************************************

+*

+* The minimal vector table for a Cortex M0.  Note that the proper constructs

+* must be placed on this to ensure that it ends up at physical address

+* 0x0000.0000.

+*

+******************************************************************************/

+   .section .isr_vector,"a",%progbits

+  .type g_pfnVectors, %object

+  .size g_pfnVectors, .-g_pfnVectors

+

+

+g_pfnVectors:

+  .word  _estack

+  .word  Reset_Handler

+  .word  NMI_Handler

+  .word  HardFault_Handler

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  SVC_Handler

+  .word  0

+  .word  0

+  .word  PendSV_Handler

+  .word  SysTick_Handler

+  .word  WWDG_IRQHandler                   /* Window WatchDog              */

+  .word  0                                 /* Reserved                     */

+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */

+  .word  FLASH_IRQHandler                  /* FLASH                        */

+  .word  RCC_IRQHandler                    /* RCC                          */

+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */

+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */

+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */

+  .word  0                                 /* Reserved                     */

+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */

+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */

+  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */

+  .word  ADC1_IRQHandler                   /* ADC1                         */

+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */

+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */

+  .word  0                                 /* Reserved                     */

+  .word  TIM3_IRQHandler                   /* TIM3                         */

+  .word  0                                 /* Reserved                     */

+  .word  0                                 /* Reserved                     */

+  .word  TIM14_IRQHandler                  /* TIM14                        */

+  .word  0                                 /* Reserved                     */

+  .word  TIM16_IRQHandler                  /* TIM16                        */

+  .word  TIM17_IRQHandler                  /* TIM17                        */

+  .word  I2C1_IRQHandler                   /* I2C1                         */

+  .word  0                                 /* Reserved                     */

+  .word  SPI1_IRQHandler                   /* SPI1                         */

+  .word  0                                 /* Reserved                     */

+  .word  USART1_IRQHandler                 /* USART1                       */

+  .word  0                                 /* Reserved                     */

+  .word  0                                 /* Reserved                     */

+  .word  0                                 /* Reserved                     */

+  .word  0                                 /* Reserved                     */

+

+/*******************************************************************************

+*

+* Provide weak aliases for each Exception handler to the Default_Handler.

+* As they are weak aliases, any function with the same name will override

+* this definition.

+*

+*******************************************************************************/

+

+  .weak      NMI_Handler

+  .thumb_set NMI_Handler,Default_Handler

+

+  .weak      HardFault_Handler

+  .thumb_set HardFault_Handler,Default_Handler

+

+  .weak      SVC_Handler

+  .thumb_set SVC_Handler,Default_Handler

+

+  .weak      PendSV_Handler

+  .thumb_set PendSV_Handler,Default_Handler

+

+  .weak      SysTick_Handler

+  .thumb_set SysTick_Handler,Default_Handler

+

+  .weak      WWDG_IRQHandler

+  .thumb_set WWDG_IRQHandler,Default_Handler

+

+  .weak      RTC_IRQHandler

+  .thumb_set RTC_IRQHandler,Default_Handler

+

+  .weak      FLASH_IRQHandler

+  .thumb_set FLASH_IRQHandler,Default_Handler

+

+  .weak      RCC_IRQHandler

+  .thumb_set RCC_IRQHandler,Default_Handler

+

+  .weak      EXTI0_1_IRQHandler

+  .thumb_set EXTI0_1_IRQHandler,Default_Handler

+

+  .weak      EXTI2_3_IRQHandler

+  .thumb_set EXTI2_3_IRQHandler,Default_Handler

+

+  .weak      EXTI4_15_IRQHandler

+  .thumb_set EXTI4_15_IRQHandler,Default_Handler

+

+  .weak      DMA1_Channel1_IRQHandler

+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler

+

+  .weak      DMA1_Channel2_3_IRQHandler

+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler

+

+  .weak      DMA1_Channel4_5_IRQHandler

+  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler

+

+  .weak      ADC1_IRQHandler

+  .thumb_set ADC1_IRQHandler,Default_Handler

+

+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler

+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler

+

+  .weak      TIM1_CC_IRQHandler

+  .thumb_set TIM1_CC_IRQHandler,Default_Handler

+

+  .weak      TIM3_IRQHandler

+  .thumb_set TIM3_IRQHandler,Default_Handler

+

+  .weak      TIM14_IRQHandler

+  .thumb_set TIM14_IRQHandler,Default_Handler

+

+  .weak      TIM16_IRQHandler

+  .thumb_set TIM16_IRQHandler,Default_Handler

+

+  .weak      TIM17_IRQHandler

+  .thumb_set TIM17_IRQHandler,Default_Handler

+

+  .weak      I2C1_IRQHandler

+  .thumb_set I2C1_IRQHandler,Default_Handler

+

+  .weak      SPI1_IRQHandler

+  .thumb_set SPI1_IRQHandler,Default_Handler

+

+  .weak      USART1_IRQHandler

+  .thumb_set USART1_IRQHandler,Default_Handler

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

diff --git a/driver_fw/system_stm32f0xx.c b/driver_fw/system_stm32f0xx.c
new file mode 100644
index 0000000..a43c3d6
--- /dev/null
+++ b/driver_fw/system_stm32f0xx.c
@@ -0,0 +1,336 @@
+/**

+  ******************************************************************************

+  * @file    system_stm32f0xx.c

+  * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates

+  * @author  MCD Application Team

+  * @version V2.3.1

+  * @date    04-November-2016

+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.

+  *

+  * 1. This file provides two functions and one global variable to be called from

+  *    user application:

+  *      - SystemInit(): This function is called at startup just after reset and 

+  *                      before branch to main program. This call is made inside

+  *                      the "startup_stm32f0xx.s" file.

+  *

+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

+  *                                  by the user application to setup the SysTick

+  *                                  timer or configure other parameters.

+  *

+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

+  *                                 be called whenever the core clock is changed

+  *                                 during program execution.

+  *

+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.

+  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to

+  *    configure the system clock before to branch to main program.

+  *

+  * 3. This file configures the system clock as follows:

+  *=============================================================================

+  *                         Supported STM32F0xx device

+  *-----------------------------------------------------------------------------

+  *        System Clock source                    | HSI

+  *-----------------------------------------------------------------------------

+  *        SYSCLK(Hz)                             | 8000000

+  *-----------------------------------------------------------------------------

+  *        HCLK(Hz)                               | 8000000

+  *-----------------------------------------------------------------------------

+  *        AHB Prescaler                          | 1

+  *-----------------------------------------------------------------------------

+  *        APB1 Prescaler                         | 1

+  *-----------------------------------------------------------------------------

+  *=============================================================================

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  *

+  * Redistribution and use in source and binary forms, with or without modification,

+  * are permitted provided that the following conditions are met:

+  *   1. Redistributions of source code must retain the above copyright notice,

+  *      this list of conditions and the following disclaimer.

+  *   2. Redistributions in binary form must reproduce the above copyright notice,

+  *      this list of conditions and the following disclaimer in the documentation

+  *      and/or other materials provided with the distribution.

+  *   3. Neither the name of STMicroelectronics nor the names of its contributors

+  *      may be used to endorse or promote products derived from this software

+  *      without specific prior written permission.

+  *

+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS

+  * @{

+  */

+

+/** @addtogroup stm32f0xx_system

+  * @{

+  */

+

+/** @addtogroup STM32F0xx_System_Private_Includes

+  * @{

+  */

+

+#include "stm32f0xx.h"

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_Defines

+  * @{

+  */

+#if !defined  (HSE_VALUE) 

+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.

+                                                This value can be provided and adapted by the user application. */

+#endif /* HSE_VALUE */

+

+#if !defined  (HSI_VALUE)

+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.

+                                                This value can be provided and adapted by the user application. */

+#endif /* HSI_VALUE */

+

+#if !defined (HSI48_VALUE)

+#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.

+                                                 This value can be provided and adapted by the user application. */

+#endif /* HSI48_VALUE */

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_Variables

+  * @{

+  */

+  /* This variable is updated in three ways:

+      1) by calling CMSIS function SystemCoreClockUpdate()

+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()

+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency

+         Note: If you use this function to configure the system clock there is no need to

+               call the 2 first functions listed above, since SystemCoreClock variable is 

+               updated automatically.

+  */

+uint32_t SystemCoreClock = 8000000;

+

+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F0xx_System_Private_Functions

+  * @{

+  */

+

+/**

+  * @brief  Setup the microcontroller system.

+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.

+  * @param  None

+  * @retval None

+  */

+void SystemInit(void)

+{

+  /* Reset the RCC clock configuration to the default reset state ------------*/

+  /* Set HSION bit */

+  RCC->CR |= (uint32_t)0x00000001U;

+

+#if defined (STM32F051x8) || defined (STM32F058x8)

+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */

+  RCC->CFGR &= (uint32_t)0xF8FFB80CU;

+#else

+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */

+  RCC->CFGR &= (uint32_t)0x08FFB80CU;

+#endif /* STM32F051x8 or STM32F058x8 */

+  

+  /* Reset HSEON, CSSON and PLLON bits */

+  RCC->CR &= (uint32_t)0xFEF6FFFFU;

+

+  /* Reset HSEBYP bit */

+  RCC->CR &= (uint32_t)0xFFFBFFFFU;

+

+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */

+  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;

+

+  /* Reset PREDIV[3:0] bits */

+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;

+

+#if defined (STM32F072xB) || defined (STM32F078xx)

+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;

+#elif defined (STM32F071xB)

+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;

+#elif defined (STM32F091xC) || defined (STM32F098xx)

+  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;

+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)

+  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;

+#elif defined (STM32F051x8) || defined (STM32F058xx)

+  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;

+#elif defined (STM32F042x6) || defined (STM32F048xx)

+  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;

+#elif defined (STM32F070x6) || defined (STM32F070xB)

+  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */

+  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;

+  /* Set default USB clock to PLLCLK, since there is no HSI48 */

+  RCC->CFGR3 |= (uint32_t)0x00000080U;  

+#else

+ #warning "No target selected"

+#endif

+

+  /* Reset HSI14 bit */

+  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;

+

+  /* Disable all interrupts */

+  RCC->CIR = 0x00000000U;

+

+}

+

+/**

+   * @brief  Update SystemCoreClock variable according to Clock Register Values.

+  *         The SystemCoreClock variable contains the core clock (HCLK), it can

+  *         be used by the user application to setup the SysTick timer or configure

+  *         other parameters.

+  *

+  * @note   Each time the core clock (HCLK) changes, this function must be called

+  *         to update SystemCoreClock variable value. Otherwise, any configuration

+  *         based on this variable will be incorrect.

+  *

+  * @note   - The system frequency computed by this function is not the real

+  *           frequency in the chip. It is calculated based on the predefined

+  *           constant and the selected clock source:

+  *

+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)

+  *

+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)

+  *

+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)

+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.

+  *

+  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value

+  *             8 MHz) but the real value may vary depending on the variations

+  *             in voltage and temperature.

+  *

+  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value

+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real

+  *              frequency of the crystal used. Otherwise, this function may

+  *              have wrong result.

+  *

+  *         - The result of this function could be not correct when using fractional

+  *           value for HSE crystal.

+  *

+  * @param  None

+  * @retval None

+  */

+void SystemCoreClockUpdate (void)

+{

+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;

+

+  /* Get SYSCLK source -------------------------------------------------------*/

+  tmp = RCC->CFGR & RCC_CFGR_SWS;

+

+  switch (tmp)

+  {

+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */

+      SystemCoreClock = HSI_VALUE;

+      break;

+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */

+      SystemCoreClock = HSE_VALUE;

+      break;

+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */

+      /* Get PLL clock source and multiplication factor ----------------------*/

+      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;

+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

+      pllmull = ( pllmull >> 18) + 2;

+      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;

+

+      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)

+      {

+        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */

+        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;

+      }

+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)

+      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)

+      {

+        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */

+        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;

+      }

+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */

+      else

+      {

+#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \

+ || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \

+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)

+        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */

+        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;

+#else

+        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */

+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;

+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 

+          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||

+          STM32F091xC || STM32F098xx || STM32F030xC */

+      }

+      break;

+    default: /* HSI used as system clock */

+      SystemCoreClock = HSI_VALUE;

+      break;

+  }

+  /* Compute HCLK clock frequency ----------------*/

+  /* Get HCLK prescaler */

+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

+  /* HCLK clock frequency */

+  SystemCoreClock >>= tmp;

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+