Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2017-08-22 | Add profiling script | jaseg | 2 | -0/+31 | |
2017-08-15 | Benchmark code | jaseg | 2 | -7/+24 | |
2017-08-15 | working commit | jaseg | 3 | -19/+60 | |
2017-08-15 | Temporary for bit shuffling | jaseg | 1 | -11/+5 | |
2017-08-15 | Working on uart code | jaseg | 2 | -35/+147 | |
2017-08-14 | Multiplexing is working | jaseg | 3 | -65/+166 | |
2017-08-13 | Board rev 0.3 working | jaseg | 1 | -12/+45 | |
2017-07-21 | Second production run, v0.3 | jaseg | 15 | -8822/+9494 | |
2017-07-21 | Final silk art positioning | jaseg | 12 | -111925/+111925 | |
2017-07-20 | Add missing firmware build files | jaseg | 2 | -0/+286 | |
2017-07-20 | Second board revision | jaseg | 16 | -160767/+167539 | |
2017-07-15 | Schematic fixed up so far | jaseg | 13 | -3006/+3496 | |
2017-06-12 | Add resistor calculation script | jaseg | 2 | -22/+149 | |
2017-06-11 | Test program working | jaseg | 1 | -30/+54 | |
2017-06-10 | fw working commit | jaseg | 8 | -0/+802 | |
2017-06-10 | foo | jaseg | 12 | -1689/+1542 | |
2017-05-17 | Release v0.2 | jaseg | 28 | -17464/+18529 | |
2017-05-04 | Design mostly done | jaseg | 52 | -4218/+351132 | |
2017-05-02 | Layout mostly done | jaseg | 10 | -1139/+6297 | |
2017-04-30 | Foo | jaseg | 6 | -4957/+4778 | |
2017-04-29 | Pre safety fixup | jaseg | 8 | -1438/+7443 | |
2017-04-28 | Added protection stuff | jaseg | 5 | -2518/+4612 | |
2017-04-26 | Initial commit | jaseg | 19 | -0/+12924 | |