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2017-09-01DMA channel assignments redone, basic protocol stuff workingjaseg3-34/+121
2017-08-24Serial protocol now working including CRCjaseg2-9/+37
2017-08-23Interrupt-driven SPI1 fundamentally workingjaseg1-44/+78
2017-08-23Comms working except for TIM3/SPI1 racejaseg2-6/+17
2017-08-23Add cmsis export generatorjaseg2-0/+32
2017-08-23Add transpose testjaseg6-129/+280
2017-08-22Add profiling scriptjaseg2-0/+31
2017-08-15Benchmark codejaseg2-7/+24
2017-08-15working commitjaseg3-19/+60
2017-08-15Temporary for bit shufflingjaseg1-11/+5
2017-08-15Working on uart codejaseg2-35/+147
2017-08-14Multiplexing is workingjaseg3-65/+166
2017-08-13Board rev 0.3 workingjaseg1-12/+45
2017-07-21Second production run, v0.3jaseg15-8822/+9494
2017-07-21Final silk art positioningjaseg12-111925/+111925
2017-07-20Add missing firmware build filesjaseg2-0/+286
2017-07-20Second board revisionjaseg16-160767/+167539
2017-07-15Schematic fixed up so farjaseg13-3006/+3496
2017-06-12Add resistor calculation scriptjaseg2-22/+149
2017-06-11Test program workingjaseg1-30/+54
2017-06-10fw working commitjaseg8-0/+802
2017-06-10foojaseg12-1689/+1542
2017-05-17Release v0.2jaseg28-17464/+18529
2017-05-04Design mostly donejaseg52-4218/+351132
2017-05-02Layout mostly donejaseg10-1139/+6297
2017-04-30Foojaseg6-4957/+4778
2017-04-29Pre safety fixupjaseg8-1438/+7443
2017-04-28Added protection stuffjaseg5-2518/+4612
2017-04-26Initial commitjaseg19-0/+12924